Eric Blasko Dr. Tong Yu CSE310 digital logic Spring 2018 Homework 3, due 5/14/2018 ( Mon ) 12 pm 1. (15 points) Write a Verilog program that simulates the outputs of graycodetobinarycode converter. First write a module named GBC which takes w, x, y, z as inputs and a, b, c, d as outputs. Then write a test bench module named bcd_tb to test the GBC module. Compile and run your program and show the outputs for all 16 combinations of w, x, y, z. Module GBC module GBC(output a,b,c,d, input W,X,Y,Z); wire T1,T2; assign a = W; xor G1 (T1,W,X); assign b = T1; xor G2 (T2,T1,Y); assign c = T2; xor G3 (d,t2,z); Endmodule Test Bench module bcd_tb(); reg W,X,Y,Z; output wire a,b,c,d; initial begin $display("time\t W X Y Z a b c d"); $monitor("%g\t %b %b %b %b %b %b %b %b", $time, W,X,Y,Z,a,b,c,d); end initial begin W=0; X=0; Y=0; Z=0; #160 $finish; end always #10 Z=~Z; always #20 Y=~Y; always #40 X=~X;
always #80 W=~W; GBC test(a,b,c,d,w,x,y,z); Endmodule Output time W X Y Z a b c d 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 20 0 0 1 0 0 0 1 1 30 0 0 1 1 0 0 1 0 40 0 1 0 0 0 1 1 1 50 0 1 0 1 0 1 1 0 60 0 1 1 0 0 1 0 0 70 0 1 1 1 0 1 0 1 80 1 0 0 0 1 1 1 1 90 1 0 0 1 1 1 1 0 100 1 0 1 0 1 1 0 0 110 1 0 1 1 1 1 0 1 120 1 1 0 0 1 0 0 0 130 1 1 0 1 1 0 0 1 140 1 1 1 0 1 0 1 1 150 1 1 1 1 1 0 1 0 [005670557@csusb.edu@jb3598 hw3]$ 2. ( 20 points ) First write a Verilog module that implements a 2x1 MUX (multiplexer) and a module that implements 4x1 MUX using 2x1 MUX. Add an extra input port enable to the 4x1 MUX and 2x1 MUX. Then write another module that implements 8x1 MUX using two 4x1 MUX with enable ports and an or gate. Draw a diagram to show how this is done. Also write test bench programs to test all the multiplexer modules. Module for mux2x1, mux4x1 and mux8x1 module mux2x1(output out,input A,B, sel,enable); reg out; always @(A,B,sel,enable) begin if(enable == 0) out = 0; else if(sel == 0) out = A; else out = B; end
endmodule module mux4x1(output out, input A, B, C, D, input s1,s2,input enable); wire T1, T2; mux2x1 mul2x10(t1,a,b,s1,enable), mul2x11(t2,c,d,s1,enable), mul2x12(out,t1,t2,s2,enable); endmodule module mux8x1(output out, input [7:0] A, input [1:0] sel,input enable); wire T1, T2; mux4x1 mux4x10(t1,a[0],a[1],a[2],a[3],sel[0],sel[1],~enable), mux4x11(t2,a[4],a[5],a[6],a[7],sel[0],sel[1],enable); or G1(out,T1,T2); Endmodule Test Bench for 2x1 mux module test(); reg A, B; reg sel; reg enable; wire out; mux2x1 uut (.out(out),.a(a),.b(b),.sel(sel),.enable(enable)); initial begin $display("time\t A1 A2 sel enable out"); $monitor("%g\t %b %b %b %b %b", $time,a,b,sel,enable,out); end initial begin A=0; B=0; sel = 0; enable = 0; #160 $finish; end always #10 B = ~B; always #20 A = ~A;
always #40 sel=~sel; always #80 enable=~enable; Endmodule 2x1 mux Output time A1 A2 sel enable out 0 0 0 0 0 0 10 0 1 0 0 0 20 1 0 0 0 0 30 1 1 0 0 0 40 0 0 1 0 0 50 0 1 1 0 0 60 1 0 1 0 0 70 1 1 1 0 0 80 0 0 0 1 0 90 0 1 0 1 0 100 1 0 0 1 1 110 1 1 0 1 1 120 0 0 1 1 0 130 0 1 1 1 1 140 1 0 1 1 0 150 1 1 1 1 1 160 0 0 0 0 0 [005670557@csusb.edu@jb3598 hw3]$ Test Bench for 4x1 module test(); reg A,B,C,D; reg s1,s2; reg enable; wire out; mux4x1 uut (.out(out),.a(a),.b(b),.c(c),.d(d),.s1(s1),.s2(s2),.enable(enable )); initial begin $display("time\t A1 A2 A3 A4 sel1 sel2 enable out"); $monitor("%g\t %b %b %b %b %b %b %b %b", $time,a,b,c,d,s1,s2,enable,out); end
initial begin A = 0; B = 0; C = 0; D = 0; s1 = 0; s2 = 0; enable = 1; #10 A = 1; B = 0; C = 0; D = 0; s1 = 0; s2 = 0; enable = 1; #10 A = 1; B = 0; C = 0; D = 0; s1 = 1; s2 = 0; enable = 1; #10 A = 1; B = 1; C = 0; D = 0; s1 = 1; s2 = 0; enable = 1; #10 A = 1; B = 0; C = 0; D = 0; s1 = 0; s2 = 1; enable = 1; #10 A = 1; B = 0; C = 1; D = 0; s1 = 0; s2 = 1; enable = 1; #10 A = 1; B = 0; C = 0; D = 0; s1 = 1; s2 = 1; enable = 1; #10 A = 1; B = 0; C = 0; D = 1; s1 = 1; s2 = 1; enable = 1; #10 A = 1; B = 0; C = 0; D = 0; s1 = 0; s2 = 0; enable = 0; #10 A = 0; B = 1; C = 0; D = 0; s1 = 1; s2 = 0; enable = 0; #10 A = 1; B = 0; C = 1; D = 0; s1 = 0; s2 = 1; enable = 0; #10 A = 1; B = 0; C = 0; D = 1; s1 = 1; s2 = 1; enable = 0; #10 $finish; end Endmodule Output for 4x1 time A1 A2 A3 A4 sel1 sel2 enable out 0 0 0 0 0 0 0 1 0 10 1 0 0 0 0 0 1 1 20 1 0 0 0 1 0 1 0 30 1 1 0 0 1 0 1 1 40 1 0 0 0 0 1 1 0 50 1 0 1 0 0 1 1 1 60 1 0 0 0 1 1 1 0 70 1 0 0 1 1 1 1 1 80 1 0 0 0 0 0 0 0 90 0 1 0 0 1 0 0 0 100 1 0 1 0 0 1 0 0 110 1 0 0 1 1 1 0 0 [005670557@csusb.edu@jb3598 hw3]$ 8x1 mux diagram
Test Bench for 8x1 mux module test(); reg [7:0] A; reg [1:0] sel; reg enable; wire out; mux8x1 uut (.out(out),.a(a),.sel(sel),.enable(enable)); initial begin $display("time\t A0 A1 A2 A3 A4 A5 A6 A7 sel1 sel2 enable out"); $monitor("%g\t %b %b %b %b %b %b %b %b %b %b %b %b", $time,a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7],sel[0],sel[1],enabl e,out); end initial begin A = 8'b00010001; sel = 2'b00; enable = 1; #10 A = 8'b00010001; sel = 2'b00; enable = 0; #10 A = 8'b11101110; sel = 2'b00; enable = 1;
#10 A = 8'b11101110; sel = 2'b00; enable = 0; #10 A = 8'b00100010; sel = 2'b01; enable = 1; #10 A = 8'b00100010; sel = 2'b01; enable = 0; #10 A = 8'b11011101; sel = 2'b01; enable = 1; #10 A = 8'b11011101; sel = 2'b01; enable = 0; #10 A = 8'b01000100; sel = 2'b10; enable = 1; #10 A = 8'b01000100; sel = 2'b10; enable = 0; #10 A = 8'b10111011; sel = 2'b10; enable = 1; #10 A = 8'b10111011; sel = 2'b10; enable = 0; #10 A = 8'b10001000; sel = 2'b11; enable = 1; #10 A = 8'b10001000; sel = 2'b11; enable = 0; #10 A = 8'b01110111; sel = 2'b11; enable = 1; #10 A = 8'b01110111; sel = 2'b11; enable = 0; #10 $finish; end Endmodule Output for 8x1 mux time A0 A1 A2 A3 A4 A5 A6 A7 sel1 sel2 enable out 0 1 0 0 0 1 0 0 0 0 0 1 1 10 1 0 0 0 1 0 0 0 0 0 0 1 20 0 1 1 1 0 1 1 1 0 0 1 0 30 0 1 1 1 0 1 1 1 0 0 0 0 40 0 1 0 0 0 1 0 0 1 0 1 1 50 0 1 0 0 0 1 0 0 1 0 0 1 60 1 0 1 1 1 0 1 1 1 0 1 0 70 1 0 1 1 1 0 1 1 1 0 0 0 80 0 0 1 0 0 0 1 0 0 1 1 1 90 0 0 1 0 0 0 1 0 0 1 0 1 100 1 1 0 1 1 1 0 1 0 1 1 0 110 1 1 0 1 1 1 0 1 0 1 0 0 120 0 0 0 1 0 0 0 1 1 1 1 1 130 0 0 0 1 0 0 0 1 1 1 0 1 140 1 1 1 0 1 1 1 0 1 1 1 0 150 1 1 1 0 1 1 1 0 1 1 0 0 [005670557@csusb.edu@jb3598 hw3]$ 3. ( 10 points) Watch the video Differences between reg and wire (with caption) and answer the following questions: a. The following syntax is correct. True or false? Why? wire a, b; always @ ( b ) a = b;
This syntax is not correct, so it is false. Wire elements cannot store values and cannot be on the lefthand side of assigning values in an always@ block. If it was not inside an always@ block it would only be legal on the lefthand side of an assign statement. b. The following syntax is correct. True or false? Why? reg a, b; assign a = b; This syntax is not correct, so it is false. Reg cannot be used on the lefthand side of an assign statement. It is however legal on the lefthand side of an always@ block and initial block. c. Wire elements can only be used to model combinational circuits. True or false? Why? True. In a combination circuit, the logic circuit operation is instantaneous as its output is a pure function of the present inputs only. This is because there is not memory in a combinational circuit because wire elements do not have memory. A reg on the other hand can be used in both combinational circuits and sequential logic. d. What are the values of a, b, c after execution of the following code segment? Why? reg [3:0] a; reg [3:0] b; reg [3:0] c; initial begin a = 1; b = 2; c = 0; a = b; c = a + 1; end Outputs will be a=2, b=2, c=3. Since this is a blocking assignment, each statement will be performed in sequence and since each variable is a reg, it will store the values. After the first three statements a=1,b=2, and c=0. When a=b is called, it copies the value of b into a, which is 2. When c=a+1 is called its performing 2+1 = 3 and stores that into c e. What are the values of a, b, c after execution of the following code segment? Why? reg [3:0] a; reg [3:0] b; reg [3:0] c; initial begin a = 1; b = 2;
c = 0; a <= b; c <= a + 1; end Outputs are a=2, b=2, and c=2. This is because the last two statements are nonblocking assignments. This means both a<=b and c<=a+1 are done at the same exact time. So as a is assigned 2 from be, c is being assigned the value were a=1 plus 1. The following are multiple choice questions. Each worth 5 points. Please show your steps in arriving at the answers. 4. Find the POS expression equivalent of the following. AB + CD + AC' + DE' A. (A+D)(B+C'+D)(A+C+E') B. (A+B)(C+D)(A+C')(D+E') C. (A+B+C)(C'+D+E') D. (A+D)(B+C'+D)(A+C+E')(B+C'+E') E. none of the above F = AB + CD + AC + DE F = (AB + CD + AC + DE ) F = (A +B )(C D )(A C)(D E) F = (A +B C)(D +C E) F = A D +A C E + B CD + B CC E F = A D +A C E + B CD + 0 F = (A D +A C E + B CD ) F = (A+D)(B+C +D)(A+C+E ) A is the correct answer 5. The addersubtractor is used to subtract the following unsigned 4bit numbers : 0110 1010 ( 6 10 ). What are the input binary values of A, B and M? Choose 3. A. 0110 B. 1010 C. 1 D. 0 E. 0101 the initial value of A will be 0110 and the initial value of B will be 1010. Since they are being subtracted m=1. These are the values before any logical gates. A, B, and C are the correct answers
6. In the previous question, what are the output binary values of S and C 5? Choose two. A. 1100 B. 0100 C. 1011 D. 0 E. 1 Table to solve. Each xor gate will complement the b inputs A B C c s At first adder 0 1 1 1 0 Second adder 1 0 1 1 0 Third adder 1 1 1 1 1 Four adder 0 0 1 0 1 A and D are the correct answer. 7. Suppose we design a decimal adder for two digits represented in the excess3 code. Which of the following regarding the correction after adding the two digits with a 4bit binary adder is/are right? A. The output carry is equal to the carry from the binary adder. B. If the output carry = 0, then add 0011 C. If the output carry = 1, then add 0011 D. If the output carry = 0, then add 1101 E. If the output carry = 1, then add 1101 Which of the four groups have produced carry = 1, then we must add 0011 to them. Else carry = 0 then we must subtract 0011 from them which is equivalent to adding the 2s complement of 0011 which is 1101. C and D are the correct answers 8. Manipulate the following Boolean expression in such a way that it can be implemented using exclusiveor and AND gates only. WX'YZ' + W'XYZ' + WX'Y'Z + W'XY'Z A. WX YZ B. W X Y Z C. WX' YZ' D. (W X)(Y Z) E. (W X)(Y Z)'
WX'YZ' + W'XYZ' + WX'Y'Z + W'XY'Z YZ (WX +W X) + Y Z(WX +W X) (YZ (1) + Y Z(1))(WX +W X) (YZ + Y Z)(WX +W X) (Y Z) (W X) D is the correct answer Score (70/70) For this homework assignment, I have demonstrated my knowledge of Verilog by producing a Grey code to binary converter and a working 2x1,4x1, and 8x1 mux module. In both programs I have verified my outputs with truth tables to make sure that the input is correct. My stimulus for the mux test benches show test cases for when 0 and 1 should be outputs based on inputs. In the 4x1 mux, you can see that my stimulus shows values where the output would be one. The same cases with a switched enable however produced a 0 output as intended. This is because when enable is 0, the output from the mux should also be 0. In the 8x1 mux one 4x1 mux while have enable as 1, while the other with receive the complement of enable. This is because only one mux should be sending output which the other is 0. The or gate simplifies the two to a single output. For the third part, all the answers could be found from the video. I used Verilog myself to test all of the cases to see how Verilog provides exceptions. For the last parts, I believe I did them all correctly and showed my work as proof of working each one out.