Challenges of Integration of Complex FHE Systems Nancy Stoffel GE Global Research
Products drive requirements to sub-systems, components and electronics GE PRODUCTS CTQs: SWaP, $$, operating environment, life SYSTEMS & COMPONENTS CTQs: Efficiency, Torque, life, operating environment, stresses, etc. PACKAGING TECHNOLOGY CTQs: Size, power, communication, Heat Flux Density
Flexible Hybrid Electronics Devices CMOS, MEMS, InP, GaAs, SiC Flexible Substrate New Materials & Processes Low cost Mfg methods FHE microsystem integration methods New Products Existing Products: New functionality via form factor, robustness etc New types of products
Interest in Wearables for Health Care From ICU to General Ward to Homecare 1. Traditional vital sign From monitoring: ICU to General Ward to H Wirefree Reduce cost and footprint o Comfort wearable devices- disposa Disposable 2. Implement New patient monitoring and develop ne parameters- sensors hydration Patient Experience Drives Requirements for : Wirefree monitoring Comfort on skin Reliable monitoring Comfortable form factor Disposable for infection control Battery, power management, RF communication, antenna, communication infrastructure in hospital or other setting New substrates: soft Robust sensor connection to patient, Data communication rates, signal fidelity, robust signal processing Miniaturization, thin devices or device packages, body attachment methods Low cost mfg methods, materials choices, product life cycle studies, Regulatory issues
FHE Elements for Monitoring System Sense Mechanical Thermal chemical Biological Opticalelectrical Power Process Signal Processing A/D Memory Communicat e Wireless Near Field User Display
Promise of Asset Monitoring Condition based monitoring of machine or structure to gain max productivity, performance and safety Requirements: Low profile on structure so as not to interfere with function Robust Attachment techniques to machine, tool or asset Energy Management: may require remote power sources Will be relatively low volume products Many applications are in harsh environments, and will require higher temperature sensor, substrates and interconnects
Simple Process Flow for Chip on Flex Based Flexible Hybrid Electronics Device Wafer UBM or Redistribution Layer Routing Device Preparation Wafer Thinning (optional) Device Singulation Packaging of device (optional) Thin Device Handling: Pick and Place Electrical Interconnect Encapsulation Flexible Circuit Preparation Integration Flex circuitization Lamination for multilayers Via formation Pad finish Challenges: Maximum Form Factor Reduction Requires Change in Packaging Approach to Chip Scale Package or Thin Bare Die New materials/methods for flex circuits are not compatible with standard methods of die attach/interconnect (thermal & surface finish) Dynamic flexing, chip on flex prone to die delamination and die cracking. CTE mismatch between substrate and film Some Substrates of interest for wearables lack dimensional stability Modification of methods will be necessary to meet all CTQs
1 3M ACF 5363 2 GaTech-PRC on rigid interposer 3-StatsChip Pac 4- i3 Integration done on PI 5-GE POL techno 6-Ormet Tech Overview May 2012 Interconnect method Make table Interconnections: new approaches Low T compatible (<150C) Die position Bond pad prep I/O PItch Flip Chip BGA No facedown Yes, RDL and solderable finsh Copper pillar thermocompression No facedown Solder tipped copper pillar Copper bumps/ pillars into NCP No facedown Solder tipped copper pillar Area Array 0.4-0.5 mm micro BGA: 0.25-0.3 mm Area array 20 um 2 70 um 4 on flex Area array 40/80 um 3 Anisotropic conductive adhesive Yes facedown Bump Area array 200 um 1 Printed Interconnect yes up No Perimeter 100 um Micro via direct plated connections yes facedown no Area Array 50 um 5 3D Compliant structures Yes facedown Copper cantilevers, springs transient liquid phase sintering adhesives TAB Yes? Up Yes, bondable metal Wire-bonding yes up Yes, bondable metal Area array facedown bump Area array 300 um 6 Perimeter Perimeter 30 um 45 um
Integrated Flex System In Package Technology for Wearables, Portable Devices and Power Conversion Miniaturization of Advanced packaging technology ideal for industrial & consumer electronics as well as high power and RF applications. Integration of Sensors, Microprocessors, Antenna, Passives on single or multilayer flex platform High-Capability & High-Reliability technology with proven performance under exceptional environments Unique flex-based interconnection technology forms a foundation for the high quality, high volume production process
GE Thin Profile POL Development Objective to extend POL technology to thin profile packages for FOWLP, SiP, and PoP applications. Focus on sub 200µm modules with conductor layers on one or both sides. Structure realized using thin (~50µm) die and 25 µm PI layers. Early test vehicles and reliability testing done. Current development focused on manufacturability and handling of thin modules as well as full package qualification.
Balanced core structure with equal material layers on both side of the module <10 um die warp Thin Profile POL Module target thicknesses (actual ~-4%) Soldermask 20µm Objective to extend POL technology to 12µm thin profile packages for FOWLP, SiP, 23µm and PoP applications. Adhesive 13µm Focus on sub 200µm modules with conductor layers on one or both sides. Die PI 50µm Structure realized using thin (~50µm) die and 25 µm PI layers. 13µm Early test vehicles PI and reliability 23µm testing done. Cu 12µm 20µm 186µm Current development focused on manufacturability and handling of thin modules as well as full package qualification.
Conclusions Development of FHE infrastructure offers opportunities for new product implementations Products will require integration of sensing, computing, communication Manufacturing materials, processes, infrastructure, reliability needs to be addressed within Next Flex Program.