Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators

Similar documents
Simulating the PCI MegaCore Function Behavioral Models

Simulating the Reed-Solomon Model

Simulating the PCI MegaCore Function Behavioral Models

UTOPIA Level 2 Slave MegaCore Function

PCI Express Compiler. System Requirements. New Features & Enhancements

Table 1 shows the issues that affect the FIR Compiler v7.1.

Introduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow

DSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path

DDR & DDR2 SDRAM Controller

Exercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.

DDR & DDR2 SDRAM Controller

Table 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues.

Simulating Excalibur Systems

Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor. 1 Introduction. For Quartus Prime 16.1

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler

DSP Builder Release Notes

White Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports

Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim

POS-PHY Level 4 MegaCore Function

AN 549: Managing Designs with Multiple FPGAs

DDR and DDR2 SDRAM Controller Compiler User Guide

ZBT SRAM Controller Reference Design

Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide

Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide

Simulating Nios II Embedded Processor Designs

DDR & DDR2 SDRAM Controller Compiler

Nios II Embedded Design Suite 7.1 Release Notes

CORDIC Reference Design. Introduction. Background

DSP Development Kit, Stratix II Edition

FFT MegaCore Function

FPGA Design Security Solution Using MAX II Devices

Simulating the ASMI Block in Your Design

Excalibur Solutions DPRAM Reference Design

FPGAs Provide Reconfigurable DSP Solutions

25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

White Paper Configuring the MicroBlaster Passive Serial Software Driver

RLDRAM II Controller MegaCore Function

Using Verplex Conformal LEC for Formal Verification of Design Functionality

Using VCS with the Quartus II Software

Video and Image Processing Suite

Low Latency 40G Ethernet Example Design User Guide

24K FFT for 3GPP LTE RACH Detection

Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide

Cadence NC-Verilog Simulator Tutorial. Product Version 5.1 September 2003

White Paper Using the MAX II altufm Megafunction I 2 C Interface

Using Simulator With Undertow Suite

FFT/IFFT Block Floating Point Scaling

Using the Serial FlashLoader With the Quartus II Software

Estimating Nios Resource Usage & Performance

Converting.srec Files to.flash Files for Nios Embedded Processor Applications

2. Mentor Graphics ModelSim and QuestaSim Support

FFT MegaCore Function User Guide

H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

2.5G Reed-Solomon II MegaCore Function Reference Design

White Paper AHB to Avalon & Avalon to AHB Bridges

RapidIO Physical Layer MegaCore Function

Low Latency 100G Ethernet Design Example User Guide

Toolflow for ARM-Based Embedded Processor PLDs

altshift_taps Megafunction User Guide

Debugging Nios II Systems with the SignalTap II Logic Analyzer

HPS SoC Boot Guide - Cyclone V SoC Development Kit

Matrices in MAX II & MAX 3000A Devices

Dynamic Reconfiguration of PMA Controls in Stratix V Devices

Nios II Embedded Design Suite 6.1 Release Notes

Stratix II vs. Virtex-4 Performance Comparison

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices

Cyclone II FPGA Family

Using MAX 3000A Devices as a Microcontroller I/O Expander

Arria II GX FPGA Development Board

ISE Simulator (ISim) In-Depth Tutorial. UG682 (v 13.1) March 1, 2011

December 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt

Supporting Custom Boards with DSP Builder

Active Serial Memory Interface

FPGA Co-Processing Architectures for Video Compression

White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices

Benefits of Embedded RAM in FLEX 10K Devices

100G Interlaken MegaCore Function User Guide

Implementing LED Drivers in MAX Devices

DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide

Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface

Nios DMA. General Description. Functional Description

SignalTap II with Verilog Designs. 1 Introduction. For Quartus II 13.1

Design Tools for 100,000 Gate Programmable Logic Devices

FFT MegaCore Function User Guide

MAX 10 User Flash Memory User Guide

Simple Excalibur System

PLD Design Flow: GAL, Verilog

Disassemble the machine code present in any memory region. Single step through each assembly language instruction in the Nios II application.

Intel Quartus Prime Pro Edition Software and Device Support Release Notes

POS-PHY Level 4 POS-PHY Level 3 Bridge Reference Design

Using ModelSim to Simulate Logic Circuits in VHDL Designs. 1 Introduction. For Quartus II 13.0

Legacy SDRAM Controller with Avalon Interface

Logic Optimization Techniques for Multiplexers

Figure 1. Device Package Ordering Information for Stratix, Stratix GX, Cyclone, APEX 20KC, APEX II, Mercury & Excalibur Devices EP1S 25 F 780 C 5 N

Mixed Signal Verification of an FPGA-Embedded DDR3 SDRAM Memory Controller using ADMS

AN423: Configuring the MicroBlaster Passive Serial Software Driver

Design Verification Using the SignalTap II Embedded

White Paper Understanding 40-nm FPGA Solutions for SATA/SAS

Transcription:

White Paper Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera intellectual property (IP) cores in third-party VHDL and Verilog HDL simulators. The following simulators support Visual IP models: Model Technology ModelSim, Cadence Leapfrog, Verilog-XL, NC-Verilog, and NC-VHDL, and Synopsys VCS and VSS. Altera distributes the Visual IP software for the end user and Visual IP models of Altera IP functions. This white paper describes how to use the Visual IP models with the NC-Verilog, Verilog-XL, VCS, and ModelSim simulators for UNIX workstations. System Requirements To run the Visual IP software, you need a UNIX workstation that meets the following system requirements: At least 32 MBytes of RAM Solaris 2.5.1 or higher At least 70 MBytes of free disk space At least 50 MBytes of swap space (more is required if your IP models are more complex) Overview Using the Visual IP models on UNIX workstations involves the following steps: 1. Download and install the Visual IP models you want to simulate. 2. Download and install the Visual IP End User software. 3. Set an environment variable pointing to the Visual IP models. 4. Run the Visual IP setup script. 5. Simulate with your simulation tool and the Visual IP models. 1. Download & Install the Visual IP Models You Want to Simulate Altera provides Visual IP models in two ways: included in a MegaCore function installation package or as a separate file. You can download both the core and the models (if provided separately) from the same download page on the Altera web site. To download and install the core and/or models, perform the following steps: 1. Point a web browser to http://www.altera.com/ipmegastore. 2. Enter the core name in the Keyword Search box of the IP MegaSearch area and click Submit. 3. Click the Try icon next to the MegaCore function you want to download. 4. Follow the on-line instructions to download the core and/or models and save them to your hard disk. 5. Refer to the core readme file and user guide for detailed installation instructions. 1 If the Visual IP models are provided as a separate file, a separate user guide is also provided. Refer to this user guide for instructions on how to install the models. Figure 1 shows the directory structure of an example MegaCore function that is packaged with Visual IP models. The figure explains where to find the Visual IP models used for various simulators. M-WP-VIPINSTALL-1.0 September 2001, ver. 1.0 1

Figure 1. Location of Visual IP Models MegaCore correlator-v1.0.0 (MegaCore installation directory) doc lib open_lib sim_lib modelsim visualip (Visual IP directory) aukcr_corr binaries docs interface leapfrog (Use this interface for NC-VHDL) mti (Use this interface for ModelSim SE only) pli (Use this interface for Verilog HDL simulators: Verilog-XL, NC-Verilog, VCS, and ModelSim PE) stand-alone visual vss... 2. Download & Install the Visual IP Software To download and install the software, perform the following steps: 1. Point your web browser to http://www.altera.com/products/ip/altera/visual_ip.html. 2. Follow the on-line instructions to download the software. 3. The Visual IP software for UNIX has been compressed using the gzip utility. Move the VIP_EndUser_<version><platform>.bin.gz file to the location in which you want to install the software. 4. Unzip the file. 5. Run the.bin file. 3. Set an Environment Variable Pointing to the Visual IP Models Before you can use the Visual IP models, you must create an environment variable that points to the location of the files. 1 The information presented here assumes that you are using the C shell. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. If a command is split over two lines, you should still enter it as a single line following the system prompt. 2

For Models Included as Part of a MegaCore Package If you downloaded and installed the Visual IP models as part of the MegaCore package, perform the following steps: 1. Refer to the directory structure information in the core user guide to determine in which directory the Visual IP models were installed. 2. Set an environment variable pointing to the directory you found in step 1 by typing the following command at a UNIX prompt: setenv VIP_MODELS_DIR /<path>/sim_lib/visualip r where <path> is where you installed the MegaCore function. For example: setenv VIP_MODELS_DIR /home/altera_user/megacore/reed-solomon/sim_lib/visualip r For Models Downloaded Separately If you downloaded the Visual IP models as a separate file, perform the following steps: 1. Change to your home or working directory, for example: cd /home/altera_user r 2. Create a directory for the Visual IP models: mkdir vip r 3. Set an environment variable pointing to the directory you made in step 2: setenv VIP_MODELS_DIR /home/altera_user/vip r 4. Run the Visual IP Setup Script Innoveda provides a setup script for setting the environment variables needed by the Visual IP software. To run the script, perform the following steps. 1 The information presented here assumes that you are using the C shell. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. v Enter the following command: source /<path>/vip_enduser_<version>/<platform>/bin/vip.setup r where <path> is the location in which you installed the Visual IP software, <version> is the Visual IP version, and <platform> is SunOS5 or hp10. For example: source /<path>/vip_enduser_43/sunos5/bin/vip.setup r 3

5. Simulate the Visual IP Models After you install the Visual IP software and models and set up your environment, you are ready to simulate. You can simulate using a single command or you can perform incremental compilation and simulation. 1 The information presented here assumes that you are using the C shell. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. If a command is split over two lines, you should still enter it as a single line following the system prompt. This white paper provides instructions for the following simulators: NC-Verilog Verilog-XL VCS ModelSim NC-Verilog The following section describes how to simulate using the NC-Verilog simulator. Simulate Using a Single Command The command to simulate is: ncverilog <path>/<model>.v <path>/<wrapper>.v <path>/<testbench>.v +debug +gui r 1 The +debug option allows read access of the model signals. The +gui option launches the graphical interface for viewing waveforms. Below is an example using the POS-PHY L2 L3 compiler models (which were installed separately into the /home/altera_user/vip directory) and the Altera-provided testbench and wrapper files (which were installed into the /MegaCore/POSPHY directory when the POS-PHY MegaCore function was installed). <path>/<model>.v (Altera-provided Visual IP model): /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v <path>/<wrapper>.v (either the.v file created by the MegaCore wizard or an Altera-supplied one): <path>/<testbench>.v (a testbench you have written or an Altera-supplied one): /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v Example command: ncverilog /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v +debug +gui r 4

To view the simulation in the user interface, perform the following steps: 1. Choose Navigator (Tools menu). 2. Double-click on the testbench filename (auk_pac_mrx_ref_tb.v in the example above). 3. Select all of the nets and registers. 4. Select the waveform view. 5. Click Run. 6. Zoom out to view the waveform. Perform Incremental Compilation & Simulation For incremental compilation and simulation, perform the following steps: 1. Create a simulation directory, for example: mkdir my_sim r 2. Change to the simulation directory: cd my_sim r 3. Create a working library directory in your simulation directory. For example: mkdir worklib r 4. Create a file named cds.lib in the my_sim directory that contains the following line: DEFINE worklib./worklib 5. Create a file named hdl.var in the my_sim directory that contains the following line: DEFINE work worklib 6. Parse the Verilog HDL source code: ncvlog <path>/<model>.v <path>/<wrapper>.v <path>/<testbench>.v r For example: ncvlog /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mtx_mw.v /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mtx_pl3_link.v /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mtx_ref_tb.v r 7. Elaborate the design (the rwc option read, write, connect is required if you want to see all of the signals later): ncelab worklib.auk_pac_mtx_ref -access +rwc -messages r 8. Simulate the design (the gui option launches the graphical interface for viewing the waveforms): ncsim worklib.auk_pac_mtx_ref -gui r 5

Verilog-XL The command to simulate is: verilog -s <path>/<model>.v <path>/<wrapper>.v <path>/<testbench>.v +debug +gui r 1 The -s option stops the simulator from completing simulation before you can open the waveform window to view the signal. The +debug option allows read access of the model signals. The +gui option launches the graphical interface for viewing waveforms. Below is an example using the POS-PHY L2 L3 compiler models (which were installed separately into the /home/altera_user/vip directory) and the Altera-provided testbench and wrapper files (which were installed into the /MegaCore/POSPHY directory when the POS-PHY MegaCore function was installed). <path>/<model>.v (Altera-provided Visual IP model): /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v <path>/<wrapper>.v (either the.v file created by the MegaCore wizard or an Altera-supplied one): <path>/<testbench>.v (a testbench you have written or an Altera-supplied one): /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v Example command: verilog -s /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v +debug +gui r VCS You can simulate using a single command and you need to link to the pli.tab and libvip_pli.a files provided with the Visual IP software. To simulate, use the following command: vcs -P <path>/pli.tab <path>/libvip_pli.a <path>/<model>.v <path>/<wrapper>.v <path>/<testbench>.v -RI r 1 The -RI option launches the interactive interface. Below is an example using the POS-PHY L2 L3 compiler models (which were installed separately into the /home/altera_user/vip directory) and the Altera-provided testbench and wrapper files (which were installed into the /MegaCore/POSPHY directory when the POS-PHY MegaCore function was installed). <path>/pli.tab: <installation path>/vip_enduser_43/sunos5/verilog_src/pli.tab <path>/libvip_pli.a: <installation path>/vip_enduser_43/sunos5/verilog_src/libvip_pli.a 6

<path>/<model>.v (Altera-provided Visual IP model): /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v <path>/<wrapper>.v (either the.v file created by the MegaCore wizard or an Altera-supplied one): <path>/<testbench>.v (a testbench you have written or an Altera-supplied one): /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v Example command: vcs -P <installation path>/vip_enduser_43/sunos5/verilog_src/pli.tab <installation path>/vip_enduser_43/sunos5/verilog_src/libvip_pli.a /home/altera_user/vip/auk_pac_mrx_mw/interface/pli/auk_pac_mrx_mw.v /MegaCore/POSPHY/sim_lib/testbench/verilog/auk_pac_mrx_ref_tb.v r ModelSim The PLI interface is used to instantiate the Visual IP models using Verilog HDL. To use the PLI interface, perform the following steps. If you want to instantiate the Visual IP models using VHDL, skip to step 6. 1 You must set a variable in the modelsim.ini file to use the ModelSim PLI interface. These instructions describe how to update your local copy of the modelsim.ini file in your working directory. 1. Create a local copy of the modelsim.ini file by performing the following steps: a. Create a new directory. b. Run the ModelSim software. c. Change to the new directory you created. d. Perform some action in the ModelSim software, e.g., change the compile options. ModelSim automatically creates a new modelsim.ini file in your working directory. e. Close ModelSim so that you do not inadvertently overwrite the modelsim.ini file. 2. Open the modelsim.ini file with a text editor. 3. Find the line that has the text string veriuser. 4. Change the line to point to the Visual IP libplimtivip file. For example: veriuser = <installation path>/vip_enduser_43/sunos5/lib/libplimtivip 5. Save the modelsim.ini file. 6. Compile the model, wrapper, and testbench (your own or an Altera-provided one). 7. Load the testbench. 8. Open the signal and waveform windows. 7

9. Select signals you wish to monitor. 10. Run the simulation. 1 Once the Visual IP model has been loaded, you must close ModelSim and then reopen it to restart the simulation or to load a different model. 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Copyright 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. 8

2024 © technodocbox.com Privacy Policy | Terms of Service | Feedback