Computer Architecture Topics: Machine Organization Machine Cycle Program Execution Machine Language Types of Memory & Access Von Neumann Design 1) Two key ideas 1) The stored program concept 1) instructions are represented in binary and stored, like data, in memory 2) Instructions are sequentially executed 2 Chapter 5 The Von Neumann Architecture 1
Data and programs are represented in binary Von Neumann design Stored program concept Instructions in binary to be interpreted as directly executable actions» Machine instruction set» Directly executable primitives ->circuits Sequential execution of instructions Fetch an instruction Decode the instruction Execute the instruction 7 The Von Neumann Architecture: A simple schematic 1. Random Access Memory 4. Input-Output Processor 1. (CPU) 2.Control unit 3.ALU 8 Chapter 5 The Von Neumann Architecture 4
9 Random Access Memory Two features Every memory cell has a unique address Takes the same amount of time to access every cell Unit of retrieval is the entire cell Memory Size = # memory cells 1 memory cell = 8 bits (1 byte) 1000 memory cells = 1000 bytes kilobyte 1 million memory cells megabyte (..1,048,576 = 2 20 ) 1 billion memory cells gigabyte ( 1,073741,824 = 2 30 ) 10 Chapter 5 The Von Neumann Architecture 5
Memory Address Memory Cells 20 bits to represent an address? -> 2 20 (1,048,576) unique patterns Can reference 1,048,576 memory cells address space 00000 00000 00000 01011 Cell 0 Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8 Cell 9 Cell 10 Cell 11 1 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 1 11 CPU s Control Unit Controls the basic machine cycle FETCH DECODE EXECUTE an instruction from RAM identify what primitive machine instruction it is activate appropriate circuits 12 Chapter 5 The Von Neumann Architecture 6
Basic Memory Operations between CPU and RAM : Fetch & Store Address Contents 00000101 00001111 Fetch (address) Fetch (00000101) nondestructive copy Store(address, value) Store (00000101, 00010000) destructive replacement e.g. set x to x + 1 13 Decomposing Fetch & Store: Memory Registers Address bus Data bus Memory Address Register 00000 00000 00000 00110 Memory Data Register 10000001 cell 0 1 2 00000 00000 00000 00110 2 n - 1 address 1 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 1 14 Chapter 5 The Von Neumann Architecture 7
Breaking down fetch and store MAR Memory decoder circuit F/S... MDR Fetch/Store controller Fetch(address) Load address into MAR. Decode the address in MAR. Copy the content of memory cell with specified address into MDR. Store(address, value) Load the address into MAR. Load the value into MDR. Decode the address in MAR Copy the content of MDR into memory cell with the specified address. 15 Decoding Memory Addresses: a 4-bit example (simplified - 1 dimensional) 0 0 1 1 4 to 16 bit decoder circuit Line 0 line 3... 1 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 0 1 Line 15 16 Chapter 5 The Von Neumann Architecture 8
Overall RAM Organization MAR Memory Cells CPU Decoding Circuits Fetch-Store Signal MDR Fetch- Store Controller 17 Size (width) of Address Bus in bits must map to address space Address Bus/Data Bus if address space = 2 n, then address bus is n bits wide Size (width) of Data bus Single unit of modification is the memory cell but multiple memory cell contents moved to/from CPU width of data bus = size of MDR (typically 16, 32) word size 18 Chapter 5 The Von Neumann Architecture 9
Instructions have a binary representation Programs = instructions implemented in control unit as circuits E.g. Add circuit test-for-equality circuit Representing instructions in binary (preview) Two key ideas Machine instruction set Operation codes (op-codes) 3 Example Imagine we are controlling a simple robot Small set of executable primitive actions robot can do: step one step forward turn 90 degrees stop raise arms lower arms sense obstacle turn warning light on or off Robot s instruction set 4 Chapter 5 The Von Neumann Architecture 2
Code English Action Op Codes for robot 000 step step forward 001 turn turn 90 degrees 010 raise arms arms go up, unless obstacle is sensed. If obstacle sensed,warning light goes on 011 lower arms arms lowered 101 if warning light on, go to a particular go to instruction <#> instruction if this condition holds 100 go to instruction <#> go to a particular instruction, no matter what 110 turn light off warning light off 111 halt 5 Program to walk robot to a wall, and stop opcode operand 1. 010 00000 raise arms 2. 101 00110 if warning light on, go to step 6 3. 011 00000 lower arms 4. 000 00000 step forward 5. 100 00001 go to step 1 6. 110 00000 turn off light 7. 111 00000 stop Besides op codes, instructions may need to represent other information 6 Chapter 5 The Von Neumann Architecture 3
Continuing now with Basic Machine Cycle Fetch an instruction from memory to the CPU Decode The instruction in the CPU Execute the instruction 19 Op Codes (revisited): simplified example 8 bits 16 bits 16 bits 16 bits Operation Code Address Field 1 Address Field 2 Address Field 3 Add X, Y add contents held at locations X and Y and put the result back into location X 00001001 0000000000001011 0000000100001011 0000000000000000 Set x to x + 10 20 Chapter 5 The Von Neumann Architecture 10
Address bus Control Unit Registers Data bus... Program Counter Register Instruction address Instruction Register Op Code Address Fields + 1 Instruction Decoder Circuit Line 000 (add) Enable add circuits Line 010 (load) enable load circuits 21 Machine Cycle (3) Fetch An instruction from memory to CPU Address taken from PC register Deposit instruction in Instruction Register Advance the PC to the next address Decode OpCode in Instruction Register decoded into one of the machine instruction primitives add the contents of addresses X and Y and place back in X Execute 22 Chapter 5 The Von Neumann Architecture 11
Execution requires fetches/stores Add values at addresses 1 and 2 and store value back in address 1 (set x to x + y) Set the fetch signal Send address 1 out on address bus, fetch those contents on data bus Send address 2 out on address bus, fetch those contents on data bus Do the add operation and get a result Set store signal Send address 1 on address bus, send result back on data bus 23 24 Chapter 5 The Von Neumann Architecture 12