DDR Memory controller fundamentals review

14 Aug 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc..

DDR Memory controller fundamentals review DDR basic FSL memory controller capability QCS DDR configuration DDR Validation Tool Parameters validation Memory testing 2

Access Transistor Column (bit) line Row (word) line G 1 => Vcc 0 => Gnd S D precharged to Vcc/2 Cbit Ccol Storage Capacitor Vcc/2 Parasitic Line Capacitance 3

ROW ADDRESS DECODER W0 W1 W2 B0 B1 B2 B3 B4 B5 B6 B7 SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER 4

A requested row is ACTIVATED and made accessible through the bank s row buffer Row 0 Row 1 Row 2 Row 3 Row Row Buffers Bank 0 Bank 1 Bank 2 Bank 3 READ and/or WRITE are issued to the active row The row is PRECHARGED and is no longer accessible through the bank s row buffer Row 0 Row 1 Row 2 Row 3 Row Row Buffers Row 0 Row 1 Row 2 Row 3 Row Row Buffers Bank 0 Bank 1 Bank 2 Bank 3 Bank 0 Bank 1 Bank 2 Bank 3 5

The cell array of DDR3 modules will run at a quarter of the speed of the external bus which requires an 8 bit I/O buffer, up from 4 bits for DDR2 Source: Micron datasheet 6

Supports most JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices Memory device densities from 64Mb through 8Gb Data rates up to: 333 MT/s for DDR1, 800 MT/s for DDR2, and 2133MT/s for DDR3 Devices with 12-16 row address bits, 8-11 column address bits, 2-3 logical bank address bits Data mask signals for sub-double word writes Up to four physical banks (chip selects) Physical bank sizes up to 8GB, total memory up to 32GB per controller Physical bank interleaving between 2 or 4 chip selects Memory controller interleaving when more than 2 controllers are available Unbuffered or registered DIMMs 7

Up to 32 open pages Open row table Amount of time rows stay open is programmable Auto-precharge, globally or by chip select Self-refresh Up to 8 posted refreshes Automatic or software controlled memory device initialization ECC: 1-bit error correction, 2-bit error detection, detection of all errors within a nibble ECC error injection Read-modify-write for sub-doubleword writes when using ECC Automatic data initialization for ECC Dynamic power management 8

DDR3L (1.35V) is a low voltage version of the DDR3 (1.5V). DDR3L meet the exact same functional and timing specifications of DDR3. VIH/VIL differences are compensated by corresponding derating values to Vref resulting no change in AC timing, and timing budget calculation. The main consideration for using DDR3L are: Memory controller needs to support DDR3L P1023, P1017, P1010, P1014, P2040, P3041, P5020 The supply voltage needs to be at 1.35V Using DDR3L SDRAM 9

Two general type of registers to be configured in the memory controller First register type are set to the DRAM related parameter values, that are provided via SPD or DRAM datasheet Second register type are the Non-SPD values that are set based on customer s application. For example: On-die-termination (ODT) settings for DRAM and controller driver impedance setting for DRAM and controller Clock adjust, write data delay, Cast to preamble override (CPO) 2T or 3T timing, Burst type selection (fixed or on-fly burst chop mode) Write-leveling start value (WRLVL_START) 10

Use the tool to generate the DDR register settings QCS generation tool will produce the best initial DDR settings Use this setting to start the verification/margin tuning of the board/application dependent settings. Tool will select the center value with best margins This verification/margin tests will run on the board via JTAG connection At this point if nothing works there is an board HW issue. If there are passing point you would know the registers are set to best margins available in the board being tested. 11

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc..

Configuration of QorIQ processors is increasing in complexity Even more complexity is around the corner We support many, many configuration settings Reference manuals are huge and intimidating to new customers Configuration problems during board bring-up are HARD and COSTLY Learning command line tools requires more training, etc. Solution/Strategy to solve these problems: Extensible suite of tools with a common user interface Consolidate into a common tools framework (Processor Expert) Provide new device support aligned with silicon roadmap Add more configuration tools over time Allow customers to add their own configuration tools to extend what we offer 13

QorIQ Configuration Suite v2.2.2 is NOW AVAILABLE!!! Supports all QorIQ and Qorivva devices Works with Eclipse 3.5, Eclipse 3.6, Eclipse 3.7 development tools Pure Java solution for maximum choice of host system support Add-in to CodeWarrior Development Studio for PA, v10.1 or later Available from www.freescale.com/qcs FREE DOWNLOAD* Compass site for Freescale employees http://compass.freescale.net/livelink/livelink/open/pexqoriqrelease * Must be a QorIQ customer or under QorIQ NDA for download permission Actual URL is http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=pe_qoriq_suite&tid=peh 14

Includes the following configuration tools all designed to collaborate on consistent configuration: PBL tool to define the Reset Control Word bit values and PBI data for the pre-boot BOOTROM generator for those QorIQ without RCW functionality DDR configuration supports setting the controller to a working state for any DDR Data path graphical view helps to define data path configuration for the DPAA. Hardware Device Tree editor supports references, synchronous GUI and XML editing, node validation based on specification bindings Packaged as a separate product with installer and wizard functionality P5040, P5021, P5020, P5010, P4080 v1.0, P4080 v2.0, P4040 v1.0, P4040 v2.0, P3041, P2041, P2040, P2020, P2010, P1025, P1024, P1023, P1022, P1021, P1020, P1017, P1016, P1015, P1014, P1013, P1012, P1011, P1010, G1110 15

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Get DRAM data sheet Maximum speed rating Capacity configuration Please do not proceed if you don t the DRAM details 20

From back of RDB box From DRAM datasheet 21

Don t worry, tool will automatically compute this for you! 22

Open the CW config file you want to adapt D:\Program Files\Freescale\CW PA v10.1\pa\pa_support\initialization_files\qoriq_p4\ P4080DS_init_core0.cfg Replace DDR1 config section with the one from D:\Profiles\b08844\workspace\p4080\Generated_Code\ ddrctrl_1.cfg Use this new config file with your stationary project 26

Licensed product *Source Eclipse.org 28

You need QCS 2.2.1 or later installed. Get it from www.freescale.com/qcs Use Eclipse Add new software.. Eclipse updater capability to install DDRV on top of QCS. Use as an update link: http://freescale.com/lgfiles/updates/eclipse/helios36/ddrvalidation for installation over QCS installed over Eclipse 3.6 or CW PA 10 http://freescale.com/lgfiles/updates/eclipse/indigo37/ddrvalidation for installation over QCS installed over Eclipse 3.7 DDRV is a licensed product. 29

Pricing $995 License file: <QCS Install directory>/eclipse/optimization/license.dat 30

1 2 Test stages / scenarios Scenario details Tests to be executed per each scenario HW Connection setup 31

7 9 3 4 5 10 6 8 2 11 1 12 32 13

Test results per DDR configuration 33

3 Optimal DDR configuration is bolded 1 Tests to be executed can be changed between executions 2 Proceed to next validation step 4 34

Optimal settings 35

Checl the scenarios to be tested (TBD) 1 Double click on test to see its content 2 Choose which test to be executed and how many times 3 36

DDR Configuration SPD configuration Import/Export data format Validation Tests Memory tests from cores DMA tests Faster/Optimized tests Support for temperature tests (delayed, repeat tests) 3 rd Party debug environment support Support for i.mx, Kinetis and Auto parts. 37

Processor Expert for QorIQ Configuration Suite - http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=pe_qoriq_suite&tid=peh Freescale s Processor Expert landing page http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=processor-expert&tid=peh http://www.processorexpert.com/ Freescale Software & Tools website - http://www.freescale.com/webapp/sps/site/homepage.jsp?code=developer_home Freescale Component Store purchasing embedded software - http://www.freescale.com/webapp/sps/site/homepage.jsp?code=bean_store_main&tid=swnt 38

Freescale on Kaixin Tag yourself in photos and upload your own! Weibo? Please use hashtag #FTF2012# Session materials will be posted @ www.freescale.com/ftf 39