Nur A. Touba. Professor Department of Electrical and Computer Engineering The University of Texas at Austin

Nur A. Touba Professor Department of Electrical and Computer Engineering The University of Texas at Austin Education: B.S. Electrical Engineering, University of Minnesota, 9/86-6/90 M.S. Electrical Engineering, Stanford University, 9/90-6/91 Ph.D. Electrical Engineering, Stanford University, 9/91-6/96 - Dissertation Title: Synthesis Techniques for Pseudo-Random Built-In Self-Test - Ph.D. Advisor: Edward J. McCluskey Academic Positions: 9/96 8/01 Assistant Professor, Dept. of Electrical and Computer Engineering, University of Texas, Austin. 9/01 8/07 Associate Professor, Dept. of Electrical and Computer Engineering, University of Texas, Austin. 9/07 Professor, Dept. of Electrical and Computer Engineering, University of Texas, Austin. Professional Experience: 9/91-6/92 Teaching Assistant, Dept. of Electrical Engineering, Stanford University. 6/92-8/92 Teaching Fellow, Dept. of Electrical Engineering, Stanford University. 9/92-6/96 Research Assistant, Center for Reliable Computing, Stanford University. 7/93-9/93 Summer Intern, Philips Research, Palo Alto, CA. 7/94-8/94 Visiting Scholar, Dept. of Electrical Engineering, Bilkent University, Turkey. 7/96-8/96 Research Associate, Center for Reliable Computing, Stanford University. Honors and Awards: Summa Cum Laude Graduate of University of Minnesota 1990 Fellowship Recipient, Dept. of Electrical Engineering, Stanford University 1997 National Science Foundation CAREER Award 2001 Engineering Foundation Faculty Award, College of Engineering, UT-Austin 2001 Best Paper Award, IEEE VLSI Test Symposium 2001 Best Panel Award, IEEE International Test Conference 2006 General Motors Foundation Centennial Teaching Fellowship in Electrical Engineering 2008 Best Paper Award, IEEE Defect and Fault Tolerance Symposium 2009 Fellow of IEEE 1

Memberships in Professional and Honorary Societies: Fellow, Institute of Electrical and Electronics Engineers (IEEE) Eta Kappa Nu (HKN) Electrical Engineering Honor Society Books: Book Chapters - X. Li, K.-J. Lee, and N.A. Touba, Test Compression, in VLSI Test Principles and Architectures: Design for Testability, (ed. L.-T. Wang, C.-W. Wu, and X. Wen), pp. 341-396, Morgan Kaufmann, ISBN 0-12-370597-5, 2006. - N.A. Touba, Fault-Tolerant Design, in System-on-Chip Test Architectures: Towards Nanometer VLSI Design, pp. 123-170, (ed. L.-T. Wang, C.E. Stroud, and N.A. Touba), Morgan Kaufmann, ISBN 0-12-373973-5, 2007. - X. Chen and N.A. Touba, Fundamentals of CMOS Design, in Electronic Design Automation: Synthesis, Verification, and Test, pp. 39-95, (ed. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng), Morgan Kaufmann, ISBN 0-12-374364-0, 2009. Editor of Books - L.-T. Wang, C.E. Stroud, and N.A. Touba, System-on-Chip Test Architectures: Towards Nanometer VLSI Design, Morgan Kaufmann, ISBN 0-12-373973-5, 2007. Refereed Archival Journal Publications: 1. N.A. Touba and E.J. McCluskey, Logic Synthesis of Multilevel Circuits with Concurrent Error Detection, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 7, pp. 783-789, Jul. 1997. 2. N.A. Touba and B. Pouya, "Using Partial Isolation Rings to Test Core-Based Designs ", IEEE Design & Test, pp. 52-59, Oct. 1997. 3. N.A. Touba and E.J. McCluskey, "RP-SYN: Synthesis of Random Pattern Testable Circuits with Test Point Insertion", IEEE Transactions on Computer-Aided Design, Vol. 18, No. 8, pp. 1202-1213, Aug. 1999. 4. D. Das and N.A. Touba, "Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes", Journal on Electronic Testing: Theory and Applications (JETTA), Vol. 15, Issue 1/2, pp. 145-155, Aug. 1999. 5. N.A. Touba and E.J. McCluskey, Bit-Fixing in Pseudo-Random Sequences for Scan BIST, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 4, pp. 545-555, Apr. 2001. 6. A. Jas and N.A. Touba, "Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor", Journal on Electronic Testing: Theory and Applications (JETTA), Vol. 18, Issue 4/5, pp. 503-514, Aug. 2002. 7. N.A. Touba, Circular BIST with State Skipping, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 5, pp. 668-672, Oct. 2002. 2

8. A. Jas, J. Ghosh-Dastidar, M.-E. Eng, and N.A. Touba, "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding", IEEE Transactions on Computer-Aided Design, Vol. 22, No. 6, pp. 797-806, Jun. 2003. 9. L. Li, K. Chakrabarty, and N.A. Touba, "Test Data Compression using Dictionaries with Selective Entries and Fixed-Length Indices", ACM Transactions on Design Automation of Electronic Systems, Vol. 8, Issue 4, pp. 470-490, Oct. 2003. 10. K.J. Balakrishnan and N.A. Touba, "Matrix-Based Software Test Data Decompression for Systems-on-a-Chip", Journal of Systems Architecture, Vol. 50, Issue 5, pp. 247-256, Apr. 2004. 11. A. Jas, B. Pouya, and N.A. Touba, "Test Data Compression Technique for Embedded Cores Using Virtual Scan Chains", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 7, pp. 775-780, Jul. 2004. 12. C.V Krishna, A. Jas, and N.A. Touba, "Achieving High Encoding Efficiency with Partial Dynamic Reseeding", ACM Transactions on Design Automation of Electronic Systems, Vol. 9, Issue 4, pp. 500-516, Oct. 2004. 13. K. Mohanram and N.A. Touba, "Lowering Power Consumption in Concurrent Checkers via Input Ordering", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 11, pp. 1234-1243, Nov. 2004. 14. A. Jas, C.V. Krishna, and N.A. Touba, "Weighted Pseudo-Random Hybrid BIST", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 12, pp. 1277-1283, Dec. 2004. 15. S. Ghosh, S. Basu, and N.A. Touba, " Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits", Journal of Low Power Electronics, Vol. 1, No. 1, pp. 63-72, Apr. 2005. 16. E. MacDonald and N.A. Touba, Delay Testing of Partially-Depleted Silicon-on- Insulator (PD-SOI) Integrated Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp. 587-595, Jun. 2006. 17. N.A. Touba, Survey of Test Vector Compression Techniques, IEEE Design & Test, Vol. 23, Issue 4, pp. 294-303, Jul. 2006. 18. K.J. Balakrishnan and N.A. Touba, Improving Linear Test Data Decompression, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 11, pp. 1227-1237, Nov. 2006. 19. J. Lee and N.A. Touba, LFSR Reseeding Scheme Achieving Low Power Dissipation During Test, IEEE Transactions on Computer-Aided Design, Vol. 26, No. 2, pp. 396-401, Feb. 2007. 20. K. Balakrishnan and N.A. Touba, Relationship Between Entropy and Test Data Compression, IEEE Transactions on Computer-Aided Design, Vol. 23, No. 4, pp. 386-395, Feb. 2007. 21. J. Lee and N.A. Touba, "Correlation-Based Rectangular Encoding", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 10, pp. 1483-1492, Oct. 2010. 3

22. J.-S. Yang and N.A. Touba, "Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis", IEEE Transactions on Computer-Aided Design, Vol. 31, No. 3, pp. 442-446, Mar. 2012. 23. J.-S. Yang and N.A. Touba, "X-Canceling MISR Architectures for Output Response Compaction with Unknown Values", IEEE Transactions on Computer-Aided Design, Vol. 31, No. 9, pp. 1417-1427, Sep. 2012. 24. J.-S. Yang and N.A. Touba, "Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops", IEEE Transactions on Computers, Vol. 61, No. 10, pp. 1473-1483, Oct. 2012. 25. J.-S. Yang and N.A. Touba, "Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug", IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 21, No. 12, pp. 320-328, Feb. 2013. 26. J.-S. Yang and N.A. Touba, "Utilizing ATE Vector Repeat with Linear Decompressor for Test Vector Compression," IEEE Transactions on Computer-Aided Design, Vol. 33, No. 8, pp. 1219-1230, Aug. 2014. 27. M.T. Rab, A.A. Bawa, and N.A. Touba, "Reducing Cost of Yield Enhancement in 3D Stacked Memories via Asymmetric Layer Repair Capability", IEEE Transactions on Very Large Scale Integration (VLSI). (Accepted for Publication) Refereed Conference Publications: 1. N.A. Touba and E.J. McCluskey, Automated Logic Synthesis of Random Pattern Testable Circuits, Proc. of IEEE International Test Conference, pp. 174-183, 1994. 2. N.A. Touba and E.J. McCluskey, Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 651-654, 1994. 3. N.A. Touba and E.J. McCluskey, Transformed Pseudo-Random Patterns for BIST, Proc. of IEEE VLSI Test Symposium, pp. 410-416, 1995. 4. N.A. Touba and E.J. McCluskey, Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST, Proc. of IEEE International Test Conference, pp. 674-682, 1995. 5. N.A. Touba and E.J. McCluskey, Applying Two-Pattern Tests Using Scan-Mapping, Proc. of IEEE VLSI Test Symposium, pp.393-397, 1996. 6. N.A. Touba and E.J. McCluskey, Test Point Insertion Based on Path Tracing, Proc. of IEEE VLSI Test Symposium, pp. 2-8, 1996. 7. N.A. Touba and E.J. McCluskey, Altering a Pseudo-Random Bit Sequence for Scan- Based BIST, Proc. of IEEE International Test Conference, pp. 167-175, 1996. 8. N.A. Touba, Obtaining High Fault Coverage with Circular BIST Via State Skipping, Proc. of IEEE VLSI Test Symposium, pp. 410-415, 1997. 9. N.A. Touba and B. Pouya, Testing Embedded Cores Using Partial Isolation Rings, Proc. of IEEE VLSI Test Symposium, pp. 10-16, 1997. 4

10. B. Pouya and N.A. Touba, Modifying User-Defined Logic for Test Access to Embedded Cores, Proc. of IEEE International Test Conference, pp. 60-68, 1997. 11. N.A. Touba and E.J. McCluskey, "Pseudo-Random Pattern Testing of Bridging Faults ", Proc. of IEEE International Conference on Computer Design (ICCD), pp. 54-60, 1997. 12. D. Das and N.A. Touba, Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes, Proc. of IEEE VLSI Test Symposium, pp. 309-315, 1998. 13. B. Pouya and N.A. Touba, Synthesis of Zero-Aliasing Elementary-Tree Space Compactors, Proc. of IEEE VLSI Test Symposium, pp. 70-77, 1998. 14. Z. Zhao, B. Pouya, and N.A. Touba, "BETSY: Synthesizing Circuits for a Specified BIST Environment", Proc. of IEEE International Test Conference, pp. 144-153, 1998. 15. A. Jas and N.A. Touba, "Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs", Proc. of IEEE International Test Conference, pp. 458-464, 1998. 16. J. Ghosh Dastidar and N.A. Touba, "A Systematic Approach for Diagnosing Multiple Delay Faults", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 211-216, 1998. 17. M. Karkala, N.A. Touba, and H.-J. Wunderlich, "Special ATPG to Correlate Test Patterns for Low Overhead Mixed-Mode BIST", Proc. of IEEE Asian Test Symposium, pp. 492-499, 1998. 18. D. Das and N.A. Touba, "A Low Cost Approach for Detecting, Locating, and Avoiding Interconnet Faults in FPGA-Based Reconfigurable Systems", Proc. of International Conference on VLSI Design, pp. 266-269, 1999. 19. A. Jas, J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding", Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999. 20. J. Ghosh-Dastidar and N.A. Touba, "Adaptive Techniques for Improving Delay Fault Diagnosis", Proc. of IEEE VLSI Test Symposium, pp. 168-172, 1999. 21. D. Das and N.A. Touba, "Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits", Proc. of IEEE VLSI Test Symposium, pp. 370-376, 1999. 22. W. Quddus, A. Jas, and N.A. Touba, "Configuration Self-Test in FPGA-Based Reconfigurable Systems", Proc. of IEEE International Symposium on Circuits and Systems, pp. 97-100, 1999. 23. P.K. Jaini and N.A. Touba, "Observing Test Response of Embedded Cores through Surrounding Logic", Proc. of IEEE International Symposium on Circuits and Systems, pp. 119-123, 1999. 24. A. Jas and N.A. Touba, "Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip", Proc. of IEEE International Conference on Computer Design, pp. 418-423, 1999. 25. E. MacDonald and N.A. Touba, "Delay Testing of SOI Circuits: Challenges with the History Effect", Proc. of IEEE International Test Conference, pp. 269-275, 1999. 5

26. J. Ghosh-Dastidar, D. Das, and N.A. Touba, "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information", Proc. of IEEE Int. Test Conf., pp. 95-102, 1999. 27. A. Jas, K. Mohanram and N.A. Touba, "An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets", Proc. of IEEE Asian Test Symposium, pp. 275-280, 1999. 28. A. Jas, B. Pouya, and N.A. Touba, "Virtual Scan Chains: A Means for Reducing Scan Length in Cores", Proc. of IEEE VLSI Test Symposium, pp. 73-78, 2000. 29. J. Ghosh-Dastidar and N.A. Touba, "A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains", Proc. of IEEE VLSI Test Symposium, pp. 79-85, 2000. 30. R. Sankaralingam, R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of IEEE VLSI Test Symp., pp. 35-40, 2000. 31. J. Ghosh-Dastidar and N.A. Touba, "Diagnosing Resistive Bridges Using Adaptive Techniques", Proc. of IEEE Custom Integrated Circuits Conference, pp. 79-82, 2000. 32. D. Das and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns", To Appear in Proc. of IEEE International Test Conference, pp. 115-122, 2000. 33. M. Ng and N.A. Touba, "Test Vector Compression Via Statistical Coding and Dynamic Compaction", Proc. of Autotestcon, pp. 348-354, 2000. 34. E. MacDonald and N.A. Touba, "Testing Domino Circuits in SOI Technology", Proc. of IEEE Asian Test Symposium, pp. 441-446, 2000. 35. A. Jas, C.V. Krishna, and N.A. Touba, "Hybrid BIST Based on Weighted Pseudo- Random Testing: A New Test Resource Partitioning Scheme", Proc. of IEEE VLSI Test Symposium, pp. 2-8, 2001. 36. R. Sankaralingam, B. Pouya, and N.A. Touba, "Reducing Power Dissipation During Test Using Scan Chain Disable", Proc. of IEEE VLSI Test Symposium, pp. 319-324, 2001. 37. J. Ghosh Dastidar and N.A. Touba, "Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 215-220, 2001. 38. C.V. Krishna, A. Jas, and N.A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of IEEE International Test Conference (ITC), pp. 885-893, 2001. 39. K. Mohanram, C.V. Krishna, and N.A. Touba "A Methodology for Automated Insertion of Concurrent Error Detection Hardware in Synthesizable Verilog RTL", Proc. of IEEE International Symposium on Circuits and Systems, pp. 577-580, 2002. 40. R. Sankaralingam and N.A. Touba, "Controlling Peak Power During Scan Testing", Proc. of IEEE VLSI Test Symposium (VTS), pp. 153-159, 2002. 41. E. MacDonald and N.A. Touba, "Very Low Voltage Testing of SOI Integrated Circuits", Proc. of IEEE VLSI Test Symposium (VTS), pp. 25-30, 2002. 6

42. C.V. Krishna and N.A. Touba, "Reducing Test Data Volume Using LFSR Reseeding with Seed Compression", Proc. of IEEE International Test Conference, pp. 321-330, 2002. 43. R. Sankaralingam and N.A. Touba, "Inserting Test Points to Control Peak Power During Scan Testing", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 138-146, 2002. 44. K.J. Balakrishnan and N.A. Touba, "Matrix-Based Test Vector Decompression Using an Embedded Processor", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 159-165, 2002. 45. K. Mohanram and N.A. Touba, "Input Ordering in Concurrent Checkers to Reduce Power Consumption", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 87-95, 2002. 46. S.Ghosh, S.Basu, and N.A. Touba, "Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering", Proc. of IEEE Symposium on VLSI, pp. 246-249, 2003. 47. K. Mohanram and N.A. Touba, "Eliminating Non-Determinism During Test of High- Speed Source Synchronous Differential Buses", Proc. of IEEE VLSI Test Symposium, pp. 121-127, 2003. 48. K.J. Balakrishnan and N.A. Touba, "Deterministic Test Vector Decompression in Software Using Linear Operations", Proc. of IEEE VLSI Test Symposium, pp. 225-231, 2003. 49. K. Mohanram, E.S. Sogomonyan, M. Goessel, and N.A. Touba, "Synthesis of Low- Cost Parity-Based Partially Self-Checking Circuits", Proc. of International On-Line Test Symposium, pp. 35-40, 2003. 50. K. Mohanram and N.A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits", Proc. of IEEE International Test Conference, pp. 893-901, 2003. 51. C.V. Krishna and N.A. Touba, "Adjustable Width Linear Combinational Scan Vector Decompression", Proc. of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 863-866, 2003. 52. K. Mohanram and N.A. Touba, "Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 433-440, 2003. 53. C.V. Krishna and N.A. Touba, "Hybrid BIST Using an Incrementally Guided LFSR", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 217-224, 2003. 54. K.J. Balakrishnan and N.A. Touba, "Scan-Based BIST Diagnosis Using an Embedded Processor", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 209-216, 2003. 55. C.V. Krishna and N.A. Touba, "3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme", Proc. of IEEE VLSI Test Symposium, pp. 79-86, 2004. 56. S. Ghosh, E. MacDonald, S. Basu, and N. A. Touba, "Low-Power Weighted Pseudo- Random BIST Using Special Scan Cells", Proc. of the ACM Great Lakes Symposium on VLSI, pp. 86-91, 2004. 7

57. K.J. Balakrishnan and N.A. Touba, "Relating Entropy Theory to Test Data Compression", Proc. of IEEE European Test Symposium, pp. 94-99, 2004. 58. J. Lee and N.A. Touba, "Low Power Test Data Compression Based on LFSR Reseeding", Proc. of IEEE International Conference on Computer Design, pp. 180-185, 2004. 59. S. Ghosh, S. Basu, and N.A. Touba, "Reducing Power Consumption in Memory ECC Checkers", Proc. of IEEE International Test Conference, pp. 1322-1331, 2004. 60. K.J. Balakrishnan and N.A. Touba, "Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion", Proc. of IEEE International Test Conference, pp. 936-943, 2004. 61. A. Dutta and N.A. Touba, Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier, Proc. of IEEE Annual Symposium on VLSI, pp. 200-205, 2005. 62. S. Ghosh, S. Basu, and N.A. Touba, "Synthesis of Low Power CED Circuits Based on Parity Codes", Proc. of IEEE VLSI Test Symposium, pp.1322-1331, 2005. 63. A. Dutta and N.A. Touba, "Synthesis of Non-Intrusive Concurrent Error Detection Using an Even Error Detecting Function", Proc. of IEEE International Test Conference, 2005. 64. S.I. Ward, C. Schattauer, and N.A. Touba, Using Statistical Transformations to Improve Compression for Linear Decompressors, Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 42-50, 2005. 65. J. Lee and N.A. Touba, Low Power BIST Based on Scan Partitioning, Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 33-41, 2005. 66. K.J. Balakrishnan, N.A. Touba, S. Patil, "Compressing Functional Tests for Microprocessors", Proc. of IEEE Asian Test Symposium, pp. 428-433, 2005. 67. A. Dutta and N.A. Touba, Iterative OPDD Based Signal Probability Calculation, Proc. of VLSI Test Symposium, pp. 72-77, 2006. 68. J. Lee and N.A. Touba, Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Coding, Proc. of VLSI Test Symposium, pp. 252-257, 2006. 69. A. Dutta and N.A. Touba, "Synthesis of Efficient Linear Test Pattern Generators", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 206-214, 2006. 70. J. Lee and N.A. Touba, "Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition", Proc. of IEEE Asian Test Symposium, pp. 237-244, 2006. 71. A. Dutta and N.A. Touba, "Using Limited Dependence Sequential Expansion for Decompressing Test Vectors", Proc. of IEEE International Test Conference, Paper 23.1, 2006. 72. R. Putman and N.A. Touba, "Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression", Proc. of IEEE VLSI Test Symposium, pp. 211-216, 2007. 73. A. Dutta and N.A. Touba, "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code", Proc. of IEEE VLSI Test Symposium, pp. 349-354, 2007. 8

74. N.A. Touba, "X-Canceling MISR An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR", Proc. of IEEE International Test Conference, Paper 6.2, 2007. 75. A. Dutta and N.A. Touba, Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code, Proc. on IEEE Symposium on Defect and Fault Tolerance, pp. 3-11, 2007. 76. R. Putman and N.A. Touba, "Using Reiterative LFSR Based X-Masking to Increase Output Compression in Presence of Unknowns", Proc. of IEEE Great Lakes Symposium on VLSI, 2008. 77. J.-S. Yang and N.A. Touba, "Expanding Trace Buffer Observation Window for In- System Silicon Debug through Selective Capture ", Proc. of IEEE VLSI Test Symposium, pp. 345-351, 2008. 78. R. Garg, R. Putman, and N.A. Touba "Increasing Output Compaction in Presence of Unknowns using an X-Canceling MISR with Deterministic Observation", Proc. of IEEE VLSI Test Symposium, pp. 35-42, 2008. 79. J.-S. Yang and N.A. Touba, "Enhancing Silicon Debug via Periodic Monitoring", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 125-133, 2008. 80. R. Datta and N.A. Touba, "Exploiting Unused Spare Columns to Improve Memory ECC" Proc. of IEEE VLSI Test Symposium, pp. 47-52, 2009. 81. J.-S. Yang and N.A. Touba, "Automated Selection of Signals to Observe for Efficient Silicon Debug" Proc. of IEEE VLSI Test Symposium, pp. 79-84, 2009. 82. J.-S. Yang, B. Nadeau-Dostie, and N.A. Touba, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 20-28, 2009. 83. M. Rab, A. Bawa, and N.A. Touba, "Improving Memory Repair by Selective Row Partitioning", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 211-219, 2009. 84. J.-S. Yang, N.A. Touba, S.-Y. Yang, and T.M. Mak, "Industrial Case Study for X- Canceling MISR", Proc. of IEEE International Test Conference, Paper 17.2, 2009. 85. J.-S. Yang, N.A. Touba, and B. Nadeau-Dostie, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points", Proc. of IEEE International Test Conference, Paper 17.3 2009. 86. L.-T. Wang, N.A. Touba, Z. Jiang, S. Wu, J.-L. Huang, and J. Li, CSER: BISERbased Concurrent Soft-Error Resilience, Proc. of IEEE VLSI Test Symposium, pp. 153-158, 2010. 87. R. Datta and N.A. Touba, "Post-Manufacturing ECC Customization Based on Orthogonal Latin Square Codes and Its Application to Ultra-Low Power Caches", Proc. of IEEE International Test Conference, Paper 7.2, 2010 88. S. Wu, L.-T. Wang, L. Yu, H. Furukawa, X. Wen, W.-B. Jone, N.A. Touba, F. Zhao, J. Liu, H.-J. Chao, F. Li, and Z. Jiang, Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains, Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 358-366, 2010. 9

89. R. Datta and N.A. Touba, Designing a Fast and Adaptive Error Correction Scheme for Increasing the Lifetime of Phase Change Memories, Proc. of VLSI Test Symposium, pp. 134-139, 2011. 90. R. Datta and N.A. Touba, "Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes -- A Graph Theoretic Approach", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 367-373, 2011. 91. R. Datta and N.A. Touba, "X-Stacking - A Method for Reducing Control Data for Output Compaction", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 332-338, 2011. 92. J. Chung and N.A. Touba, "Exploiting X-Correlation in Output Compression via Superset X-Canceling", Proc. of VLSI Test Symposium", 2012. 93. S.S. Muthyala and N.A. Touba, "Improving Test Compression by Retaining Non-Pivot Free Variables in Sequential Linear Decompressors", Proc. of Int. Test Conference, pp. 195-200, 2012. 94. A.A. Bawa, M.T. Rab, and N.A. Touba, "Using Partial Masking in X-Chains to Increase Output Compaction for an X-Canceling MISR", Proc. of Int. Symp. on Defect and Fault Tolerance, pp. 19-24, 2012. 95. M.T. Rab, A.A. Bawa, and N.A. Touba, "Implementing Defect Tolerance in 3D-ICs by Exploiting Degrees of Freedom in Assembly", Proc. of Int. Symp. on Defect and Fault Tolerance, pp. 178-181, 2012. 96. M.T. Rab, A.A. Bawa, and N.A. Touba, "Using Asymmetric Layer Repair Capability to Reduce the Cost of Yield Enhancement in 3D Stacked Memories", Proc. of Int. Conf. on VLSI and System-on-Chip, pp. 195-200, 2012. 97. S.S. Muthyala and N.A. Touba, "SOC Test Compression Scheme Using Sequential Linear Decompressors with Retained Free Variables", Proc. of VLSI Test Symposium, pp. 31-37, 2013. 98. Y.-W. Lee and N.A. Touba, "Unified 3D Test Architecture for Variable Test Data Bandwidth Across Pre-Bond, Partial Stack, and Post-Bond Test", Proc. of Int. Symp. on Defect and Fault Tolerance, pp. 184-189, 2013. 99. P. Reviriego, S.-F. Lu, S.-E. Lee, N.A. Touba, J.A. Maestro, and R.Datta, "Implementing Triple-Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes", Proc. of Int. Symp. on Defect and Fault Tolerance, pp. 167-171, 2013. 100. A.A. Bawa, M.T. Rab, and N.A. Touba, "Efficient Compression of X-Masking Control Data via Dynamic Channel Allocation", Proc. of Int. Symp. on Defect and Fault Tolerance, pp. 125-130, 2013. 101. K. Saleem and N.A. Touba, "Efficient Algorithm for Test Vector Decompression Using an Embedded Processor", Proc. of Autotestcon Conference, 2014. 102. S.S. Muthyala and N.A. Touba, "Reducing Test Time for 3D-ICs by Improved Utilization of Test Elevators ", Proc. of International Conference on Very Large Scale Integration and System-on-Chip, Paper M1B.3, 2014. 103. S.S. Muthyala and N.A. Touba, "Improving Test Compression using Scan Feedforward Techniques", Proc. of International Test Conference, 2014. (Accepted) 10

Workshop Presentations: 1. N.A. Touba, "Synthesis of Random Pattern Testable Circuits", IEEE BAST Workshop, Feb. 1994. 2. N.A. Touba and E.J. McCluskey, "Logic Synthesis of Random Pattern Testable Circuits Using Algebraic Transformations," IEEE International Test Synthesis Workshop, May. 1994. 3. N.A. Touba, "Synthesis of Mapping Logic", IEEE BAST Workshop, Feb. 1995. 4. N.A. Touba and E.J. McCluskey, "Transformed Pseudo-Random Patterns for BIST", IEEE Built-In Self-Test / Design-For-Testability Workshop, Mar. 1995. 5. N.A. Touba and E.J. McCluskey, "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST", IEEE Int. Test Synthesis Workshop, May 1995. 6. N.A. Touba, "Test Point Insertion Based on Path Tracing", IEEE BAST Workshop, Feb. 1996. 7. N.A. Touba and E.J. McCluskey, "Partial Isolation Rings for Testing Embedded Cores", IEEE High-Level Design, Validation, and Test Workshop, Nov. 1996. 8. B. Pouya and N.A. Touba, "Modifying User-Defined Logic for Testing Access to Embedded Cores", IEEE International Test Synthesis Workshop, May 1997. 9. M. Karkala and N.A. Touba, "Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST", IEEE International Test Synthesis Workshop, May 1997. 10. B. Pouya and N.A. Touba, "Space Compaction in Core-Based Designs ", IEEE High-Level Design, Validation, and Test Workshop, Nov. 1997. 11. B. Pouya, Z. Zhao, and N.A. Touba, "Synthesizing Circuits with High Fault Coverage for a Specified BIST Environment", IEEE International Test Synthesis Workshop, Mar. 1998. 12. A. Jas and N.A. Touba, "Test Data Compression/Decompression Schemes for Testing Core- Based Designs", IEEE International Test Synthesis Workshop, Mar. 1998. 13. A. Jas and N.A. Touba, "Test Vector Compression/Decompression for Systems-on-a-Chip Using Statistical Coding", IEEE High-Level Design, Valid., and Test Workshop, Nov. 1998. 14. J. Ghosh-Dastidar, D. Das, and N.A. Touba, "Fault Diagnosis in Scan-Based BIST Using both Time and Space Information", IEEE Int. Test Synthesis Workshop, Mar. 1999. 15. A. Jas and N.A. Touba, "Efficient Testing of Systems-on-a-Chip Using an Embedded Processor", IEEE International Test Synthesis Workshop, Mar. 1999. 16. A. Jas and N.A. Touba, "Scan Length Reduction in Cores Using Virtual Scan Chains", IEEE International Workshop on Testing Embedded Core-based Systems, Apr. 1999. 17. D. Das and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns", IEEE International Test Synthesis Workshop, Mar. 2000. 18. R. Sankaralingam and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", IEEE International Test Synthesis Workshop, Mar. 2000. 19. D. Das, N.A. Touba, M. Seuring, and M. Goessel, "Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes", IEEE On-Line Test Workshop, Jul. 2000. 20. R. Sankaralingam, N.A. Touba, and B. Pouya, "Disabling Scan Chains to Reduce Power Dissipation During Test", IEEE International Test Synthesis Workshop, Mar. 2001. 21. C.V. Krishna, A. Jas, and N.A. Touba, "Weighted Pseudo-Random Hybrid BIST", IEEE International Test Synthesis Workshop, Mar. 2001. 11

22. C.V. Krishna, A. Jas, and N.A. Touba, "Reducing Test Data Volume for Cores Using Dynamic LFSR Reseeding", IEEE International Workshop on Testing Embedded Core-based Systems, May 2001. 23. R. Sankaralingam and N.A. Touba, "Reducing Test Power Using Programmable Scan Chain Disable", IEEE International Workshop on Electronic Design, Test, and Applications, Jan. 2002. 24. E. McDonald and N.A. Touba, "Very Low Voltage Testing of SOI Integrated Circuits", IEEE Latin-American Test Workshop, Feb. 2002. 25. R. Sankaralingam and N.A. Touba, "Reducing Peak Power Consumption During Scan Testing by Vector Modification", IEEE International Test Synthesis Workshop, Mar. 2002. 26. C.V. Krishna and N.A. Touba, "Improving Test Data Compression Based on LFSR Reseeding", IEEE International Test Synthesis Workshop, Mar. 2002. 27. C.V. Krishna, N.A. Touba, and B. Pouya, "Improving Test Data Compression Based on LFSR Reseeding", IEEE International Test Synthesis Workshop, Mar. 2002. 28. K.J. Balakrishnan and N.A. Touba, "Matrix-Based Test Vector Decompression Using an Embedded Processor", IEEE Workshop on Microprocessor Test and Verification, Jun. 2002. 29. R. Sankaralingam and N.A. Touba, "Multi-Phase Shifting to Reduce Instantaneous Peak Power during Scan", IEEE Latin-American Test Workshop, Feb. 2003. 30. K.J. Balakrishnan and N.A. Touba, "Deterministic Test Vector Decompression in Software Using Linear Operations", IEEE International Test Synthesis Workshop, Apr. 2003. 31. K. Mohanram and N.A. Touba, "Non-Deterministic Behavior in the Test of High-Speed Packet Switched I/O Ports", IEEE International Test Synthesis Workshop, Apr. 2003. 32. K.J. Balakrishnan and N.A. Touba, "Using an Embedded Processor for Diagnostic Response Compaction", IEEE Workshop on Microprocessor Test and Verification, Jun. 2003. 33. J. Lee and N.A. Touba, "Low Power LFSR Reseeding", IEEE International Test Synthesis Workshop, Apr. 2004. 34. K.J. Balakrishnan and N.A. Touba, "Entropy Limits on Test Data Compression", IEEE International Test Synthesis Workshop, Apr. 2004. 35. K.J. Balakrishnan and N.A. Touba, "Compressing Functional Tests for Microprocessors", IEEE Workshop on Microprocessor Test and Verification, Sep. 2004. 36. A. Dutta and N.A. Touba, "SLING: A Procedure for Synthesis of Linear Test Pattern Generators with Strong Randomness Properties", IEEE International Test Synthesis Workshop, Apr. 2005. 37. J. Lee and N.A. Touba, "Low Power BIST Based on Scan Chain Partitioning", IEEE International Test Synthesis Workshop, Apr. 2005. 38. N.A. Touba, "Exploiting Asymmetric Soft Error Susceptibility for Cost-Effective Concurrent Error Detection in Logic Circuits", IEEE Workshop on System Effects of Logic Soft Errors, Apr. 2005. 39. N.A. Touba, "Test Vector Compression based on Limited Depth Sequential Expansion", IEEE BAST Workshop, Mar. 2006. 40. N.A. Touba, "Using Rectangular Coding to Combine Linear and Non-Linear Test Vector Compression", IEEE International Test Synthesis Workshop, Apr. 2006. 12

41. Using Limited Dependence Sequential Expansion for Decompressing Test Vectors," IEEE North Atlantic Test Workshop, May 2006. 42. "How to Compact Output Reponses with X's Using a MISR without Losing Fault Coverage via Symbolic Simulation", IEEE International Test Synthesis Workshop, Mar. 2007. 43. "A Low Cost Code-Based Methodology for Tolerating Multiple Bit Upsets in Memories," IEEE Workshop on System Effects of Logic Soft Errors, Apr. 2007. 44. "X-Canceling - A Way to Compact Output Responses with X's Using a MISR," IEEE North Atlantic Test Workshop, May 2007. 45. "Expanding Observation Window for Trace Buffer via Selective Data Capture", IEEE International Test Synthesis Workshop, Apr. 2008. 46. "Using an X-Canceling MISR with Deterministic Observation for Increasing Output Compaction in the Presence of Unknowns", IEEE International Test Synthesis Workshop, Apr. 2008. 47. "Improving Memory Repair by Selective Row Partitioning" IEEE International Test Synthesis Workshop, Mar. 2009. 48. "Selecting Signals to Observe for Silicon Debug" IEEE International Test Synthesis Workshop, Mar. 2009. 49. "Efficient Linear Decompression Using ATE Vector Repeat-Per-All-Pins" IEEE International Test Synthesis Workshop, Mar. 2009. 50. "Improving Logic Obfuscation via Logic Cone Analysis", Proc. of North Atlantic Test Workshop, 2014. Patents: N.A. Touba and E.J. McCluskey, "Altering Bit Sequences to Contain Predetermined Patterns", U.S. Patent 6,061,818; Issue Date: May 9, 2000. 13

Vita: Nur Touba was born and raised in suburban Minneapolis. He did his undergraduate work at the University of Minnesota where he graduated Summa Cum Laude. He received a graduate fellowship at Stanford University. At Stanford, he worked with Prof. Edward McCluskey at the Center for Reliable Computing. He completed his Ph.D. in 1996. He received a National Science Foundation (NSF) CAREER Award in 1997, Best Paper Award at the VLSI Test Symposium in 2001, Best Panel Award at the International Test Conference in 2005, General Motors Faculty Fellowship in 2006, Best Paper Award at the Defect and Fault Tolerance Symposium in 2008, and IEEE Fellow in 2009. His research interests are in computer-aided design, VLSI testing, and fault-tolerant computing. He has developed a number of innovative techniques for automated design of testable and fault-tolerant circuits. In particular, his research has focused on developing new techniques for built-in self-test (BIST), test data compression, delay fault testing, concurrent error detection, and design-fortestability (DFT) in core-based designs. He is currently serving as Program Chair for the 2008 International Test Conference and 2008 International Test Synthesis Workshop. He has previously served as General Chair for the 2007 Defect and Fault Tolerance Symposium. He is on the program committee for the International Test Conference (ITC), International Conference on Computer Design (ICCD), Design Automation and Test in Europe Conference (DATE), International On-Line Test Symposium (IOLTS), European Test Symposium (ETS), Asian Test Symposium (ATS), Defect and Fault Tolerance Symposium (DFTS), International Test Synthesis Workshop (ITSW), Latin American Test Workshop (LATW), Microprocessor Test and Verification Workshop (MTV), International Workshop on Open Source Test Technology Tools (IOST3), ATE Vision 2020 Workshop, International Workshop on Impact of Low-Power Design on Test and Reliability, and International Conference on Advances in System Testing and Validation Lifecycle (VALID). He is on the editorial board of the Journal of Low Power Electronics (JOLPE) and the Journal of Electronic Testing: Theory and Applications. 14