Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Similar documents
5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

COMPSCI 313 S Computer Organization. 7 MIPS Instruction Set

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC)

CS222: MIPS Instruction Set

MIPS%Assembly% E155%

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

Computer Architecture. The Language of the Machine

Levels of Programming. Registers

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

Lecture 4: MIPS Instruction Set

Instructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

Chapter 2. Instructions:

MIPS Reference Guide

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

EEC 581 Computer Architecture Lecture 1 Review MIPS

Computer Architecture. MIPS Instruction Set Architecture

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

The MIPS Instruction Set Architecture

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

MIPS Instruction Reference

Instructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

CS/COE1541: Introduction to Computer Architecture

Chapter 2A Instructions: Language of the Computer

MACHINE LANGUAGE. To work with the machine, we need a translator.

F. Appendix 6 MIPS Instruction Reference

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Chapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Computer Architecture

MIPS Instruction Set

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson.

SPIM Instruction Set

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Chapter 2: Instructions:

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

CS3350B Computer Architecture MIPS Instruction Representation

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Mips Code Examples Peter Rounce

Chapter 2. Instruction Set Architecture (ISA)

Concocting an Instruction Set

Assembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006

Computer Architecture

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

1/26/2014. Previously. CSE 2021: Computer Organization. The Load/Store Family (1) Memory Organization. The Load/Store Family (2)

Previously. CSE 2021: Computer Organization. Memory Organization. The Load/Store Family (1) 5/26/2011. Used to transfer data to/from DRAM.

Chapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.

Examples of branch instructions

CS3350B Computer Architecture MIPS Introduction

CS3350B Computer Architecture

CPS311 - COMPUTER ORGANIZATION. A bit of history

CENG3420 Lecture 03 Review

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

Lecture 5: Procedure Calls

Flow of Control -- Conditional branch instructions

Assembly Programming

All instructions have 3 operands Operand order is fixed (destination first)

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

ECE232: Hardware Organization and Design

Instruction Set Design and Architecture

Instructions: Language of the Computer

We will study the MIPS assembly language as an exemplar of the concept.

Lectures 3-4: MIPS instructions

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

MIPS Assembly Language. Today s Lecture

CS 351 Exam 2 Mon. 11/2/2015

Topic Notes: MIPS Instruction Set Architecture

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Programming the processor

CMPE324 Computer Architecture Lecture 2

ECE369. Chapter 2 ECE369

Chapter 3. Instructions:

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Concocting an Instruction Set

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018

Q1: /30 Q2: /25 Q3: /45. Total: /100

CS61C : Machine Structures

UCB CS61C : Machine Structures

Week 10: Assembly Programming

Course Administration

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

COMPUTER ORGANIZATION AND DESIGN

CSE 141 Computer Architecture Spring Lecture 3 Instruction Set Architecute. Course Schedule. Announcements

Unsigned Binary Integers

Unsigned Binary Integers

Transcription:

CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language mapping Floating-Point (pending) Data Translation Code Translation compiler Assembly Lang (obj) Topic for next few classes Shakil M. Khan (adapted from Profs. Roumani & Asif) Machine Lang (exe) save.exe to disk CSE-2021 May-19-2011 2 Levels of Programming The RISC Philosophy In this course we will cover MIPS ISA used by NEC, Nintendo, Silicon Graphics, and Sony MIPS is more primitive than higher level languages with a very restrictive set of instructions High-level language program (in C) Assembly language program (for MIPS) Binary machine language program (for MIPS) swap(int v[], int k) {int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } C compiler swap: muli $2, $5,4 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Assembler 00000000101000010000000000011000 00000000100011100001100000100001 10001100011000100000000000000000 10001100111100100000000000000100 10101100111100100000000000000000 10101100011000100000000000000100 00000011111000000000000000001000 MIPS adopts the RISC philosophy very simple instructions so they can execute in one cycle, perhaps with some parallelism Compared to CISC RISC programs tend to be bigger but this is offset by the higher execution speed and the simplicity of the hardware. The latter leads to faster CPU clocks and bigger on-board caches RISC: Reduced Instruction Set Computing CISC: Complex Instruction Set Computing CSE-2021 May-19-2011 3 CSE-2021 May-19-2011 4 1

Design Principles Stored Program Computers The design of the MIPS ISA (Instruction Set Architecture) observes these principles: smaller is faster simplicity favors regularity make the common case fast good design demands good compromises Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs e.g., compilers, linkers, Binary compatibility allows compiled programs to work on different computers Standardized ISAs The BIG Picture CSE-2021 May-19-2011 5 CSE-2021 May-19-2011 6 Fetch and Execute Cycle Processor Memory memory for data, programs, compilers, editors, etc. Instructions are fetched and put into a special register Bits in the register control the subsequent actions Data if required is fetched from the memory and placed in other registers Fetch the next instruction and continue (program counter) Registers Registers are memory cells In MIPS, data must be in registers before arithmetic operations can be performed Size of each register is 32 bits, referred to as a word (1 word = 4 bytes = 32 bits) MIPS has a total of 32 registers CSE-2021 May-19-2011 7 CSE-2021 May-19-2011 8 2

Variables > Registers Registers (Table) Register Allocation associate a register with each variable Preferred Registers eighteen: t0 t9 and s0 s7 Can also use six more: a0 a3 and v0 v1 But cannot use $0, $ra (reserved for the H/W) $k0, $k1 (reserved the O/S) $gp, $sp, $fp (reserved for addressing) $at (reserved for the assembler) CSE-2021 May-19-2011 9 Name Number Usage $zero 0 Constant value of 0 $at 1 reserved for the assembler $v0-$v1 2 3 Values for results and expression evaluation $a0-$a3 4 7 Input arguments to a procedure $t0-$t7 8 15 Not preserved across procedures (temp) $s0-$s7 16 23 Preserved across procedure calls $t8-$t9 24 25 More temporary registers $k0-$k1 26 27 Reserved for OS Kernel $gp 28 Global pointer $sp 29 Stack pointer, points to last location of stack $fp 30 Frame pointer $ra 31 Return address from a procedure call CSE-2021 May-19-2011 10 Assumptions for Phase I (a simple app.) A single class hence, no instantiation of objects and no linking No Attributes hence no heap and no data segment A single method, main hence no stack needed for method invocation Few integer variables hence no spilling everything fits in registers The Arithmetic Family add/sub slt mult/div CSE-2021 May-19-2011 11 CSE-2021 May-19-2011 12 3

Addition & Subtraction Syntax Meaning Comments Example add rd, rs, rt rd = rs + rt Overflow detected add $s0, $s1, $s2 addi rt, rs, imm rt = rs + SignExtImm Overflow detected addi $s0, $s1, 5 sub rd, rs, rt rd = rs rt Overflow detected sub $s0, $s1, $s2 Why three operands? Why addi but not subi? Editors and SPIM Unix, Windows Demo Our very first assembly program: let s convert the following C code to MIPS: x = 1; y = x + x; CSE-2021 May-19-2011 13 CSE-2021 May-19-2011 14 Mapping Variables MIPS Code: step 1: Specify registers containing variables step 2: Express instruction in MIPS $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 Set Less Than slt rd, rs, rt rd = (rs < rt)? 1 : 0 slt $s0, $s1, $s2 slti rt, rs, imm rt = (rs < SignExtImm)? 1 : 0 slti $s0, $s1, -5 sltu rd, rs, rt rd = (rs < rt)? 1 : 0 slt $s0, $s1, $s2 sltiu rt, rs, imm rt = (rs < SignExtImm)? 1 : 0 sltiu $s0, $s1, 5 $s0 - $s7 x $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 $t8 $t9 Why do we need it? Why sltu? $t0 - $t7 y CSE-2021 May-19-2011 15 CSE-2021 May-19-2011 16 4

Multiplication & Division mult rs, rt {hi,lo} = rs*rt mult $s0, $s1 div rs, rt lo = rs / rt hi = rs % rt div $s0, $s1 MIPS to Binary Machine Language (1) Example: add $t0,$s1,$s2 Binary Machine Language Equivalent: 000000 10001 10010 01000 00000 100000 Why two operands? When to ignore hi? mfhi rd rd = hi mfhi $s3 mflo rd rd = lo mflo $s3 Can we derive the binary machine language code from the MIPS instruction? MIPS field for arithmetic instructions: op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits opcode 1 st operand 2 nd operand destination shift function CSE-2021 May-19-2011 17 CSE-2021 May-19-2011 18 MIPS Fields for Arithmetic Operations (R-type) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits opcode 1 st operand 2 nd operand destination shift function Example: add $t0, $s1, $s2 opcode = 0 10 = (000000) 2 rs = $s1 = 17 10 = (10001) 2 rt = $s2 = 18 10 = (10010) 2 rd = $t0 = 8 10 = (01000) 2 shamt is not used = (00000) 2 funct for add = 32 10 = (100000) 2 leads to the binary machine language code: 000000 10001 10010 01000 00000 100000 CSE-2021 May-19-2011 19 MIPS Fields for Immediate Arithmetic Operations (I-type) op rs rt constant 6 bits 5 bits 5 bits 16 bits opcode 1 st operand 2 nd operand Memory address (offset) Example: addi $s1, $s2, 23 opcode = 8 10 = (001000) 2 rs = $s2 = 18 10 = (10010) 2 rt = $s1 = 17 10 = (10001) 2 constant = 23 10 = (0000 0000 0001 0111) 2 leads to the binary machine language code: 001000 10010 10001 0000000000010111 CSE-2021 May-19-2011 20 5

The Logical Family (1) The Logical Family (2) and, or, and xor is there an immediate version? nor what about not? sll and srl is there a variable version? sra why do we need it? CSE-2021 May-19-2011 21 and rd, rs, rt rd = rs & rt and $s3, $s1, $s2 andi rt, rs, imm rt = rs & ZeroExtImm andi $s3, $s1, 5 or rd, rs, rt rd = rs rt or $s3, $s1, $s2 ori rt, rs, imm rt = rs ZeroExtImm ori $s3, $s1, 5 nor rd, rs, rt rd = ~ (rs rt) nor $s0, $s0, $0 sll rd, rt, shamt rd = rt << shamt sll $s1, $s1, 5 srl rd, rt, shamt rd = rt >> shamt srl $s3, $s1, 3 sra rd, rt, shamt rd = rt >>> shamt sra $s3, $s1, 3 sllv rd, rt, rs rd = rt << rs sllv $s1, $s1, $s2 srlv rd, rt, rs rd = rt >> rs srlv $s3, $s1, $s2 srav rd, rt, rs rd = rt >>> rs srav $s3, $s1, $s2 CSE-2021 May-19-2011 22 The Jump Family MIPS Fields for Jump (J-type) Used for unconditional branching to skip the else fragment of if statements and implement method invocation/return opcode address 6 bits 26 bits j and jr do we need both? jal and jalr do we need both? Syntax j C jr rs jal C jalr rs Meaning PC = JumpAddr PC = rs $ra = PC + 8 PC = JumpAddr $ra = PC + 8 PC = rs Example: j 100 opcode = 2 10 = (000010) 2 address = 100 10 = (00 0000 0000 0000 0000 0110 0100) 2 leads to the binary machine language code: 000010 00000000000000000001100100 CSE-2021 May-19-2011 23 CSE-2021 May-19-2011 24 6

The Branch Family Used for conditional branching to implement if statements and loops beq and bne beq rs, rt, C if( rs==rt) PC = PC+4+BranchAddr beq $s1, $s2, L1 bne rs, rt, C if( rs!=rt) PC = PC+4+BranchAddr bne $s1, $s2, L2 Branch Instructions for if Example: C instructions if (i == j) f = g + h; else f = g - h; Variable Register f $s0 g $s1 h $s2 i $s3 j MIPS Code: $s4 bne $s3,$s4,l1 # go to L1 if i == j add $s0,$s1,$s2 # f = g + h j L2 # go to L2 L1: sub $s0,$s1,$s2 # f = g - h L2: Ex.: write the above code using branch if equal to CSE-2021 May-19-2011 25 CSE-2021 May-19-2011 26 General Patterns The u suffix stands for un-trapped for add/sub stands for unsigned for mult, div, and slt Handling immediates 5-bit, zero-extended for shifts 16-bit, zero-extended for logical and lui 26-bit, sign-extended for jump 16-bit, sign-extended for all the rest Large immediates the instruction lui + ori I/O > System Calls Each O/S comes with a host of syscalls also known as interrupts SPIM uses $v0 for the service number see the SPIM Syscall Sheet Service $v0 Send Return Read integer 5 - $v0 Print integer 1 $a0 - Example: #we want to print 99 addi $v0, $0, 1 addi $a0, $0, 99 syscall CSE-2021 May-19-2011 27 CSE-2021 May-19-2011 28 7

Demo (cont d) Another assembly program: read x and y compute and output: z + t*r + 1, where, z = x + y t = max(x,y) r = x y 10 import java.util.*; import java.io.*; Java Code public class First{ public static void main(string[] args){ Scanner input = new Scanner(System.in); PrintStream output = System.out; int x = input.nextint(); // $t0 holds x int y = input.nextint(); // $t1 holds y int z = x + y; int r = x - y - 10; int t = x; if (y > x) t = y; int e = z + t*r + 1; // $t2 holds z // $t3 holds r // $t4 holds t // $t5 holds e } } output.println(e); CSE-2021 May-19-2011 29 CSE-2021 May-19-2011 30.text main: addi $v0, $0, 5 # v0 = 5 syscall add $t0, $v0, $0 # t0 = x addi $v0, $0, 5 # v0 = 5 syscall add $t1, $0, $v0 # t1 = y $t1=$v0 add $t2, $t0, $t1 # t2 = z $t2=$t0+$t1 Let s Assemble! sub $t3, $t0, $t1 # t3 = x - y addi $t3, $t3, -10 # t3 = t3-10 = r add $t4, $0, $t0 # t4 = x slt $t9, $t0, $t1 # t9 = (x<y)? 1 : 0 beq $t9, $0, skip # if t9=0 go to skip add $t4, $0, $t1 # t4 = y skip: #----------------------- # t4 = t mult $t4, $t3 # product in Hi Lo mflo $t5 # t5 = t*r add $t5, $t2, $t5 # t5 = z + t*r addi $t5, $t5, 1 # t5 = z + t*r + 1 addi $v0, $0, 1 add $a0, $t5, $0 syscall jr $ra CSE-2021 May-19-2011 32 8

for Loops Example: C instructions for (i=0; i<5; i++) k = k+1; Say k => $s0 and let s map i => $t0 MIPS Code: Loop: add $t0,$0,$0 #$t0 = 0 addi $t1,$t1,5 #$t1 = 5 beq $t0,$t1,rest #go to Rest if (i==5) addi $s0,$s0,1 #k = k+1 addi $t0,$t0,1 #i = i+1 j Loop #go to Loop Rest: #rest of the program Example: C instructions while (i!=0){ k = k+1; i = i-1; } while Loops Say k => $s0 and i => $t0 MIPS Code: Foo: beq $t0,$0,bar #go to Bar if (i==0) addi $s0,$s0,1 #k = k+1 addi $t0,$t0,-1 #i = i+1 j Foo #go to Foo Bar: CSE-2021 May-19-2011 33 CSE-2021 May-19-2011 34 Demo (Exercise) First, write a simple Java/C program add, mult, slt, j, beq, ifs, loops, read 2 ints, multiply them (using both mult and add), compare them, and print 0 if both are same, ±1 otherwise Now, let s translate it to MIPS How about to machine language? Summary Stored program computers Registers Arithmetic and logical instructions Jump and branch I/O (syscall) Mapping MIPS assembly language to binary machine language CSE-2021 May-19-2011 35 CSE-2021 May-19-2011 36 9