JPEG Decode Framework Module Guide

Similar documents
SEGGER J-Link Lite for Renesas Synergy TM

1. Uses of Breakpoints... 2

PK-S5D9 v1.0 Out-of-Box Demonstration Programming Guidelines

1. RTC HAL Module Features RTC APIs Overview RTC HAL Module Operational Overview... 3

Getting Started Guide for Heartbeat Kit

Getting Started Guide for LED Toggle Kit

Customizing a SSP Module

I²C Slave HAL Module Guide

Simple Audio Playback Example for DK-S124

Introduction to Renesas Synergy SSP v.1.2.0

Getting Started with NetX Duo Web Server

e² studio Pin Configurator Usage

USBX Mass Storage Class (Device)

I/O Port HAL Module Guide

1. Overview Board Specifications S3 Series Board System... 3

Renesas Flash Programmer V

External IRQ HAL Module Guide

Out-of-Box Demonstration for S1/S3/S5 Target Boards

1. DTC HAL Module Features DTC HAL Module APIs Overview DTC HAL Module Operational Overview... 3

Block Media RAM Framework Module Guide

IAR Embedded Workbench for Renesas Synergy v8.21.1

Migrating Existing e 2 studio Projects to IAR Embedded Workbench for Renesas Synergy

R-IN, RZ/T1, TPS-1 Groups

Synergy Standalone Configurator (SSC) v Release Note. Renesas Synergy Platform Synergy Tools & Kits. Release Note

Key Matrix HAL Module Guide

Renesas Synergy Project Import Guide

USER S MANUAL. Features. Evaluation System Contents. JESD204B High Speed ADC. Evaluation Kit. AN1809 Rev 0.00 Dec 5, 2012

Debugging Your Application with IAR C-SPY

USER S MANUAL ISL55110_11EVAL1Z, ISL55110_11EVAL2Z. Before Getting Started. BNC Connections. Scope Probe Connections. Power Down Feature

1. Kit Contents Features Device Components Programming to the SK-S7G2 Starter Kit... 15

RL78 Family Flash Self-Programming Library Type01 Ver.2.21 for the CC-RL compiler

1. Overview Hardware Hardware Configuration Clock Settings Pin Settings... 6

USBX CDC ACM (Device) for Target Boards

ADC Periodic Framework Module Guide

APPLICATION NOTE. Basic SPI Bus Information. Bus Configuration and SPI Protocol of Multiple DCPs. SPI Protocol and Bus Configuration of Multiple DCPs

1. CAC HAL Module Features CAC HAL Module APIs Overview CAC HAL Module Operational Overview... 4

APPLICATION NOTE. Introduction. Copying the SPICE Netlist. Model Editor. From SPICE Netlist to Allegro Design Sub-Circuit. AN1613 Rev.0.

Thread Monitor Framework Module Guide

Target Board S5D5 (TB-S5D5)

USER S MANUAL ISL2800XEVAL1Z. Introduction. Reference Documents. Evaluation Board Schematic. Power Supplies. Optional Transient Protection

GUIX Studio v Release Note. Renesas Synergy Platform Synergy Software Express Logic GUIX Studio v

1. Installation Creating the Project Workspace Opening Sample Code and Source Files Source Code Functionality...

IWDT HAL Module Guide

USBX Device Class Mass Storage Module Guide

1. Overview TPS-1 GUI Configuration Tool Procedure of configure TPS Error Code... 9

USBX TM Host Class Mass Storage Module Guide

AP4 for RH850 V

FIGURE 1. DIGITAL POT POWER TRENDS

1. Opening the sample code workspace Loading the selected sample code project Opening Sample Code and Source Files...

Bluetooth Low Energy on DK-S7G2 and DK S3A7

USBX Host Class Hub Module Guide

R-IN32M3-EC, EC-1, RZ/T1

1. Installation Creating the Project Workspace Opening Sample Code and Source Files Source Code Functionality...

e² studio V7.0.1 Linux Host Public Beta for RZ

PB0 25 PB1 26 PB2 27 PB3 28 PB4 29 PB5 30 PB6 31 PB7 32 VCC PC0 9 PC1 10 PC2 11 PC3 12 PC4 13 PC5 14 PC6 15 PC7 16

APPLICATION NOTE. 16-Bit Data Bus Operation. Summary of 16-Bit Data Bus Performance. 80C286/80386 Hardware Comparison. AN112 Rev 1.

Target Board S1JA (TB-S1JA)

Synergy Software Package Pin Configurator Usage

USER S MANUAL. Key Board Features. Description. References. Specifications. Ordering Information ISL91110IIN-EVZ, ISL91110II2A-EVZ, ISL91110IIA-EVZ

PG-FP6 Gang Programmer V1.00 User s Manual

1. Overview of RX DSP Library System Requirements for the Sample Project... 2

USER S MANUAL ISL54206AEVAL1Z. Picture of Evaluation Board (Top View) Description. Board Architecture/Layout. Features.

QE for USB: A Dedicated Tool for USB

Capacitive Touch Button Framework Module Guide

APPLICATION NOTE. Introduction. Scope. Hardware Connections. Serial Port Operation. The X24C44 NOVRAM Teams up with 8051 Microcontrollers

USBX Device Class HID Module Guide

1. ADC HAL Module Features ADC HAL Module APIs Overview ADC HAL Module Operational Overview... 4

Renesas Starter Kit Sample Code for Cubesuite + Toolchain

Using ADC to Wake Up the MCU from Low Power Modes

1. Installation Creating the Project Workspace Adding Sample Code into DS Adding GNU Toolchain Support for DS-5...

R20AN0311EJ0106 Rev.1.06 Interface conversion module for Ethernet Driver and Embedded system M3S-T4-Tiny Nov 30, 2016

Renesas Flash Programmer V

NetX Telnet Client Module Guide

USER S MANUAL. Description. Key Features. References. Specifications. Ordering Information ISL9120IIA-EVZ. Evaluation Board User Guide

FileX Port Block Media Framework Module Guide

Capacitive Touch Slider Framework Module Guide

USER S MANUAL. Description. Evaluation Board. Board Architecture/Layout. Features

Development Kit S124 (DK-S124)

1. Overview BACnet Demo Software Architecture Programming and Debugging Building Sample Project... 5

Introduction Serial Programing... 2 Write Cycle... 2 Read Cycle... 2 Shared Timing Requirements Write Timing Diagram...

1. GPT HAL Module Features GPT HAL Module APIs Overview GPT HAL Module Operational Overview... 3

Development Kit S128 (DK-S128)

USER S MANUAL. ISL54059EVAL1Z Through ISL54064EVAL1Z. Description. Picture of Evaluation Board (Top View) Board Architecture/Layout.

Tools used Renesas R32C/100 Standard Toolchain version (compiler, assembler, linker): E8a in-circuit debugger.

RX Family APPLICATION NOTE. DNS client using the embedded TCP/IP M3S-T4-Tiny Module Firmware Integration Technology. Introduction.

Renesas Synergy APPLICATION NOTE. Project Migration Guide: SSP v1.0.0 to SSP v Introduction. Goals and Objectives.

NetX Port Ether Module Guide

EX 6 XT 5 RESET 2 3 INT VCC FIGURE 1. TYPICAL HARDWARE CONNECTION FOR INTERFACING AN X24C44 TO A 6805 MICROCONTROLLER.

Mutual Capacitive Touch Software Application Design with Synergy S124 and S3A7 MCUs

USBX Host Class HID Module Guide

Checking Analog Inputs in Sleep State in S3A7

CAN HAL Driver Module Guide

Contents. Chapter 1 Target Product Chapter 2 User's Manual Chapter 3 Revisions Chapter 4 Supported Tools... 3

Self-Capacitive Touch Software Application Design with Synergy S124 and S3A7 MCUs

APPLICATION NOTE. Hardware Implementation. Power-On-Reset (POR) Software Implementation. Low Voltage Reset (LVR) Watchdog Timer

COMMON INFORMATION. AC Power Faults. Introduction. Overview of Telecom and ESD Standards. Transients. Electrostatic Discharge (ESD) Lightning

PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC PD0 PD1 PD2 PD3 PD4 PD5 MODA MODB 27 AS 26 R/W 28

RL78/G11 APPLICATION NOTE. Demonstration Application. Introduction. Target Device. R01AN3918EG0100 Rev July 12, 2017

Audio Playback I2S Framework Module Guide

RX Family RXv2 CPU Products

Transcription:

Application Note Renesas Synergy Platform R11AN0093EU0100 Rev.1.00 Introduction This module guide will enable you to effectively use a module in your own design. Upon completion of this guide, you will be able to add this module to your own design, configure it correctly for the target application and write code, using the included application project code as a reference and an efficient starting point. References to more detailed API descriptions and suggestions of other application projects that illustrate more advanced uses of the module are included in this document and should be valuable resources for creating more complex designs. The JPEG Decode HAL module is a generic API for JPEG decode processing implemented on r_jpeg. (The JPEG Decode HAL module supports the Synergy JPEG Codec peripheral.) The JPEG Decode Framework Module is a ThreadX -aware high-level API for JPEG Framework module applications and is implemented on sf_jpeg_decode; it provides thread-safe access to the Synergy JPEG hardware on a Synergy MCU Group. A user-defined callback can be created to detect hardware supported events. Contents 1. JPEG Decode Framework Module Features... 2 2. JPEG Decode Framework Module APIs Overview... 2 3. JPEG Decode Framework Module Operational Overview... 3 3.1 JPEG Decode Framework Module Important Operational Notes and Limitations... 4 3.1.1 JPEG Decode Framework Module Operational Notes... 4 3.1.2 JPEG Decode Framework Module Limitations... 4 4. Including the JPEG Decode Framework Module in an Application... 4 5. Configuring the JPEG Decode Framework Module... 5 5.1 JPEG Decode Framework Module Clock Configuration... 6 5.2 JPEG Decode Framework Module Interrupt Configuration... 6 5.3 JPEG Decode Framework Module Pin Configuration... 6 6. Using the JPEG Decode Framework Module in an Application... 7 7. The JPEG Decode Framework Module Application Project... 7 8. Customizing the JPEG Decode Framework Module for a Target Application... 11 9. Running the JPEG Decode Framework Module Application Project... 11 10. JPEG Decode Framework Module Conclusion... 12 11. JPEG Decode Framework Module Next Steps... 13 12. JPEG Decode Framework Module Reference Information... 13 R11AN0093EU0100 Rev.1.00 Page 1 of 14

1. JPEG Decode Framework Module Features Provides thread-safe access to the Synergy JPEG hardware. Supports JPEG decompression using the JPEG Decode HAL module. Supports a polling mode that allows an application to wait for the JPEG Decoder to complete. Supports an interrupt mode with user-supplied callback functions. Configures parameters such as horizontal and vertical subsample values, horizontal stride, decoded pixel format, input and output data format and color space. Obtains the size of the image prior to decoding it. Supports putting coded data in an input buffer and an output buffer to store the decoded image frame. Supports streaming coded data into the JPEG Decoder module. This feature allows an application to read a coded JPEG image from a file or from a network without buffering the entire image. Configures the number of image lines to decode. This feature enables the application to process the decoded image on the fly without buffering the entire frame. Supports the input decoded formats YCbCr444, YCbCr422, YCbCr420 and YCbCr411. Supports the output formats ARGB8888 and RGB565. Returns an error when the JPEG image s size, height, and width don t meet the requirements. Supports the wait API function to suspend/resume the thread for synchronizing with the JPEG hardware supported events. Figure 1 JPEG Decode Framework Module Block Diagram 2. JPEG Decode Framework Module APIs Overview The JPEG Decode Framework module defines APIs for opening, closing, setting alarms and starting and stopping RTC operations. A complete list of the available APIs, an example API call and a short description of each can be found in the following table. A table of status return values follows the API summary table. R11AN0093EU0100 Rev.1.00 Page 2 of 14

Table 1 Function Name.open.close.calendarTimeSet JPEG Decode Framework Module API Summary Example API Call and Description g_rtc0.p_api->open(g_rtc0.p_ctrl, g_rtc0.p_cfg); Open the JPEG Decode Framework. g_rtc0.p_api->close(g_rtc0.p_ctrl); Close the JPEG Decode Framework. g_rtc0.p_api->calendartimeset(g_rtc0.p_ctrl, &start_time_struct_in, true); Set the calendar time..calendartimeget g_rtc0.p_api->calendartimeget(g_rtc0.p_ctrl, &current_time_struct_out); Get the calendar time..calendaralarmset g_rtc0.p_api->calendaralarmset(g_rtc0.p_ctrl, &in_alarm_time_struct_in, true); Set the calendar alarm time..calendaralarmget g_rtc0.p_api->calendaralarmget(g_rtc0.p_ctrl, &get_alarm_time_struct_out); Get the calendar alarm time..calendarcounterstart g_rtc0.p_api->calendarcounterstart(g_rtc0.p_ctrl); Start the calendar counter..calendarcounterstop g_rtc0.p_api->calendarcounterstop(g_rtc0.p_ctrl); Stop the calendar counter..irqenable g_rtc0.p_api->irqenable(g_rtc0.p_ctrl, CALLBACK); Enable the alarm irq..irqdisable g_rtc0.p_api->irqdisable(g_rtc0.p_ctrl, CALLBACK); Disable the alarm irq..periodicirqrateset g_rtc0.p_api->periodicirqrateset(g_rtc0.p_ctrl, Rate); Set the periodic irq rate..infoget g_rtc0.p_api->infoget(g_rtc0.p_ctrl, clk_src); Return the currently configure clock source for the RTC..versionGet g_rtc0.p_api->versionget(&version); Retrieve the API version with the version pointer. Note: For more complete descriptions of operation and definitions for the function data structures, typedefs, defines, API data, API structures and function variables, review the SSP User s Manual, API References for the associated module. Table 2 Status Return Values Name Description SSP_SUCCESS JPEG Decode driver is successfully opened. SSP_ERR_ASSERTION Assertion error. SSP_ERR_IN_USE Module already in use. SSP_ERR_TIMEOUT The wait operation times out, the underlying driver did not respond in time. SSP_ERR_WAIT_ABORTED System internal error occurred. Note: Lower-level drivers may return common error codes. Refer to the SSP User s Manual API References for the associated module for a definition of all relevant status return values. 3. JPEG Decode Framework Module Operational Overview The JPEG Decode Framework module implements the standard JPEG decode operation. It takes the data in an input buffer and applies the defined JPEG decode algorithm to the buffer; the output is then delivered to the defined output buffer location. A wait API function can be used to suspend/resume the thread for synchronization with JPEG hardware supported events. R11AN0093EU0100 Rev.1.00 Page 3 of 14

3.1 JPEG Decode Framework Module Important Operational Notes and Limitations 3.1.1 JPEG Decode Framework Module Operational Notes You can start decoding JPEG-encoded data by calling the open API. To open the module, use the JPEG Decode Framework module instance that includes the API function pointer, the pointer to the control block and static configuration that is generated through the Synergy Project configurator in the e2 studio for ISDE. Stop the JPEG Decode Framework module by calling the close API. An input buffer-streaming mode is available when an input-centric function is needed. An output buffer-streaming mode is available when an output-centric function is needed. Supports RGB565 and ARGBB888 output data-color formats. The JPEG Decode Framework module has a status flag in the control block; you can get the current status of the module through the statusget API. The status is also reported through a user-callback function when specific events occur in the module. The JPEG Decode Framework module supports buffer-streaming mode for the input buffer in cases when the input buffer is smaller than the source image size. Set the next input frame as an input buffer every time there is a hardware-generated INPUT_PAUSE interrupt. The JPEG Decode Framework module supports buffer-streaming mode for the output buffer in cases when the resultant image is larger than the output buffer-size. Read and store data from the output buffer to make space for upcoming data every time there is a hardware generated OUTPUT_PAUSE interrupt. The input and output buffers should be 8-bytes aligned for the JPEG Decode Framework module to be successful. Otherwise, the APIs return error codes that indicate unsuccessful execution. 3.1.2 JPEG Decode Framework Module Limitations The JPEG Framework module does not support JPEG-encode processing. Refer to the latest SSP Release Notes for any additional operational limitations for this module. 4. Including the JPEG Decode Framework Module in an Application This section describes how to include the JPEG Decode Framework module in an application using the SSP configurator. Note: It is assumed that you are familiar with creating a project, adding threads, adding a stack to a thread and configuring a block within the stack. If you are unfamiliar with any of these items, refer to the first few chapters of the SSP User s Manual to learn how to manage each of these important steps in creating SSP-based applications. To add the JPEG Decode Framework module to an application, simply add it to a thread using the stacks selection sequence given in the following table. (The default name for the JPEG Decode Framework module is g_sf_jpeg_decode0. This name can be changed in the associated Properties window.) Table 3 RTC Selection Sequence Resource ISDE Tab Stacks Selection Sequence g_sf_jpeg_decode0 JPEG Threads New Stack> Framework> Graphics> JPEG Framework Decode Framework on sf_jpeg_decode When the JPEG Decode Framework module on sf_jpeg_decode is added to the thread stack as shown in the following figure, the configurator automatically adds the needed lower-level drivers. Any drivers that need additional configuration information will be highlighted in Red. The specific settings required can be viewed by hovering the cursor over the highlighted text or suggested in the highlighted stack frame. For this stack, the reported requirements for the JPEG HAL module are to enable the decompression-interrupt priority and the data-transfer interrupt-priority interrupts. R11AN0093EU0100 Rev.1.00 Page 4 of 14

Decompression Process Interrupt (JEDI) The JPEG decompression-process interrupt occurs when: Figure 2 JPEG Decode Framework Module Stack The current decompression process is successfully completed. An error happens in the decompression process. Image size and pixel format are successfully read out. Data Transfer Interrupt (JDTI) The JPEG data-transfer interrupt occurs when: All the JPEG-coded data has successfully completed. The number of output image-data lines specified by linesdecodedget has been transferred. The number of input image-data lines specified by inputbufferset has been transferred. 5. Configuring the JPEG Decode Framework Module The JPEG Decode Framework module must be configured by the user for the desired operation. The SSP configuration window automatically identifies (by highlighting the block in red) any required configuration selections, such as interrupts or operating modes, that must be configured for lower-level modules for successful operation. Furthermore, only those properties that can be changed without causing conflicts are available for modification. Other properties are locked and not available for changes and are identified with a lock icon for the locked property in the Properties window in the ISDE. This approach simplifies the configuration process and makes it much less error-prone than previous manual approaches to configuration. The available configuration settings and defaults for all the useraccessible properties are given in the Properties tab within the SSP Configurator and are shown in the following tables for easy reference. Note: You may want to open your ISDE, create the JPEG Decode Framework module and explore the property settings in parallel with looking over the configuration table settings in the following table. This helps to orient you and can be a useful hands-on approach to learning the ins and outs of developing with SSP. Table 4 Configuration for the JPEG HAL Module on r_jpeg ISDE Property Value Description Parameter Checking BSP, Enabled, Disabled (Default: BSP) Enable or disable the parameter error checking. Name g_jpeg_decode0 The name to be used for a JPEG Decode module instance. Byte Order for Input Data Format Normal byte order (1)(2)(3)(4)(5)(6)(7)(8), Byte Swap (2)(1)(4)(3)(6)(5)(8)(7), Specify the byte order for input data. The order is swapped as specified in every 8-byte. R11AN0093EU0100 Rev.1.00 Page 5 of 14

ISDE Property Value Description Word Swap (3)(4)(1)(2)(7)(8)(5)(6), Word-Byte Swap (4)(3)(2)(1)(8)(7)(6)(5), Longword Swap (5)(6)(7)(8)(1)(2)(3)(4), Longword-Byte Swap (6)(5)(8)(7)(2)(1)(4)(3), Longword-Word Swap (7)(8)(5)(6)(3)(4)(1)(2), Longword-Word Swap (7)(8)(5)(6)(3)(4)(1)(2) (Default: Normal Byte order) Byte Order for Output Data Format Output Data Color Format Alpha value to be applied to decoded pixel data (only valid for ARGB8888 format) Name of user callback function Decompression Interrupt Priority Data Transfer Interrupt priority Normal byte order (1)(2)(3)(4)(5)(6)(7)(8), Byte Swap (2)(1)(4)(3)(6)(5)(8)(7), Word Swap (3)(4)(1)(2)(7)(8)(5)(6), Word-Byte Swap (4)(3)(2)(1)(8)(7)(6)(5), Longword Swap (5)(6)(7)(8)(1)(2)(3)(4), Longword-Byte Swap (6)(5)(8)(7)(2)(1)(4)(3), Longword-Word Swap (7)(8)(5)(6)(3)(4)(1)(2), Longword-Word Swap (7)(8)(5)(6)(3)(4)(1)(2) (Default: Normal Byte order) Pixel Data RGB565 format, Pixel Data ARGBB888 format (Default: Pixel Data RGB565 format) Specify the byte order for output data. The order is swapped as specified in every 8-byte. Specify the output data format. 255 Specify the alpha value for the output data format (only valid for ARGB8888 format). NULL Priority 0 (highest), 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 (lowest, not valid if using Thread X), Disabled (Default: Disabled) Priority 0 (highest), 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 (lowest, not valid if using Thread X), Disabled (Default: Disabled) 5.1 JPEG Decode Framework Module Clock Configuration Specify the name of user callback function. JPEG JEDI Interrupt selection JPEG JDTI Interrupt selection The JPEG Framework module uses the peripheral module clock A (PCLKA) to run the internal logic. 5.2 JPEG Decode Framework Module Interrupt Configuration To enable interrupts, set the priority of the decompression interrupt and the data-transfer interrupt in the Properties window of the JPEG Decode Framework module in the ISDE. 5.3 JPEG Decode Framework Module Pin Configuration The JPEG Decode Framework module does not use any pins. R11AN0093EU0100 Rev.1.00 Page 6 of 14

6. Using the JPEG Decode Framework Module in an Application The typical steps in using the JPEG Decode Framework module in an application are: 1. Initialize the JPEG Decode peripheral using the open API. 2. Set Image Subsample using the imagesubsampleset API. 3. Set Horizontal stride using the horizontalstrideset API. 4. Set output buffer using the outputbufferset API. 5. Set Input buffer using the inputbufferset API. 6. Wait for decode to complete with the wait API. 7. Check decode status with the statusget API. 8. Close the instance with the close API (if needed). The following figure illustrates these steps in a typical operational flow. Figure 3 Flow Diagram of a Typical JPEG HAL/Framework Module Application 7. The JPEG Decode Framework Module Application Project The application project associated with this module guide demonstrates the illustrated steps in a full design. The project can be found using the link provided in the References section at the end of this document. You may want to import and open the application project in the ISDE and view the configuration settings for the JPEG Decode Framework module. You can also read over the code in jpeg_decodeimage_mg.c/.h, jpeg_decode_hal_api_mg.h, R11AN0093EU0100 Rev.1.00 Page 7 of 14

jpeg_decode_framework_api_mg.h and jpeg_decode_framework_thread_entry.c. These files are used to illustrate the JPEG Decode Framework APIs in a complete design. The application project demonstrates the typical use of the JPEG Decode Framework APIs. The application project main-thread entry initializes the JPEG Decode HAL and Framework modules in respective entry functions and decodes two different images stored in sample_image1.c and sample_image2.c; the output can be viewed in the ISDE s memory tab during debug operation. A user-callback function is entered when an event occurs during JPEG decoding. The user-specified callback function sets flags for executing programs to determine the course of actions. The following table identifies the target versions for the associated software and hardware used by the application project: Table 5 Software and Hardware Resources Used by the Application Project Resource Revision Description e 2 studio 5.3.1 or later Integrated Solution Development Environment SSP 1.2.0 or later Synergy Software Platform IAR EW for Synergy 7.71.2 or later IAR Embedded Workbench for Renesas Synergy SSC 5.3.1 or later Synergy Standalone Configurator SK-S7G2 v3.0 to v3.1 Starter Kit A simple flow diagram of the application project is given in the following figures. Figure 4 JPEG Decode Framework Module Application Project Flow Diagram The complete application project can be found using the link provided in the References section at the end of this document. The jpeg_decodeimage_mg.c/.h, jpeg_decode_hal_api_mg.h, jpeg_decode_framework_api_mg.h and jpeg_decode_framework_thread_entry.c files are located in the project once it has been imported into the ISDE. You can open these files within the ISDE and follow along with the description provided to help identify key uses of APIs. Descriptions of what each of the files contain is given as well. The jpeg_decode_hal_api_mg.h file is a header file that has inline functions that use HAL APIs for JPEG decoding. Similarly, jpeg_decode_framework_api_mg.h is a header file that has inline functions that use framework APIs provided in the first table of this module guide. The sample_image1.c and sample_image2.c image files are stored in hexadecimal array format. The extended dump and code utility software tool is used to convert a JPEG image to hexadecimal C array (link is provided as described in the References section.) The sample_image1.c data is decompressed by the HAL APIs and the sample_image2.c data is decompressed by the framework decode application in this application project. The jpeg_decode_image_mg.h file contains a function prototype, macros, and a declaration of flags that are used by the callback function. The jpeg_decode_image_mg.c file contains the application code which uses HAL and Framework APIs to decode JPEG images. This file also contains callback function to set flags when the JPEG decode events occur. This file includes code for JPEG decompression using the HAL and framework modules. The jpeg_decode_hal_run() function is an entry point to JPEG HAL decoding. The following figure explains the flow of this function: R11AN0093EU0100 Rev.1.00 Page 8 of 14

Figure 5 JPEG Decode Framework Module Application Project Flow Diagram The jpeg_decode_framework_run() function is an entry point to JPEG HAL decoding. The following figure explains the flow of this function: R11AN0093EU0100 Rev.1.00 Page 9 of 14

Figure 6 JPEG Decode Framework Module Application Project Flow Diagram Note: This description assumes you are familiar with using printf()with the Debug Console in the Synergy Software Package. If you are unfamiliar with this, refer to the How do I Use Printf() with the Debug Console in the Synergy Software Package Knowledge Base article, available as described in the References section at the end of this document. Alternatively, the user can see results via the watch variables in the debug mode. A few key properties that are configured in this application project to support the required operations and the physical properties of the target board and MCU. The following table lists the properties with the values set for this specific project. You can also open the application project and view these settings in the Properties window as a hands-on exercise. R11AN0093EU0100 Rev.1.00 Page 10 of 14

Table 6 JPEG Decode Framework Module Configuration Settings for the Application Project Resource ISDE Property Value Set g_sf_jpeg_decode0 Parameter Checking Enable JPEG Decode Framework on r_jpeg g_jpeg_decode0 Parameter Checking Enabled JPEG Decode Driver Name g_jpeg_decode0 on r_jpeg Byte Order for Input Data Format Normal byte order (1)(2)(3)(4)(5)(6)(7)(8) Byte Order for Output Data Format Normal byte order (1)(2)(3)(4)(5)(6)(7)(8) Output Data Color Format Pixel Data RGB565 format Alpha value to be applied to decoded 255 pixel data (only valid for ARGB8888 format) Name of user callback function jpeg_decode_callback Decompression Interrupt Priority Priority 3 Data Transfer Interrupt priority Priority 3 8. Customizing the JPEG Decode Framework Module for a Target Application Some configuration settings are normally changed by the developer from those shown in the application project. For example, the user can easily change the byte order for the input/output buffer, output-data format or the alpha value to be applied to the decoded pixel data. The user can also change the horizontal stride value, image subsample value and input/output image size through the APIs. 9. Running the JPEG Decode Framework Module Application Project To run the JPEG Framework module application project and to see it executed on a target kit, you can simply import it into your ISDE, compile and run debug. See Importing a Renesas Synergy Project. (11an0023eu0116-synergy-ssp-import-guide.pdf, included in this package) for instructions on importing the project into ISDE or IAR EW for Synergy and building/running the application. Note: The following steps are described in sufficient detail for someone experienced with the basic flow through the Synergy development process. If these steps are not familiar, refer to the first few chapters of the SSP User s Manual for a description of how to accomplish these steps. To create and run the JPEG Decode Framework module application project, simply follow these steps: 1. Import the attached example project JPEG_Decode_MG_AP to the ISDE or IAR EW for Synergy. For steps to import the example project, refer to the Importing a Renesas Synergy Project. 2. Compile the application without errors and warnings. 3. Connect to the host PC via a micro USB cable to J19 on SK-S7G2 Synergy MCU Group. 4. Start to debug the application. 5. LED1-3 toggle periodically when communication is ongoing. To view the decoded image, follow these steps: A. While the application example is running in debug mode, go to the Memory tab shown in the following figure and click the + sign to add the address locations jpeg_decoded_img1 and jpeg_decoded_img2. (Output buffer starting addresses). R11AN0093EU0100 Rev.1.00 Page 11 of 14

B. Click on tab New Renderings for each memory address and double click on the Raw Image option and click on Raw Image Format button. C. Fill in the information displayed in the following figure. The pop-up window opens after step 2 and press Ok. D. Observe the following outputs (output 1 and output 2 respectively). Figure 7 Example Output from JPEG Decode Framework Module Application Project 10. JPEG Decode Framework Module Conclusion This module guide has provided all the background information needed to select, add, configure and use the JPEG Framework module in an example project. Many of these steps were time consuming and error-prone activities in previous generations of embedded systems. The Renesas Synergy Platform makes these steps much less time consuming and removes the common errors, such as conflicting configuration settings or the incorrect selection of lower-level drivers. The use of high-level APIs (as demonstrated in the application project) illustrates additional development time savings by allowing work to begin at a high level and avoiding the time required in older development environments to use, or in some cases, create lower-level drivers. R11AN0093EU0100 Rev.1.00 Page 12 of 14

11. JPEG Decode Framework Module Next Steps After you have mastered a simple JPEG Decode project, you may want to use these APIs in your example that decodes JPEG files and uses an LCD to display the decompressed image. Also, try using this example with streaming input and output buffers, high decompression settings or images with different color formats. 12. JPEG Decode Framework Module Reference Information SSP User Manual: Available in html format in the SSP distribution package and as a pdf from the Synergy Gallery. Links to all the most up-to-date sf_jpeg_decode module reference materials and resources are available on the Synergy Knowledge Base: https://enus.knowledgebase.renesas.com/english_content/renesas_synergy%e2%84%a2_platform/renesas_synergy_knowle dge_base/sf_jpeg_decode_module_guide_resources. R11AN0093EU0100 Rev.1.00 Page 13 of 14

Website and Support Support: https://synergygallery.renesas.com/support Technical Contact Details: America: https://renesas.zendesk.com/anonymous_requests/new Europe: https://www.renesas.com/en-eu/support/contact.html Japan: https://www.renesas.com/ja-jp/support/contact.html All trademarks and registered trademarks are the property of their respective owners. R11AN0093EU0100 Rev.1.00 Page 14 of 14

Revision History Description Rev. Date Page Summary 1.00 - Initial Release

Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawing, chart, program, algorithm, application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics products. 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for each Renesas Electronics product depends on the product s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. When using the Renesas Electronics products, refer to the latest product information (data sheets, user s manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat radiation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions or failure or accident arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please ensure to implement safety measures to guard them against the possibility of bodily injury, injury or damage caused by fire, and social damage in the event of failure or malfunction of Renesas Electronics products, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures by your own responsibility as warranty for your products/system. Because the evaluation of microcomputer software alone is very difficult and not practical, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please investigate applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive carefully and sufficiently and use Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall not use Renesas Electronics products or technologies for (1) any purpose relating to the development, design, manufacture, use, stockpiling, etc., of weapons of mass destruction, such as nuclear weapons, chemical weapons, or biological weapons, or missiles (including unmanned aerial vehicles (UAVs)) for delivering such weapons, (2) any purpose relating to the development, design, manufacture, or use of conventional weapons, or (3) any other purpose of disturbing international peace and security, and you shall not sell, export, lease, transfer, or release Renesas Electronics products or technologies to any third party whether directly or indirectly with knowledge or reason to know that the third party or any other party will engage in the activities described above. When exporting, selling, transferring, etc., Renesas Electronics products or technologies, you shall comply with any applicable export control laws and regulations promulgated and administered by the governments of the countries asserting jurisdiction over the parties or transactions. 10. Please acknowledge and agree that you shall bear all the losses and damages which are incurred from the misuse or violation of the terms and conditions described in this document, including this notice, and hold Renesas Electronics harmless, if such misuse or violation results from your resale or making Renesas Electronics products available any third party. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (Rev.3.0-1 November 2016) SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com 2017 Renesas Electronics Corporation. All rights reserved. Colophon 6.0