Reg No Name FIFTH SEMESTER B.TECH DEGREE EXAMINATION MODEL TEST QUESTION PAPER, NOVEMBER 2017 CS 305: Microprocessor and Microcontrollers Max. Marks: 100 Duration: 3 Hours PART A Answer all questions. Each carries 3 marks 1. Define macro and subroutine with example. 2. Explain the use of following 8086 signals a. HOLD, and HLDA b. DEN and BHE 3. Explain the procedure for generating physical address and generate the physical address corresponds to the segment address 1055H and offset address 5555H 4. Explain the indexed addressing and based index addressing modes of 8086 with examples 5. PART B Answer any Two questions. Each carries 9 marks a. Draw the maximum mode circuit connections of 8086 b. Write an 8086 programme to find factorial of a number using procedure 6. a. Write an 8086 assembly language programme to convert ASCII to decimal conversion using macro. b. Draw the minimum mode of 8086 bus timing for a memory read and write operations. 7. What are the different addressing modes available in 8086 PART C Answer all questions. Each carries 3 marks 8. Explain the different types of interrupts in 8086
9. Discuss about fixed addressing and variable port addressing in i/o interfacing with 8086. 10. What are the registers available in DMA controller? Mention its use 11. Explain the use of keyboard / display controller- 8279 PART D Answer any Two questions. Each carries 9 marks 12. What do you meant by an interrupt and how an interrupt is handled in 8086 13. a. Write about memory mapped i/o and isolated i/o. b. Interface Two 16X8 ROM and Two 32X8 RAM with 8086. Select the starting address of EPROM suitably. The RAM address must start at 00000H. 14. Briefly explain the architecture of programmable input-output (8255) PART E Answer any four questions. Each carries 10 marks 15. a. Write about Microcontrollers and its types. (4 marks) b. Discuss the factors to be considered while selecting microcontrollers. c. Mention the applications of Microcontrollers. 16. Draw and explain the architecture of 8051 17. a. Briefly explain the interrupt structure of 8051. b. Write an assembly language program to compute x to the power n where both x and n are 8- bit numbers given by the user and the result should not be more than 16 bits using 8051 18. a. Explain the different addressing modes of 8051 b. Write an assembly language program to count the number of 0s and 1s in an 8- bit number using 8051 19. Explain the different types of instructions available in 8051. 20. Write a note on Programmable Interval Timer.
Answer Key PART A 1. Macro and Subroutine (3 marks) 2. A macro call is an instruction to replace the macro name with its body, whereas subroutine call is an instruction to transfer the program s control to the subroutine s definition with all parameters, if required. A macro call results in macro expansion, whereas subroutine call results in execution. Macro expansion increases the size of the program but subroutine execution doesn t affect the size of the program Macro expansion doesn t affect the execution speed of the program much in comparison to subroutines affect the execution speed of the program a. HOLD: Input signal to the processor form the bus masters as a request to grant the control of the bus. Usually used by the DMA controller to get the control of the bus. HLDA: Is an Acknowledgment signal from the processor for HOLD (1.5marks) b. DEN (Data Enable): Output signal from the processor used as out put enable for the transceivers and BHE (Bus High Enable): It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. (1.5 mark) 3. In Indexed mode, Displacement is added to the index value in SI or DI register to obtain the EA. In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value. (1 mark) Example: MOV CX, [SI + 0A2H] (1/2 mark) In Based Index Addressing, the effective address is computed from the sum of a base register (BX or BP), an index register (SI or DI) and a displacement. (1 mark) Example: MOV DX, [BX + SI + 0AH] (1/2 mark) 4. Steps 1. Segment address shifted by 4 bit positions 2. Add shifted segment address with offset address (1 mark) Problem (2 marks) 4 bit left shift segment address 0001 0000 0101 0101 0000 + Offset address 0101 0101 0101 0101 0001 0101 1010 1010 0101
PART B Physical Address is 15AA5 5. a. Include Block diagram (3 marks) Description of the signals used (1.5 marks) b. ALP for finding factorial of a number MASM Program(3 marks) Macro definition(1.5 marks) 6. a. ALP To do ASCII to decimal conversion MASM Program(3 marks) Macro definition(1.5 marks) b.draw the memory read and write operations
Memory read (2.25 marks) Memory write (2.25 marks) 7. Addressing modes (9 marks) It refers to the way in which operands can be specified. 1. Immediate addressing mode
The addressing mode in which the data operand is a part of the instruction itself Example MOV CX, 3456H 2. Direct addressing mode The addressing mode in which the effective address of the memory location is written directly in the instruction. Example MOV AX, [4000H] 3. Register addressing mode It means that the register is the source of an operand for an instruction. Example MOV AX,BX 4. Register indirect addressing mode This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI & SI. Example MOV AX, [BX] 5. Indexed addressing mode Here the offset of the operand is stored in one of the index registers. DS is the default segment for SI and DI, in case of string instructions DS and ES are the default segments for SI and DI respectively. Example MOV AX, [SI] The effective address is computed as 10H *DS+[SI] 6. Register Relative The data available at an effective address formed by adding 8-bit / 16 bit displacement with the contents of the registers Example MOV AX, 50H [BX] The effective address is computed as 10H *DS+50H+[BX] 7. Based Index In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of an Index register. Example MOV CX, [BX] [SI] The effective address is computed as 10H *DS+[BX]+[SI]
8. Relative Based Index In this addressing mode, the operands offset is computed by adding the base register contents with an Index registers contents and 8 or 16-bit displacement. Example MOV CX, 20H [BX] [SI] The effective address is computed as 10H *DS+10H+[BX]+[SI] 9. Intrasegment Direct Mode In this mode, the address to which the control is to be transferred lies in the same segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value Example JMP SHORT LABEL 10. Intrasegment Indirect Mode In this mode, the address to which the control is to be transferred lies in the same segment in which the control transfer instruction lies, but it is passed to the instruction indirectly Example JMP [BX]: Jump to the effective address stored in BX 11. Intersegment Direct Mode In this mode, the address to which the control is to be transferred is in a different segment. Here CS and IP of the destination address are specified directly in the instruction. Example JMP 5000H: 3000H Jump to the effective address 3000H in segment 5000H 12. Intersegment Indirect Mode In this mode, the address to which the control is to be transferred is in a different segment and is passed indirectly. Example JMP [5000H] Jump to an address in other segment specified at 5000H in DS PART C 8. NON-MASKABLE INTERRUPT (1.5 marks) The processor has non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR) and it is of type 2 interrupt. Example TRAP The NMI is activated on positive transition
MASKABLE INTERRUPT (1.5 marks) A maskable interrupt is one that can be ignored by setting (or clearing) a bit in an interrupt control register. Example INTR The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. 9. Fixed Port Addressing (1.5 marks) Fixed port addressing is of 8-bit. In this case, only the lower AX, that is, AL is used. Here the address of the port is directly mentioned in the instruction Example address 45H Variable Port Addressing IN AL, 45H Move 8-bit data from an input port with the This is used when the addressed port has 16-bit address (1.5 marks) The port address is to be loaded in DX and then only i/o instruction can be used. Example MOV DX,3458H IN AL, DX address is in DX 10. DMA Address Register Move 8-bit data from an input port whose Each DMA channel has one DMA address register. The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel. Terminal Count Register Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit register isused for ascertaining that the data transfer through a DMA channel ceases or stops after the required number of DMA cycles. Mode Set Register The mode set register is used for programming the 8257 as per the requirements of the system. The function of the mode set register is to enable the DMA channels individually and also to set the various modes of operation. Status Register
The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the terminal count status for the four individual channels. If any of these bits is set, it indicates that the specific channel has reached the terminal count condition. 11. Input (Keyboard) modes and Output (Display) modes Input (Keyboard) modes : 8279 provides three input modes, they are : 1.ScannedKeyboardMode: This mode allows a key matrix to be interfaced using either encoded or decoded scans. In the encoded scan, an 8 x 8 keyboard or in decoded scan, a 4 x 8 Keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM. 2. Scanned Sensor Matrix: In this mode, a sensor array can be interfaced with 8279 using either encoder or decoder scans. With encoder scan 8 x 8 sensor matrix or with decoder scan 4 x 8 sensor matrix can be interfaced. 3. Strobed Input : In this mode, if the control line goes low, the data on return lines, is stored in the FIFO byte by byte. Output (Display) Modes : 8279 provides two output modes for selecting the display options. 1. Display Scan: In this mode, 8279 provides 8 or 16 character multiplexed displays those can be organized as dual 4-bit or single 8-bit display units
2. Display Entry: The Display data is entered for display either from the right side or from the left side. 12. An INTERRUPT is a condition that causes the microprocessor to temporarily work on a different task and then return to its previous task. Interrupt is an event or signal that request to attention of CPU. 8086 Interrupts We are aware of the fact that the interrupt can be either hardware or software. If the interrupts are generated by the inbuilt devices, like timers or by the interfaced devices, they are called as hardware interrupts. NMI It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt. INTR The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. The INTR interrupt is activated by an I/O port. If the interrupts are generated by the software code, they are called as software interrupts. INT- Interrupt instruction with type number The first five pointers are dedicated interrupt pointers. TYPE 0 interrupt represents division by zero situation. TYPE 1 interrupt represents single-step execution during the debugging of a program. TYPE 2 interrupt represents non-maskable NMI interrupt. TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt. INT 3-Break Point Interrupt Instruction It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches there, then it stops the normal execution of program and follows the break-point procedure. INTO - Interrupt on overflow instruction Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the main routine where it was interrupted. Interrupt Service Routine For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt is invoked, the microprocessor runs the interrupt service routine. For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table. When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the content of program counter into stack. It also stores the current status of the interrupts internally but not on stack. After this, it jumps to the memory location specified by Interrupt Vector Table (IVT). After that the code written on that memory area will execute. Interrupt Vector Table The first 1Kbyte of memory of 8086 (00000 to003ff) is set aside as a table for storing the starting addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. The starting address of an ISP is often called the Interrupt Vector or Interrupt
Pointer. Therefore the table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector & CS is put in high vector. 13. a)draw and explain 1.Isolated i/o(2.5marks) 2.Memory mapped i/o(2marks) b) explaining details(4.5marks) MMIO is used in real MIPS processors. It uses addresses from 0xffff0000 to 0xffffffff (in kernel). 14. 8255 Programmable Peripheral Interface (PPI) Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status informa-tion are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the CPU. (RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255. (WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 8255. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). (RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode.
A1 A0 SELECTION 0 0 PORT A 0 1 PORT B 1 0 PORT C 1 1 CONTROL Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Ports A, B, and C The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 8255. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.
PART E 15. Explain a) Microcontroller- A microcontroller (μc or uc) is a solitary chip microcomputer fabricated from VLSI fabrication. A micro controller is also known as embedded controller(.5marks) functional unit(1.5marks)( CPUMemoryInput/output portsserial Ports TimersADC (Analog to digital converter)dac (digital to analog converter) Interpret Control-Special Functioning Block) Microcontrollers are divided into categories according to their memory, architecture, bits and instruction sets. So types of microcontrollers(2marks) Bits: 1. 8 bits microcontroller executes logic & arithmetic operations. Intel 8031/8051. 2. 16 bits microcontroller executes with greater accuracy and performance in contrast to 8-bit. Example Intel 8096. 3. 32 bits microcontroller is employed mainly in automatically controlled appliances such as office machines, implantable medical appliances, etc. Memory:
1.External Memory Microcontroller When an embedded structure is built with a microcontroller which does not comprise of all the functioning blocks existing on a chip it is named as external memory microcontroller. 2.Embedded Memory Microcontroller When an embedded structure is built with a microcontroller which comprise of all the functioning blocks existing on a chip it is named as embedded memory microcontroller. Instruction Set: 1. CISC- CISC means complex instruction set computer. 2. RISC- RISC means Reduced Instruction Set Computers Memory Architecture: 1. Harvard Memory Architecture Microcontroller 2. Princeton Memory Architecture Microcontroller b)criteria Efficiency, cost effective Speed Packaging Power consumption Amount of RAM and ROM No of I/O pin and timer Easiness in developing product Availability in needed quantities c) Each application carry 1 mark Application of Microcontroller in Day to Day Life Devices: 1. Light sensing & controlling devices 2. Temperature sensing and controlling devices 3. Fire detection & safety devices 4. Industrial instrumentation devices 5. Process control devices Application of Microcontroller in Industrial Control Devices: 1. Industrial instrumentation devices 2. Process control devices Application of Microcontroller in Metering & Measurement Devices: 1. Measuring revolving objects 2. Volt Meter 3. Current meter 4. Hand-held metering systems
16. Draw the block diagram neatly(3marks) Explaining functional blocks in detail(7marks) Salient features of 8051 microcontroller are given below. Eight bit CPU On chip clock oscillator 4Kbytes of internal program memory (code memory) [ROM] 128 bytes of internal data memory [RAM] 64 Kbytes of external program memory address space. 64 Kbytes of external data memory address space. 32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O lines) Two 16 Bit Timer/Counter :T0, T1 Full Duplex serial data receiver/transmitter Four Register banks with 8 registers in each bank. Sixteen bit Program counter (PC) and a data pointer (DPTR) 8 Bit Program Status Word (PSW) 8 Bit Stack Pointer Five vector interrupt structure (RESET not considered as an interrupt.) 8051 CPU consists of 8 bit ALU with associated registers like accumulator A, B register, SW, SP, 16 bit program counter, stack pointer. ALU can perform arithmetic and logic functions on 8 bit variables. 8051 has 128 bytes of internal RAM which is divided into
Working registers [00 1F] Bit addressable memory area [20 2F] General purpose memory area (Scratch pad memory) [30-7F] 8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the program size is more than 4 K Bytes 8051 will fetch the code automatically from external memory. Accumulator is an 8 bit register widely used for all arithmetic and logical operations. Accumulator is also used to transfer data between external memory. B register is used along with Accumulator for multiplication and division. A and B registers together is also called MATH registers. PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of ALU and the bank select bits of register banks. 17. a) explain five interrupts. They are maskable and vectored interrupts. Out of these five, two are external interrupt and three are internal interrupts. 8051 makes use of two registers to deal with interrupts. 1. IE Register This is an 8 bit register used for enabling or disabling the interrupts. Explain and draw the structure of IE register. 2. IP Register. This is an 8 bit register used for setting the priority of the interrupts b) writing program effectively(5 marks) 18. a)explain in brief(5marks) immediate, register, direct, indirect addressing mode with example b) writing program effectively(5 marks) 19. Explain arithmetic instruction with example(2marks) logic and compare instruction with example(2marks) rotate and data serialization instructions(2marks)
20. data transfer instructions(2marks) branch instructions(2marks) Draw block diagram (1.5marks) explain the functional unit(7marks) List applications(1.5marks) 1.Interrupt a time sharing operating system at evenly spaced intervals so that it can switch a program 2. Programmable one shot generator 3. Serve as a programmable baud rate generator. 4. Measure time delays between external events. 5. Count the number of times an event occurs. 6. Causes the processer to be interrupted after a programmed number of external events have occurred. 7. Real time clock.. Prepared By MUMTHAS T.K, JINSHA K