EE 214 Lab 7 Computer-Based Minimization Tools Page 1/8

EE 214 Lab 7 Computer-Based Minimization Tools Page 1/8 Overview NAME: SECTION: Logic functions can be described using behavioral descriptions or structural descriptions. Behavioral descriptions, such as truth tables, worded descriptions, or minterm/maxterm equations, describe the behavior of a logic function without providing any information about how that function might actually be constructed. Behavioral descriptions are easy for humans to read and understand. They use simple, high-level forms, and little or no attention is paid to finding or using minimal (or even reduced) expressions. As an example, a behavioral description might be "whenever switches A and B are on at the same time that C is off, or whenever A is on and B and C are off, or whenever C is on and A is on, the light should be turned on". This worded description can readily be transformed to the equivalent minterm equation L = Σm(4,5,6,7), and/or to a truth table. All three descriptions give a clear picture of the intended logic system, but say nothing of the eventual circuit's structure. Clearly, a minimum expression of the intended logic function should be found before a circuit is constructed. The engineering process starts with a behavioral description of a circuit or system. But before the circuit or system can be built, the behavioral description must be molded into a form that can be directly constructed: a structural description. A structural description, such as a minimized Boolean equation or a logic circuit schematic, describes the intended function in a form that can be directly implemented. The process of transforming a behavioral description to a structural description is commonly called design when done by humans, and synthesis when done by computers. For example, a structural description of the logic problem mentioned above would be L=A or a schematic showing a wire connecting output L directly to input A. Whereas behavioral descriptions are most useful in earlystage design activities, structural descriptions are required for late-stage design activities. So far, we have focused on several design techniques (such as using Boolean algebra or K-maps) that can be used to transfer a behavioral description into a minimized structural description. In practice, the more time spent at the "front-end" of a design, studying and perfecting the behavioral description of a given system, the better. A collection of computer-based tools, including minimizers, synthesizers, optimizers, etc., has evolved that can take a high-level behavioral description and create a nearoptimum structural description. Using these tools, an engineer can spend more time investigating design requirements and experimenting with various design approaches, and less time worrying about implementation details. After a design problem has been well analyzed, the best design can be readily reduced to a minimal (or near-minimal) structural description using computer-based tools. When using such tools, you must be very clear in describing the intended logic function, and you must be able to critically interpret the output. These tools should never be used as substitutes for detailed design knowledge; rather, they should only be used as labor-savors. This lab presents several logic-minimization computer programs that can be used to simplify more complex logic systems. Minimization programs are regularly used by designers when they are working with functions that have more than one output or more than five inputs. Some programs, such as those based on the Quine-McCluskey algorithm, find a true minimum by exhaustively checking all possibilities. Programs based on these exhaustive search algorithms can require long execution times, especially when dealing with large numbers of inputs. Other programs, such as the popular Espresso program developed at UC Berkeley, use heuristic (or rule-based) methods instead of exhaustive searches. Although these programs run much faster (especially on moderate to large systems), they terminate upon finding a "very good" solution that may not always be minimal. In many real-world engineering situations, finding a greatly minimized solution quickly is often the best approach.

EE 214 Lab 7 Computer-Based Minimization Tools Page 2/8 It often occurs in the design of digital circuits and systems that several outputs must be generated at the same time from the same set of inputs. In this lab, we'll use a classic example of a circuit that has four inputs and seven outputs -- a seven-segment display decoder. Seven segment displays, described below, can be configured to display any of the decimal digits by selecting which segments are active and which are dormant. The seven-segment display device on the Digilab I/O board requires seven logic signals to drive the segment inputs -- placing 5V on a segment's input will cause the segment to illuminate. In a digital system, where all information must be encoded as HV or LV, numbers must be represented using the binary number system. The ten decimal digits can be represented by the first ten four-bit binary numbers -. A seven-segment decoder receives as inputs four signals that represent the four bits of a binary number (B3-B0), and produces as output the seven segment-driving logic signals. In this lab, we will attack the design of a seven segment decoder using several different methods. In the initial exercise, the design requirements will be firmly established. In the second exercise, pencil-and-paper solution methods will be investigated. Then in the next three exercises, different computer-based tools will be used to solve the problem. Seven Segment Displays Seven-segment displays (7sd) are some of the most common electronic display devices in use. They can be used to display any decimal digit by illuminating segments in various patterns (see right). The four 7sd devices on the Digilab I/O board are each built from seven LEDs that have been arranged in a figure "8" pattern as shown in the figure on the right. These LEDs are identical in function to the nine individual LEDs on the I/O board -- they emit light when a small current (about 20mA) passes through them. By controlling which LED segments are illuminated, we can control which digit is displayed. As examples, if only segments b and c are illuminated, then the display will show a '1', and if only segments a, b and c are illuminated then the display will show a '7'. GND placed here will cause LED to emit light; the 7- segment LEDs use this circuit Vdd 270 ohms 270 ohms GND 5V placed here will cause LED to emit light; the individual LEDs use this circuit These two circuits are equivalent. To illuminte the LED on the left, GND must be applied to the resistor in the cathode lead, and to illuminate the LED on the right, 5V must be applied to resistor in the anode lead. To anode connection To cathode connection One segment enlarged Each segment of the 7sd contains a single LED labeled a-g. Segment illumination patterns for the first five digits are shown. The individual LEDs on the Digilab I/O board have resistors in their anode leads, while the 7sd LEDs have resistors in their cathode leads (see left). Thus, the individual LEDs can be illuminated by applying a 5V signal to the anode inputs labeled LD1 - LD9 on J9. The 7sd LEDs can be illuminated by applying GND to the cathode inputs labeled CA - CG on J9. Additionally, for reasons that will become clear in later labs, 5V must be connected to the common anode lead for each digit that you wish to use. For this lab, we will only use the 1 st digit, so only the input labeled A1 on J9 needs to be connected to 5V. f e a g d b c

EE 214 Lab 7 Computer-Based Minimization Tools Page 3/8 Part 1 (%). Background for designing a 7sd Decoder At the outset of a new design project, prior to beginning any design activities, you must strive to gain a very clear mental picture of the circuit or device that you intend to create. It is often advantageous to gain experience with your intended design by simulating (using a computer program) or emulating (using actual circuit hardware) the behavior of the intended circuit or device before beginning the actual design. In this first exercise, you are asked to construct a simple circuit that you can use to gain a clear understanding how a 7sd device functions. Using just the Digilab board and eight wires (no chips), you can drive one of the 7sd devices, and see exactly what segments must be illuminated to form the various digits. a) Insert one end of each of seven wires into the first seven switch connections on J9 (S1-S7), and insert the other wire ends into the J9 connections labeled CA through CG (connect S0 to CA, S1 to CB, etc.). Then insert one end of a wire into the J9 connection labeled A1, and the other end of the wire in an open VDD connection. Now you can use the switches to directly illuminate the first 7sd device. By moving the switches back and forth, you can illuminate various segment patterns and learn which segments must be illuminated to cause each of the nine decimal digits to be displayed. 5V must be applied to the LED anodes using the J9 A1-A4 connections GND must be applied to whichever segment is to be illluminated using the J9 CA-CG connections The 7sd devices on the Digialb board are configured as shown. To cause a segment to illuminate, 5V must be applied to the common anode connection, and GND must be applied to which ever segment is to be illuminated. Inputs Outputs Decimal Four-bit binary number Seven functions that will drive Digit representing digits 0-9. the individual display segments B3 B2 B1 B0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 NA 1 0 1 0 NA 1 0 1 1 NA 1 1 0 0 NA 1 1 0 1 NA 1 1 1 0 NA 1 1 1 1 A B C D E F G b) The table on the left shows the nine decimal digits, their binary equivalents, and seven columns labeled A-G. The columns labeled A-G can be used to record when a segment must be illuminated to display a given digit. For example, in the first row corresponding to the digit '0', segments A,B,C,D,E, and F must be illuminated, so a '1' must be placed in those columns. Complete all the rows of the table by placing a '1' in an output column when a given segment must be illuminated to form the digit, and a '0' when the segment must not be illuminated. When completed, the table on the left can serve as a truth table for the seven-segment controller -- it shows the required logic relationship between the four inputs and seven outputs.

EE 214 Lab 7 Computer-Based Minimization Tools Page 4/8 Note that in the truth table, the last six input patterns ( through ) are not associated with a decimal digit. They are therefore "illegal" inputs, and all outputs columns can receive a don't care for those rows. Part 2 (15%). Pencil-and-paper 7sd Controller design The goal in this section is to use pencil-and-paper methods to design a 4-input, 7-output circuit that can drive the 7sd LEDs to display the decimal digits. The four inputs are the four bits of a binary number in the range -, and the seven outputs are logic signals that can drive the segments. A block diagram for the circuit is shown below. The first step in the design process is to transfer the information from the truth table above to seven K- maps (one for each output function) so that minimal circuits can be found. Then, logic circuits for each segment can be extracted from the K-maps individually. But to create a minimal circuit, we should try to find all prime implicants that are shared between two or more of the output functions and then use them wherever possible. The process of finding the shared prime implicants can be quite exhaustive; with this many functions, it could be a highly frustrating challenge. a) Populate the K-maps below by transferring the data from the previous truth table. b) The second step would be to find all shared prime implicants -- in this case, we'll skip that step. c) The third step would be to loop the K-maps using the list of shared prime implicants. Prior to looping the K-maps, we'll use some computer-based programs to help us find minimal solutions. B3 B2 B1 B0 A B C D E F G B3B2 B3B2 B3B2 Seven-segment decoder block diagram A B C B3B2 B3B2 B3B2 B3B2 D E F G

EE 214 Lab 7 Computer-Based Minimization Tools Page 5/8 Part 3 (25%). Quine-McCluskey algorithm-based tools The Quine-McCluskey logic minimization algorithm was developed in the mid-1950's, and it was the first computer-based algorithm that could find a minimal expression. The algorithm finds all possible prime implicants through an exhaustive search, and then from that collection finds a minimal set that covers all minterms in the on-set (recall the on-set is the set of all minterms for which the function output is asserted). Because this method searches for all possible solutions, and then selects the best, it can take a fair amount of computing time. The program based on the Qunie-McCluskey algorithm called switchmin, available on the lab PC's and from the website: http://incolor. inetnebr.com/double/softlib/switchmin.html, can handle up to 32 inputs and an unlimited number of outputs. It is windows based, and features a simple and intuitive interface. It can provide outputs in several formats, including minimized Boolean expressions as well as SOP and POS circuit sketches. a) Run the switchmin program, and select File New from the File pulldown menu. A dialog box will appear that can be used to enter functions. b) Select the Outputs tab from the dialog box. c) Select Edit Add Functions, causing the Function Entry dialog box to appear. Enter the function for the segment A by typing the function name ("A" in this case) in the provided area, and then by enter all the minterms for function A in the "terms" box. Separate each minterm in the list with a comma, and be sure to enter all don't cares as well. d) Add the remaining six functions in the same manner. e) Select Tools Minimize. In the dialog box that opens, place a check mark in all boxes, and then click on "OK". f) When you get tired of waiting for the output to appear, read the hint below (you will need to terminate the current SwitchMin process). g) In the output viewing screen, click on "lc" in the upper right corner to see the POS output, and "ld" to see the SOP output. For systems using more than three outputs, you will see several numbered lc and ld solutions -- choose the lowest cost solution for viewing. You can click on Boolean equations, or AND/OR, NAND, or NOR depending on the output view you wish to use. (You may need to zoom in or out using the zoom function at the bottom of the display). h) Print out a hard-copy of the SOP logic functions, and attach it to your lab report. i) By referring to this output, loop out all functions in the K-maps you completed earlier. SwitchMin hint: SwitchMin requires more than an hour on a P-III 550 to minimize all seven functions simultaneously. I suggest chopping the problem into two pieces -- the first piece can minimize a, b and c, and the second piece d, e, f, and g. Note that you will not get an overall system minimum in this way; you will at least get an output that is piece-wise minimum. Part 4. (25%) Espresso Espresso is a logic minimization program in common use in industry today, and (unfortunately) it only runs in a DOS environment. You must first prepare an input file describing the logic function to be minimized before the program can execute. Although it may seem a little awkward to use initially, the big advantage to Espresso is that it can be used not only to minimize a single logic function of several variables, but many logic functions of several variables as well. Unlike the Quine-McCluskey algorithm, espresso uses a heuristic algorithm that does not guarantee a minimum expression. It does, however, run much faster for larger systems.

EE 214 Lab 7 Computer-Based Minimization Tools Page 6/8 Running Espresso Espresso is a DOS program that must be run from the DOS prompt. Espresso must be given an input file describing the logic system to be minimized, and it produces an output file with the minimized results. The input and output files are described below. To run Espresso, perform the following steps. 1. In W95, go to START program MSDOS prompt 2. Change directories to your network directory on Bradbury. 3. At the DOS prompt, type espresso filename, where filename is the name of the input file you have created (see below). Espresso will automatically create an output file called filename.out containing the minimized results. 4. To view the output file, type type filename.out at the DOS prompt, or load the file into an editor. Espresso Input Files All logic data input to Espresso must be in minterm format. For example, in the logic equations F1(A, B, C, D) = Σm(4,5,6,8,9,,13) + φ(0,7,15) F2(A, B, C, D) = Σm(1,5,6,7,) + φ(13,15) the minterms 1,4,5,6, would appear as,,, in the Espresso input file. Minterms can be entered into Espresso when the function output is asserted (i.e., logic 1), when the output is a don t care, or when the output is not asserted (i.e., a logic 0). Typically, minterms are only input into espresso when the function output is either a 1 or a don t care -- espresso assumes that any minterms not found in the input file contribute a logic 0 to the function output. Following is an annotated example of an Espresso input file. This input file is derived from the example binary logic equations above. Any text editor can be used to create an input file (i.e., use notepad, wordpad, or the DOS edit filename command, where filename is your chosen name for the input file). Example Espresso input file.i 4.i n tells espresso n logic inputs are present.o 2.o m tells espresso m functions are present.ilb A B C D all input variable names are provided on the.ilb line.ob F1 F2 the function name(s) are provided on the.ob line.p.p N tells espresso that N product terms (minterms) follow 0 Listing of minterms derived from the equation above. Note that an input row exists for all minterms from both equations, including the don't cares. The output columns indicate whether a minterm is included as a "1", "0", or -1 don't care in the logic equation. 1- -.e.e is the last line of the input file

EE 214 Lab 7 Computer-Based Minimization Tools Page 7/8 Espresso Output Files Running espresso (by typing espresso filename at the DOS prompt) will cause an output file, called filename.out, to be automatically created. If espresso were run with the above input file, the following output file would be produced. The file has been annotated for reference. Example Espresso output file.i 4 These first four line are simply copied to the output file from the.o 2 input file..ilb A B C D.ob F1 F2.p 6 Number of product terms required in the minimized output Product terms produced by espresso. A - appearing in the first four -0 columns means the corresponding product term variable is not needed. 0- A "1" appearing in an output column means the product term is needed 1- in that function's output expression, and a "0" means that product term -1-1 is not needed. --.e End of file marker This output file would give the Boolean expressions: F1 = AB'CD' + B'C'D' + BD + A'B and F2 = AB'CD' + A'C'D + A'BC. a) Use espresso to minimize the equations for the seven segment decoder. A partial input file is shown to the right; complete and enter this file for use with expresso (note that all don't cares are used). b) Run espresso, print a copy of the output file and attach it to this report. Write the Boolean equations for all seven outputs on the printed output. c) Compare the product terms that were obtained from the SwitchMin program with the product terms obtained from espresso. Find the gate/input tally for each output function and for the entire system that was produced by each tool. With tool generated the simpler result? Part 5. (25%) VHDL Partial Espresso input file for a Seven Segment Decoder.i 4.o 7.ilb B3 B2 B1 B0.ob A B C D E F G.p 16 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 [ missing statements here] - - - - - - - - - - - - - -.e As a final exercise, we will use the VHDL tool in the Xilinx environment to minimize the same system. Any truth table can easily be entered into a VHDL program by using a "conditional assignment" statement as shown below. The conditional assignment uses a when clause to associate a group of outputs with a group of inputs. Notice that the four output function values appear on the left of the when clause, and the two input values appear on the right. With input_vars select output_vars <= "" when "", "" when "", "" when "", "" when others; A B F1 F2 F3 F4 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0

EE 214 Lab 7 Computer-Based Minimization Tools Page 8/8 In this statement, the variable name and output name are both vectors, meaning they represent more than a single input or output. The statement functions by comparing the value of input_vars to the value shown in the when clause: the output variable output_vars gets assigned the binary values shown in quotes when the input_vars is equal to the value in the when clause. Thus, if input_vars is "", then output_vars gets assigned "". Note the last line uses a "when others" clause instead of "when ". For reasons that will be explained later, it is necessary to include a "when others" clause as the last selection of a conditional assignment statement. A conditional assignment statement can be used to implement any truth table by listing the function inputs on the right of the when clause, and the associated outputs on the left of the when clause. In the example below, VHDL code for the seven segment decoder has been partially supplied. Note the syntax for declaring a vector in lines 5 and 6 below. A vector is simply a logical grouping of signals. In this case, the four inputs (representing a binary number) have been grouped into a vector called BIN, and the seven segment outputs have been grouped into a vector called SEG_OUT. Note also that the last line of the select statement contains a "when others" clause. This catch-all clause can be used to assign the value "1" to the seven segment decoder outputs whenever an unspecified input condition occurs. In this case, this clause can be used to assign an output value when the binary numbers through are present on the inputs. VHDL Conditional Assignment Example for a Seven Segment Decoder 1. library ieee; 2. use ieee.std_logic_64.all; 3. 4. entity seven_seg_dec is 5. port (BIN: in STD_LOGIC_VECTOR(3 downto 0); 6. SEG_OUT: out STD_LOGIC_VECTOR (6 downto 0)); 7. end seven_seg_dec; 8. 9. architecture behavioral of seven_seg_dec is. begin. with BIN select 12. SEG_OUT <= "0" when "", 13. "1" when "", 14.. 15.. 16.. 17. "1" when others; 18. end behavioral; a) Type in VHDL code for the seven segment decoder b) Simulate the code, and verify that the output is correct c) Turn in a hard-copy of your VHDL code. Coding behaviors in VHDL has several powerful advantages. The interface is clear and straightforward, the form and syntax are industry standard and therefore portable, and most importantly, the circuit can be directly implemented in hardware using existing computer tools. But that's another lab!