MODULE 5 - COMBINATIONAL LOGIC

Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5 - COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific output. A truth table is used to show the input variables and all possible combinations of ones and zeros that can occur as a result of the possible input combinations. For each combination of input variable ones and zeros that results in a "1" output, a Boolean algebra expression of that combination is generated. Each of these terms are logically Ored together so that the term will produce a "1" output. CONCEPT 5.1: AND, OR, INVERT Combinational Logic For AND-OR logic, each individual term in a truth table that generates a "1" output is ANDed together. Inverters, or NOT gates, are used to turn each "0" input variable into a "1", so the final group can be input into an AND gate in order to generate the desired "1" output. As an example, consider a 3 variable truth table with a "1" output at the input variable location 010. The two zeros on either end must be converted to "1"s before this number can be input into an AND gate, resulting in a "1" output. If the input variables are labeled A, B & C, and the output X; the resulting Boolean Algebra expression would be: X = A B C The lines over the top of the A and C terms indicate that they must go through an Inverter, or NOT gate, before X will be true, or "1". If other terms exist where X will output a "1", they will be described in the same way, and logically ORed together to produce the final logic design. Example 5.1: A Three Variable Truth Table & Resulting Logic Design

Introduction to Digital Electronics Module 5: Combinational Logic 2 For the resulting three combinations of input variables that result in a "1" output, an AND OR digital logic circuit can be designed that will produce a "1" output if any of the three combinations come up: CONCEPT 5.2: The Result of Increasing the Number of Variables If you have three input variables, you will have eight possible combinations. Four input variables will give you sixteen possible combinations; five will yield thirty two, and so on. Increasing the number of variables increases the number of possible outcomes, but it also increases the complexity of the design. When designing using classical logic gates, you will want to make your design as simple as possible. You will apply some of the simplification techniques from Module 4 and do everything possible to reduce the number of gates. If a design must use more than three or four input variables, the designer must consider using computer aided design tools and programmable logic devices to realize the design. We will study these devices and design techniques in some depth in Module 7.

Introduction to Digital Electronics Module 5: Combinational Logic 3 CONCEPT 5.3: Simplifying Three and Four Variable Designs Three and four variable designs can be simplified using three and four variable K maps. Three and four variable truth tables can be simplified by mapping the truth table outputs onto a K map, and simplifying the Boolean algebra by grouping adjacent states, and eliminating redundant variables. The techniques are described in Module 4, but will be reviewed in this section. Consider the design from Concept 5.1. The resulting digital design required three, 3 input AND gates and two, 2 input OR gates. This expression can be simplified down to two, 2 input AND gates, and a single 2 input OR gate. The resulting logic will generate the same truth table outputs as the more complex version of the design, so it represents a significant savings in both work and the number of required gates.

Introduction to Digital Electronics Module 5: Combinational Logic 4 For a four variable design, consider the truth table below: To implement this design would require eight 4 input AND gates, and seven 2 input OR gates. If this were to be burned into a programmable logic array, there would be no reason to simplify unless the array had fewer gates than needed.

Introduction to Digital Electronics Module 5: Combinational Logic 5 CONCEPT 5.4: Truth Table and K Map Circuit Design Outline When designing a digital circuit that must be simplified, and which contains six variables or less, a truth table and a K map are powerful tools. The truth table catalogs all of the combinations of input variables with all allowed outcomes. For each 1 output, the corresponding combination of input variables becomes one term of the Boolean algebra expression that defines the design. The 1 and 0 outputs are mapped onto a K map corresponding to their cell locations or input binary combinations. By grouping these adjacent 1 s in groups of 2, 4, 8, or 16, the redundant variables cancel, leaving only the simplified combinations, which will produce the same output as the truth table. 1. On the right side of the truth table, the outputs are listed and receive a "1" for the combinations where they are active or true, and a "0" for the combinations where they are off, inactive or false. This allows you to specify when a machine turns "on" or "off", and for what combinations of input variables. 2. After you have specified the states of the output variables as a function of the input variable combinations, you can extract the active or control terms, or combinations of input states from your truth table. 3. Extract the Boolean algebra expression of the input variables for the corresponding "1" outputs, or true states. Convert these terms into their equivalent combinational logic circuits of either AND OR logic, NAND logic or NOR logic gates. All three different types of logic circuits can be used to produce the same results. The combinational logic circuit designed directly from the truth table may not be the simplest design, but the truth table is always the starting point for digital design. 4. Simplify the circuit by mapping the 1 s in a K map and canceling out redundant terms. The "1"s map directly into the K map cells that correspond to that combination of input variables.

Introduction to Digital Electronics Module 5: Combinational Logic 6 CONCEPT 5.5: K Mapping Boolean Algebra Expressions Directly A K map can be used to directly simplify a complex Boolean algebra expression, and to convert it directly to SOP form. The simple rule is to put a 1 on the K map everywhere a term would be true. After each term of the expression has been mapped, the 1 s can be simplified in exactly the same way as the truth table entries. Prior to mapping the Boolean algebra expressions directly onto a K map, it may be necessary to use Boolean algebra and/or DeMorgan s Theorem to reorganized the expression and to isolate terms into an SOP form. After you have manipulated the expression and changed it into a series of terms separated by + (OR) signs, you are ready to map the expression. Once the expression has been mapped onto the K map, it can be simplified by grouping the 1 s and canceling out the redundant terms.

Introduction to Digital Electronics Module 5: Combinational Logic 7 CONCEPT 5.6: Analyzing Combinational Logic Circuits A combinational logic circuit can be analyzed and tested for the simplest form, using a K map. Starting with the input variables, let each gate operate on the variables. At the output of each gate, write the resulting output expression. This expression is put into the next gate, and so on. The best way to understand combinational logic circuit analysis is to do it. We will analyze the following simple circuit: To know if this is the simplest design, the next step is to map the unsimplified expression, and use the K map to simplify it.

Introduction to Digital Electronics Module 5: Combinational Logic 8 CONCEPT 5.7: Shorthand SOP and POS Form The shorthand form of SOP and POS equations require only the cell number to be presented, and not the individual terms as in a Boolean algebra expression. As an example, consider the 4 variable truth table shown below. The truth table and the Boolean algebra form are both shown: Notice that the truth table has positive results at cells 1,3,4,5,7,10,11, and 13. The shorthand uses the Greek letter capital sigma (S), to indicate SOP, and the final shorthand form is: X(ABCD) = S(1,3,4,5,7,10,11,13) The POS form of the equation is derived by grouping those cells that are 0"s. They are 0,2,6,8,9,14, and 15. The POS form of the equation uses the capital Greek letter pi (P). The resulting POS shorthand equation is: X(A B C D) = P(0,2,6,8,9,14,15)