VCU110 GT IBERT Design Creation

VCU110 GT IBERT Design Creation June 2016 XTP374

Revision History Date Version Description 06/08/16 4.0 Updated for 2016.2. 04/13/16 3.0 Updated for 2016.1. Updated for Production Kit. 02/03/16 2.1 Updated HMC Software. 01/28/16 2.0 Updated for 2015.4 for ES3 Silicon. AR65643 fixed. 10/06/15 1.0 Initial version. Added AR61285 and AR65643. Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

Note: This presentation applies to the VCU110 VCU110 IBERT Overview Xilinx VCU110 Board VCU110 Software Install and Board Setup Testing IBERT Designs Testing IBERT GTH FMC and HMC Testing IBERT GTY CFP4 and BullsEye Testing IBERT GTY ExaMax Testing IBERT GTY Interlaken Create IBERT Design for Banks GTY Create IBERT Design for Banks GTH Add HMC Control logic to IBERT GTH design References

VCU110 IBERT Overview Description The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a pattern generation and verification design to exercise the UltraScale Virtex GTH and GTY transceivers. A graphical user interface is provided through the Vivado Hardware Manager. Reference Design IP LogiCORE UltraScale IBERT GTY Example Designs LogiCORE UltraScale IBERT GTH Example Designs Testing This tutorial builds a bitstream for all GTHs and another bitstream for all GTYs on the VCU110 GTH Testing: FMC and Hybrid Memory Cube (HMC) GTY Testing: ExaMax/Interlaken, CFP4, and BullsEye cables

Xilinx VCU110 Board

Note: The IBERT tests require the clock setup from XTP380 VCU110 Software Install and Board Setup Complete setup steps in XTP380 VCU110 Software Install and Board Setup: Software Requirements VCU110 Board Setup UART Driver Install Clock setup

VCU110 Setup Open the RDF0336 - VCU110 GT IBERT Design Files (2016.2 C) ZIP file, and extract the ready_for_download files to your C:\ drive:

VCU110 Setup From RDF0336 ZIP file, extract the hmc_files files to your C:\ drive:

Testing IBERT GTH

Testing IBERT GTH Open a Vivado Tcl Shell: Start All Programs Xilinx Design Tools Vivado 2016.2 Vivado 2016.2 Tcl Shell

Testing IBERT GTH In the Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_gth.tcl

Testing IBERT GTH The HMC initialization routine can be seen in the UART window

Testing IBERT GTH If needed, set Vivado GUI layout to Serial I/O Analyzer

Testing IBERT GTH FMC Line Rate is 16.3 Gbps

Testing IBERT GTH HMC Line Rate is 15 Gbps; close Vivado GUI after finished viewing

Testing IBERT GTY

Testing IBERT GTY This test requires customer supplied BullsEye cables In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_gty.tcl

Testing IBERT GTY BullsEye line rate is 28 Gbps; CFP4 line rate is 25 Gbps Close Vivado GUI and Tcl Shell after finished viewing

Testing IBERT ExaMax

Testing IBERT ExaMax In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_examax.tcl

Testing IBERT ExaMax ExaMax line rate is 28 Gbps Close Vivado GUI and Tcl Shell after finished viewing

Testing IBERT Interlaken

Testing IBERT Interlaken In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_interlaken.tcl

Testing IBERT Interlaken Interlaken line rate is 28 Gbps Close Vivado GUI and Tcl Shell after finished viewing

Create IBERT Design for GTYs

Create IBERT Design for GTYs Open Vivado Start All Programs Xilinx Design Tools Vivado 2016.2 Vivado Select Create New Project

Create IBERT Design for GTYs Click Next

Note: Vivado generally requires forward slashes in paths Create IBERT Design for GTYs Set the Project name and location to ibert_bank_gty and C:/vcu110_ibert; check Create project subdirectory

Create IBERT Design for GTYs Select RTL Project Select Do not specify sources at this time

Create IBERT Design for GTYs Under Boards, select the VCU110 Board

Create IBERT Design for GTYs Click Finish

Create IBERT Design for GTYs Click on the IP Catalog

Create IBERT Design for GTYs Select IBERT UltraScale GTY, v1.2 under Debug & Verification

Create IBERT Design for GTYs Right click on IBERT UltraScale GTY and select Customize IP

Create IBERT Design for GTYs Set the Component name: ibert_bank_gty Under the Protocol Definition tab Select 2 Protocols

Create IBERT Design for GTYs Under the Protocol Definition tab Protocol Custom 1: LineRate: 28.0, Refclk: 175 Quad Count: 9 Protocol Custom 2: LineRate: 25.0, Refclk: 156.25 Quad Count: 4 Select the Protocol Selection tab

Create IBERT Design for GTYs Set Quads 122, 125, 127, and 128 to Custom 2 / 25.0 Gbps

Create IBERT Design for GTYs Set the remaining Quads to Custom 1 / 28.0 Gbps

Create IBERT Design for GTYs Under the Clock Settings tab, set the System Clock: DIFF SSTL12, P Package Pin: J24, Frequency: 300 Deselect Enable DIFF Term

Create IBERT Design for GTYs Review the summary and click OK

Note: This step will take about 40 minutes Create IBERT Design for GTYs Click Generate

Create IBERT Design for GTYs The Generated IBERT IP appears in Design Sources Wait until checkmark appears on ibert_bank_gty_synth_1

Compile Example Design Right click on ibert_bank_gty and select Open IP Example Design

Compile Example Design Set the location to C:/vcu110_ibert/ibert_bank_gty and click OK

Note: This step will take about 140 minutes Compile Example Design A new project is created under <design path>/ Click Generate Bitstream

Note: *Will take 15 minutes to open; this step can be skipped Compile Example Design Open and view the Implemented Design* Click Open Hardware Manager

Run IBERT Example Design Click Open target and select Auto Connect

Run IBERT Example Design Select Program device xcvu190_0

Run IBERT Example Design The newly created bitstream and LTX files are set to the default Click Program

Run IBERT Example Design Click on Create links

Run IBERT Example Design Add links from Quad_122 through Quad_128

Run IBERT Example Design Skip Quad_124 and Quad_126, if BullsEye cables are not available

Run IBERT Example Design Click OK

Run IBERT Example Design The GTY links appear under the Serial I/O Links tab

Run IBERT Example Design Select the TX and RX Patterns and set to PRBS 31-bit

Run IBERT Example Design Click the BERT Reset button for Link Group 0 to reset all links

Run IBERT Example Design All the links are showing no errors

Run IBERT Example Design The Tcl commands can be captured into a TCL file for later playback

Create IBERT Design for Banks GTH

Create IBERT Design for Banks GTH Open Vivado Start All Programs Xilinx Design Tools Vivado 2016.2 Vivado Select Create New Project

Create IBERT Design for Banks GTH Click Next

Note: Vivado generally requires forward slashes in paths Create IBERT Design for Banks GTH Set the Project name and location to ibert_bank_gth and C:/vcu110_ibert; check Create project subdirectory

Create IBERT Design for Banks GTH Select RTL Project Select Do not specify sources at this time

Create IBERT Design for Banks GTH Under Boards, select the VCU110 Board

Create IBERT Design for Banks GTH Click Finish

Create IBERT Design for Banks GTH Click on IP Catalog

Create IBERT Design for Banks GTH Select IBERT UltraScale GTH, v1.3 under Debug & Verification

Create IBERT Design for Banks GTH Right click on IBERT UltraScale GTH and select Customize IP

Create IBERT Design for Banks GTH Set the Component name: ibert_bank_gth Under the Protocol Definition tab Select 3 Protocols

Create IBERT Design for Banks GTH Under the Protocol Definition tab Protocol Custom 1: LineRate: 16.3, Refclk: 163, Quad Count: 4 Protocol Custom 1: LineRate: 15, Refclk: 187.5, Quad Count: 8 Protocol Custom 1: LineRate: 5, Refclk: 100, Quad Count: 1

Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_220, QUAD_221, QUAD_224, and QUAD_224 to Custom 1 / 16.3 Gbps Set QUAD_220 Refclk to MGTREFCLK0 221

Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_225 through QUAD_232 to Custom 2 / 15 Gbps Set QUAD_225-QUAD_228 Refclk to MGTREFCLK0 226 Set QUAD_229-QUAD_232 Refclk to MGTREFCLK0 230

Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_233 to Custom 3 / 5 Gbps Set QUAD_233 Refclk to MGTREFCLK0 233

Create IBERT Design for Banks GTH Under the Clock Settings tab, set the System Clock: DIFF SSTL12, P Package Pin: J24, Frequency: 300 Deselect Enable DIFF Term

Create IBERT Design for Banks GTH Review the summary and click OK

Note: This step will take about an hour Create IBERT Design for Banks GTH Click Generate

Create IBERT Design for Banks GTH The Generated IBERT IP appears in Design Sources Wait until checkmark appears on ibert_bank_gth_synth_1

Compile Example Design Right click on ibert_bank_gth and select Open IP Example Design

Compile Example Design Set the location to C:/vcu110_ibert/ibert_bank_gth and click OK

Note: The original project window can be closed Compile Example Design A new project is created under <design path>/

Compile Example Design In the Tcl console, type: source C:/vcu110_ibert/hmc_files/system.tcl

Compile Example Design HMC control Block design appears Click Add Sources

Modifications to Example Design Select Add or create constraints and click Next

Modifications to Example Design Select the example_ibert_bank_gth.xdc file and delete it from the Add Sources dialog This file is already in the project

Modifications to Example Design Add the system.xdc file from C:\vcu110_ibert\hmc_files Make sure Copy constraint files into project is checked Click Finish

Compile Example Design Right click on example_ibert_bank_gth.v and remove it from the project

Compile Example Design Select Ignore and click OK

Compile Example Design Click Add Sources again

Modifications to Example Design Select Add or create design sources and click Next

Modifications to Example Design Add example_ibert_bank_gth.v from C:\vcu110_ibert\hmc_files Make sure Copy constraint files into project is checked Click Finish

Modifications to Example Design Click Generate Block Design

Modifications to Example Design Click Generate

Modifications to Example Design Select File Export Export Hardware Deselect Include bitstream then click OK

Modifications to Example Design Select File Launch SDK Click OK

Modifications to Example Design From the New pulldown, select Board Support Package

Modifications to Example Design Click Finish

Modifications to Example Design Click OK

Modifications to Example Design From the pulldown, select Application Project

Modifications to Example Design Name the project hmc_loopback For the Board Support Package, select Use existing Click Next

Modifications to Example Design Select Empty Application Click Finish

Modifications to Example Design Right click on hmc_loopback, and select Import

Modifications to Example Design Expand General, select File System, and click Next

Modifications to Example Design Select the C:\vcu110_ibert\hmc_files directory Expand hmc_files and check the src folder Click Finish

Modifications to Example Design Expand the hmc_loopback and src folders; the five.c and.h files should be present as shown here

Modifications to Example Design Right click on hmc_loopback and select Generate Linker Script

Modifications to Example Design Set the stack and heap to 16384 (16 KB), then click Generate

Modifications to Example Design After software recompiles, close SDK and return to Vivado

Modifications to Example Design Select Add Sources

Modifications to Example Design Select Add or Create Design Sources

Modifications to Example Design Add hmc_loopback.elf from the SDK tree Make sure Copy sources into project is deselected Click Finish

Modifications to Example Design Right-click on the ELF file and select Associate ELF Files

Modifications to Example Design Click the button to the right; select the hmc_loopback.elf then click OK twice

Note: This step will take about 120 minutes Compile Example Design Click Generate Bitstream

Note: *Will take 13 minutes to open; this step can be skipped Compile Example Design Open and view the Implemented Design* Click Open Hardware Manager

Run IBERT Example Design Click Open target and select Auto Connect

Run IBERT Example Design Select Program device xcvu190_0

Run IBERT Example Design The newly created bitstream and LTX files are set to the default Click Program

Run IBERT Example Design The HMC initialization routine can be seen in the UART window

Run IBERT Example Design As per AR61285, if a QPLL is not locking, at the Tcl Console, type: source C:/vcu110_ibert/ready_for_download/reset.tcl

Run IBERT Example Design Quads are now locked Click Create links

Run IBERT Example Design Add the first forty-eight links

Run IBERT Example Design The GTH links appear under the Serial I/O Links tab

Run IBERT Example Design Set the TX and RX Patterns to PRBS 31-bit

Run IBERT Example Design Now all links are set to PRBS 31-bit Click the BERT Reset button to reset all links

Note: If needed, tune FMC TX Pre-Cursor to 3.41 db Run IBERT Example Design All the links are showing no errors

Run IBERT Example Design The Tcl commands can be captured into a TCL file for later playback

References

References IBERT IP LogiCORE IP Integrated Bit Error Ratio Tester for UltraScale GTY PG196 http://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/ v1_2/pg196-ibert-ultrascale-gty.pdf LogiCORE IP Integrated Bit Error Ratio Tester for UltraScale GTH PG173 http://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gth/ v1_3/pg173-ibert-ultrascale-gth.pdf Vivado Programming and Debugging Vivado Design Suite Programming and Debugging User Guide UG908 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ ug908-vivado-programming-debugging.pdf

Documentation

Documentation Virtex UltraScale Virtex UltraScale FPGA Family http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html VCU110 Documentation Virtex UltraScale FPGA VCU110 Development Kit http://www.xilinx.com/products/boards-and-kits/dk-u1-vcu110-g.html VCU110 Board User Guide UG1073 http://www.xilinx.com/support/documentation/boards_and_kits/vcu110/ ug1073-vcu110-eval-bd.pdf VCU110 Known Issues Master Answer Record http://www.xilinx.com/support/answers/62604.html