ESD7002, SZESD7002. Transient Voltage Suppressors. Low Capacitance ESD Protection Diode for High Speed Data Line

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ESD72, SZESD72 Transient Voltage Suppressors Low Capacitance ESD Protection Diode for High Speed Data Line The ESD72 transient voltage suppressor is designed to protect high speed data lines from ESD. Ultra low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3. and HDMI. Features Low Capacitance (.3 pf Typical, I/O to GND) Diode capacitance matching Protection for the Following IEC Standards: IEC 61 4 2 (Level 4) Low ESD Clamping Voltage SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q11 Qualified and PPAP Capable These Devices are Pb Free and are RoHS Compliant Typical Applications USB2./3. LVDS HDMI High Speed Differential Pairs MAXIMUM RATINGS (T J = 25 C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range T J 55 to +125 C Storage Temperature Range T stg 55 to +15 C Lead Solder Temperature Maximum (1 Seconds) T L 26 C SC 7 CASE 419 STYLE 4 MARKING DIAGRAM 72 = Specific Device Code M = Date Code = Pb Free Package (*Note: Microdot may be in either location) PIN CONFIGURATION AND SCHEMATIC Pin 1 Pin 2 = Pin 3 72 M ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1 IEC 61 4 2 Contact (ESD) IEC 61 4 2 Air (ESD) ESD ESD ±8 ±15 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. kv kv Semiconductor Components Industries, LLC, 214 January, 214 Rev. 3 1 Publication Order Number: ESD72/D

ESD72, SZESD72 ELECTRICAL CHARACTERISTICS (T A = 25 C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V RWM I/O Pin to GND 5 16 V Breakdown Voltage V BR I T = 1 ma, I/O Pin to GND 16.5 V Reverse Leakage Current Clamping Voltage (Note 1) Clamping Voltage TLP (Note 2) Junction Capacitance Match I R V RWM = 5 V, I/O Pin to GND 1 A V C IEC61 4 2, ±8 kv Contact See Figures 3 and 4 V C C J I PP = 8 A I PP = 16 A I PP = 8 A I PP = 16 A VR = V, f = 1 MHz between I/O1 to GND and I/O 2 to GND 31.2 33.9 5.5 1.8 V 5 1 % Junction Capacitance C J VR = V, f = 1 MHz between I/O Pins.2.4 pf Junction Capacitance C J VR = V, f = 1 MHz between I/O Pins and GND.3.5 pf 3dB Bandwidth f BW R L = 5 5 GHz 1. For test procedure see Figures 5 and 6 and application note AND837/D. 2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 5, t p = 1 ns, t r = 4 ns, averaging window; t 1 = 3 ns to t 2 = 6 ns. CURRENT (A) 1E 2 1E 3 1E 4 1E 5 1E 6 1E 7 1E 8 1E 9 1E 1 1E 11 1E 12 1E 13 2 4 6 8 1 12 14 16 18 2 22 24 Figure 1. Typical IV Characteristic Curve CAPACITANCE (pf) 1..9.8.7.6.5.4.3.2.1 2 4 6 8 1 12 14 VBias (V) Figure 2. Typical CV Characteristic Curve 15 14 13 12 11 1 9 8 7 6 5 4 3 2 1 1 5 5 1 15 2 25 3 35 4 TIME (ns) Figure 3. IEC61 4 2 +8 kv Contact ESD Clamping Voltage 1 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 2 2 4 6 8 1 12 14 16 18 2 TIME (ns) Figure 4. IEC61 4 2 8 kv Contact ESD Clamping Voltage 2

ESD72, SZESD72 IEC 61 4 2 Spec. Level Test Voltage (kv) First Peak Current (A) Current at 3 ns (A) Current at 6 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 3 16 8 IEC61 4 2 Waveform I peak 1% 9% I @ 3 ns I @ 6 ns 1% t P =.7 ns to 1 ns ESD Gun TVS Figure 5. IEC61 4 2 Spec Oscilloscope 5 Cable 5 Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND838/D Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61 4 2 waveform. Since the IEC61 4 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND837/D. 3

ESD72, SZESD72 18 16 14 18 16 14 CURRENT (A) 12 1 8 6 CURRENT (A) 12 1 8 6 4 2 5 1 15 2 25 3 35 4 Figure 7. Positive TLP IV Curve 4 2 2 4 6 8 1 12 14 Figure 8. Negative TLP IV Curve NOTE: TLP parameter: Z = 5, t p = 1 ns, t r = 3 ps, averaging window: t 1 = 3 ns to t 2 = 6 ns. Transmission Line Pulse (TLP) Measurement Transmission Line Pulse (TLP) provides current versus voltage (I V) curves in which each data point is obtained from a 1 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I V curves of ESD protection devices accurately demonstrate the product s ESD capability because the 1s of amps current levels and under 1 ns time scale match those of an ESD event. This is illustrated in Figure 1 where an 8 kv IEC 61 4 2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 5 Coax Cable L 1 M V C S Attenuator Oscilloscope Figure 9. Simplified Schematic of a Typical TLP System I M 5 Coax Cable V M DUT Figure 1. Comparison Between 8 kv IEC 61 4 2 and 8 A and 16 A TLP Waveforms 4

ESD72, SZESD72 Without ESD72 With ESD72 Figure 11. USB3. Eye Diagram with and without ESD72 at 5 Gb/s S21 (db) 1.5.5 1 1.5 2 2.5 3 3.5 4 1.E+6 1.E+7 1.E+8 1.E+9 FREQUENCY (Hz) Figure 12. Typical Insertion Loss ORDERING INFORMATION Device Package Shipping ESD72WTT1G SZESD72WTT1G* SC 7 (Pb Free) SC 7 (Pb Free) 3 / Tape & Reel 3 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. *SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q1 Qualified and PPAP Capable. 5

ESD72, SZESD72 PACKAGE DIMENSIONS SC 7 (SOT 323) CASE 419 4 ISSUE N D e1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH..5 (.2) 3 H E 1 2 e A1 E A b A2 L c MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A.8.9 1..32.35.4 A1..5.1..2.4 A2.7 REF.28 REF b.3.35.4.12.14.16 c.1.18.25.4.7.1 D 1.8 2.1 2.2.71.83.87 E 1.15 1.24 1.35.45.49.53 e 1.2 1.3 1.4.47.51.55 e1.65 BSC.26 BSC L.2.38.56.8.15.22 H E 2. 2.1 2.4.79.83.95 STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE SOLDERING FOOTPRINT*.65.25.65.25.9.35.7.28 1.9.75 SCALE 1:1 mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: 33 675 2175 or 8 344 386 Toll Free USA/Canada Fax: 33 675 2176 or 8 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 79 291 Japan Customer Focus Center Phone: 81 3 5817 15 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ESD72/D