Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc..

Introduction of IEEE 1588 Basics of Precision Time Protocol Basics of Synchronization Hardware: IEEE 1588 hardware assist block Timer Time-stamping Interrupts, Registers and signals Software: Device driver and application Test setup and results Usage Summary References 2

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc.. 3

IEEE 1588 is the standard for a precision clock synchronization protocol for networked measurement and control The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system Intended for local area networks Targeted accuracy of microsecond to sub-microsecond with easy configuration and fast convergence between components IEEE 1588-2002 (Version 1) approved September 2002 and published November 2002 IEEE 1588-2008 (Version 2) approved March 2008 and published August 2008 Available from the IEEE 1588 web site (http://www.nist.gov/el/isd/ieee/ieee1588.cfm) 4

Target Uses NTP GPS TTP IEEE 1588 Autonomous systems dispersed over a wide area. Time information passed via messages on the Internet. Autonomous systems dispersed over a wide area. Time information passed via satellite. Tightly integrated, closed systems usually connected via a bus or specialized TDMA network Groups of relatively stable components, locally networked (a few subnets), cooperating on a set of well defined tasks Target Accuracy Synchronization Resolution Time under 1ms possible, 1-10ms typical in LAN, <100ms over the Internet Minutes to hours Sub microsecond Sub microsecond Sub microsecond (± 50ns typ) < Minute Resource Requirements Moderate network and compute footprint Moderate compute footprint Moderate compute footprint Small network and compute footprint Latency Correction Yes Yes Configured Yes Update Interval Variable, but normally seconds Approximately every second Milliseconds Approximately every 2 seconds Hardware Required No Yes Yes Yes, to achieve greatest accuracy 5

100 102 104 106 108 110 Estimated Send Time (100) Precise Send Time (101) B Precise Receive Time (108) Master Clock PTP Appl. G/MII t 0 t 3 t 2 Slave Clock G/MII PTP Appl. t 1 Offset Computation A Precise Receive Time (106) Precise Send Time (111) 104 106 108 110 112 114 112 Key Equations: A = t 1 t 0 = Delay + Offset B = t 3 - t 2 = Delay Offset Delay = (A+B) / 2 Offset = (A-B) / 2 Example: A = 106 101 = 5 B = 108 111 = -3 Delay = (5-3) / 2 = 1 Offset = (5+3) / 2 = 4 7 116 UDP port 319: Sync and Delay_Req UDP port 320: Follow_up, Delay_Resp, and Mgmt

SYNC Messages Master sends an estimate of the sending time When received by a slave clock, the receipt time is noted FOLLOW_UP messages: Always associated with the preceding Sync message Contain the precise sending time of SYNC message measured close to the physical layer of the network DELAY_REQ messages: Issued by clock nodes in the Slave state When received by the master clock the receipt time is noted DELAY_RESP messages: Always associated with a preceding Delay_Req message from a specific slave clock Contain the receipt time of the associated Delay_Req message 8

Master Clock Slave Clock Milliseconds of delay and variation introduced by protocol stack PTP UDP IP MAC PTP UDP IP MAC Milliseconds of delay and variation introduced by protocol stack PHY Network PHY IEEE 1588 PTP Code Network protocol stack & OS Hardware time-stamping removes protocol stack delay Timestamp generation / message detection PHY MII / GMII 9

Master Clock Switch / Router with Boundary Clock (Slave) (Master) Slave Clock PTP PTP PTP PTP UDP UDP UDP UDP IP IP IP IP MAC MAC MAC MAC PHY Network 1 PHY PHY Network 2 PHY Synchronization across multiple network/subnets 10

Node A Node B : : : : Clocks advancing at the same rate, but are 8 minutes apart Clocks in frequency alignment, with constant offset * *also called Syntonous clocks 12

Node A Node B : : : : Clocks start at the same time, but are advancing at different rates Clocks not in frequency alignment, with zero initial offset 13

Node A Node B : : : : Clocks advancing at the same rate, with the same initial offset Clocks in frequency alignment, with zero offset (same time) 14

Timer Logic 15

Software Time-Stamp External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter R_CNTH/L etsec Tx Clock + + Tip R_CNTL/H are modified when difference between master and slave is huge 32-bit Addend Tip ADDEND is modified to fine tune the slave clock TCLK_PERIOD 16

Four choices of input clock Addend and accumulator provides a digital fractional divider Provision for bypassing the divider logic ADDEND = 2 32 FreqDivRatio If input clock = 150MHz & desired nominal clock = 100MHz ADDEND = 2 32 (150/100) = 0xAAAA_AAAA External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter R_CNTH/L etsec Tx Clock + + 32-bit Addend TCLK_PERIOD 17

The 64-bit counter increments by TCLK_PERIOD on every pulse of nominal clock To represent time in nanoseconds, TCLK_PERIOD should be equal to reciprocal of frequency of nominal clock It is recommended to have TCLK_PERIOD as integral factor of 10 9 Example: Few integral factors of 10 9 : 2, 4, 8, 10, 16, 20 For Input clock = 333MHz, recommended choices for nominal clock are 100MHz, 125MHz, 200MHz and 250MHz External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter R_CNTH/L etsec Tx Clock + + TCLK_PERIOD 32-bit Addend 18

Example assumes the accumulator overflows after 9, therefore ADDEND= 9 / (150/100) = 6 The resultant clock may not have 50% duty cycle or uniform period Input Clock = 150MHz Addend = 9 / 1.5 = 6 68 24 0 + Carry after 9 Accumulator 6 Nominal Clock = 100MHz 19

Systems which require to synchronize an external clock may choose to bypass internal fine-tuning The counter runs on the input clock SPI or IIC can be used to fine-tune VCXO Tip External clock needs to be tuned VCXO DAC External Clock Ref Platform Clock Ref RTC Clock etsec Tx Clock Bypass Enable Accum + Addend Carry Nominal Clock Counter R_CNTH/L + TCLK_PERIOD IIC/SPI 20

Prescaler GCLK TCLK_PERIOD 32-bit FIPER PULSE_OUTn 64 bit ALARM ALARM_OUTn External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter R_CNTH/L etsec Tx Clock + + 32-bit Addend TCLK_PERIOD 21

ALARM_OUT is generated when counter is equal to or greater than ALARM can be used to trigger the periodic pulse generator Prescaler TCLK_PERIOD GCLK With FIPER as the initial value, a downcounter decrements by TCLK_PERIOD on every pulse of nominal clock 32-bit FIPER PULSE_OUTn A pulse is generated when the down counter reaches zero or less than TCLK_PERIOD Generates periodic pulse with a width of one period of the pre-scaled output clock Down counter is reloaded; the process repeats Nominal Clock 64 bit ALARM 64-bit Counter R_CNTH/L + ALARM_OUTn GCLK outputs pre-scaled output clock TCLK_PERIOD 22

FIPER should be programmed to an integer multiple of TCLK_PERIOD value to ensure a period pulse being generated correctly To generate 1PPS signal: FIPER = <10 9 nanoseconds> / TCLK_PERIOD TCLK_PERIOD 32-bit FIPER 64 bit ALARM PULSE_OUTn ALARM_OUTn To align PPS signal with R_CNT: Program ALARM to a value which is a whole number of seconds, and greater than the present R_CNT ALARM = (floor{(r_cnt/10 9 ) + n})*10 9 Example: For R_CNT = 5.3s and n=2, ALARM = 7s Set R_CTRL[FS] to trigger FIPER by ALARM Nominal Clock 64-bit Counter R_CNTH/L + TCLK_PERIOD Tip Only ALARM1 can trigger FIPER1. 23

Should user need to change the value of R_CNT, the following procedure should be followed to realign the PPS signal: Calculate the new value of ALARM Write new values to R_CNTL/H Write calculated values to ALARM1L/H Rewrite FIPER to reset the down counter Set R_CTRL[FS] Nominal Clock TCLK_PERIOD 32-bit FIPER 64 -bit ALARM 64-bit Counter R_CNTH/L + PULSE_OUTn ALARM_OUTn TCLK_PERIOD 24

R_CNT_L should be read first to get correct 64-bit R_CNT_H/L counter values Reads from the R_CNT_L register copies the entire 64-bit clock time into shadow registers R_CNT_L should be written first Contents of the shadow registers are copied into the R_CNT_L and R_CNT_H registers following a write into the R_CNT_H register Writing the R_ALARMn_L register deactivates the alarm event Writing the R_ALARMn_L followed by the R_ALARMn_H register rearms the alarm function with the new compare value Writing new value to FIPER register resets the down counter used in PULSE_OUT generation ATTENTION Above recommendations should be strictly followed. Any violation may result in unpredictable results. 25

There are three different time-stamp capture triggers Reception of a packet Transmission of a packet On the positive or negative edge of the external trigger 27

For etsec: On detection of SFD, the value of R_CNT_H/L is copied to R_RXTS_H/L if RCTRL[TS] in etsec is set to 1 In addition, the time-stamp is inserted into the packet data buffer as padding alignment bytes if: R_CTRL[RTPE] is set to 1 AND RCTRL[PAL] (receive pad alignment length) is set to a value greater than or equal to 8 etsec indicates reception of PTP packet to CPU CPU reads time-stamp from RxBuffer or R_RXTS_H/L 28

For dtsec: When enabled by setting RCTRL[RTSE] in dtsec, every incoming packet will be accompanied with an 8-byte time-stamp The BMI will extract the timestamp and copy it to the timestamp field within the internal buffer The whole frame together with timestamp is copied into external buffers and FD is enqueued to indicate reception of PTP packet to CPU CPU reads time-stamp from Frame Descriptor 29

etsec supports a two-step clock The time-stamp of frame being transmitted is stored in registers or frame control buffer The follow-up packet carries the actual time-stamp of previous packet etsec supports selective time-stamping for Tx packets using TxFCB[PTP] In dtsec, setting TCTRL[TTSE] to 1 ensures that all the packets will be time-stamped during transmission The packet ID and time-stamp are stored in the R_TXTS1-2_ID and R_TXTS1-2_H/L registers 30

For etsec: To get time-stamps of transmit packets on FCB, the following requirements should be met: R_CTRL[RTPE], TxBD[TOE] and TxFCB[PTP] should be set to 1 A minimum of two TxBDs are used per packet The first points to the start of the 8 byte TxFCB The second points to the start of frame data The TxFCB, and at least the first 16 bytes of the TxPAL, must be located in contiguous memory locations The time-stamp is written to memory location TxBD[Data Buffer Pointer]+ 0x10 31

For dtsec: When enabled by setting TCTRL[TTSE], every requested transmit packet will cause the return of a time-stamp value from the dtsec The BMI receives the actual time-stamp after the frame is transmitted In the TX confirmation phase, The BMI writes the time-stamp into the time-stamp field in the internal buffer of the sent frame and issues DMA request to internal buffer to external memory dtsec also supports two-step clock 32

The polarity of TRIG_IN signal can be chosen using R_CTRL[ETEPn] R_TEVENT[ETSn] is set if external trigger is received R_ETTS1 2_H/L stores the time-stamp Attention P1010 has 16 pairs of R_ETTSn_H/L registers 33

Generally PowerQUICC processors and QorIQ communications processors have more than one etsec/dtsec(s) There is a single IEEE 1588 block shared among all etsec(s) in a device Every FrameManager has its own instance of a 1588 hardware assist block All dtsecs corresponding to an FM share the 1588 hardware assist However, there are some registers and interrupts dedicated per etsec/dtsec Tip Since the common 1588 time-stamping registers exist within the etsec1 memory space, the etsec1 controller must remain enabled in order to use 1588 time-stamping for any Ethernet port. 35

The Interrupt controller has different interrupt numbers associated with IEEE 1588 interrupts of different etsecs Interrupts generated on transmission or reception of Ethernet packet are dedicated per-etsec These interrupts are indicated by R_PEVENT Interrupts generated by ALARM, FIPER and external trigger (TRIG_IN) are registered to etsec1 1588 timer These events are shown by R_TEVENT Internal Interrupt Number Interrupt Source 52 etsec1 1588 timer 53 etsec2 1588 timer 54 etsec3 1588 timer 36

All the registers of Hardware Assist IEEE 1588 are valid only on the etsec1 memory region, except for the registers listed below: R_TXTS1 2_ID : Transmit Time Stamp Identification Register R_TXTS1 2_H/L : Transmit Time Stamp Register R_RXTS_H/L : Receive Time Stamp Register R_PEVENT: Timer PTP Packet Event Register R_PEMASK : Timer Event Mask Register R_STAT : Timer Status Register Attention Access to any other register of Hardware Assist IEEE 1588 from memory region other than etsec1 is illegal 37

For dtsec: All the registers of Hardware Assist IEEE 1588 are valid on FMan s 1588 timer module memory region except registers listed below which reside in the dtsec s memory region: R_CTRL is not the same to the R_CTRL register in the 1588 timer module R_PEVENT - Time-stamp event register R_PEMASK - Timer event mask register Comparing to etsec: No R_TXTS1 2_ID Register No R_TXTS1 2_H/L Register No R_RXTS_H/L Register The BMI gets the time-stamp to put into the IC time-stamp field 38

TSEC_1588_CLK_IN: One of the four choices of input clocks TSEC_1588_CLK_OUT: Output of pre-scalar TSEC_1588_TRIG_IN[1:n] : External trigger input TSEC_1588_PULSE_OUT[1:n] : Output of FIPER TSEC_1588_ALARM_OUT[1:n]: Output of ALARM Attention 1. The number of TSEC_1588_TRIG_IN, TSEC_1588_PULSE_OUT and TSEC_1588_ALARM_OUT may vary from device to device 2. There might be some variation in the name of the signal from device to device 39

The application interacts with the network layer to send/receive PTP messages Using IEEE 1588 APIs, the application gets the time-stamps of packets sent or received Based on time-stamps, it decides to tune the clock using IEEE 1588 APIs Application Layer Messaging Unit Network Layer Kernel Hardware Clock Servo Mechanism IEEE 1588 Timer APIs 41

Get the frequency of the input clock Calculate as explained earlier and feed results in ADDEND and TCLK_PERIOD Write desired value to R_PRSC and FIPER Calculate and feed ALARM register Set R_CTRL[FS] to trigger FIPER with ALARM Choose input clock using R_CLK[CKSEL] Start timer by setting R_CTRL[TE] to 1 Initialize rest of the registers for time-stamps and interrupts are required 42

GET_RX_TIMESTAMP : To read time-stamp of packet received GET_TX_TIMESTAMP : To read time-stamp of packet transmitted GET_CNT : Read value of R_CMT SET_CNT : Write new value of R_CNT along with reinitializing FIPER and ALARM ADJ_ADDEND : Write new data to ADDEND GET_ADDEND : Read ADDEND 43

IEEE 1588 Master (MPC8313E-MDS-PB) IXXAT IEEE 1588 application software IEEE 1588 Slave (MPC8313E-MDS-PB) IXXAT IEEE 1588 application S/W 200 150 100 50 0-50 -100-150 -200 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125 129 133 137 PTP stack evaluation version - will stop after 4 hours -0,085857248; 0,000000000; 0,000000000; 0,000000000; 2152; -0,000002152;-0,000002152; 0,000000000; 0,000000000; 3132; -0,000002056;-0,000002056; 0,000000000; 0,000000000; 2960; -0,000000856;-0,000000856; 0,000000000; 0,000000000; 2268; 0,000000264; 0,000000216; 0,000000808;-0,000000048; 1792; 0,000000608; 0,000000560; 0,000000808;-0,000000048; 1648; 0,000000448; 0,000000400; 0,000000808;-0,000000048; 1760; 0,000000112; 0,000000064; 0,000000808;-0,000000048; 1944; -0,000000128;-0,000000176; 0,000000808;-0,000000048; 2032; Plot the Offset from Master Raw Data 45

Offset in ns 1 215 429 643 857 1071 1285 1499 1713 1927 2141 2355 2569 2783 2997 3211 3425 3639 3853 4067 4281 4495 4709 4923 5137 5351 5565 5779 5993 6207 6421 6635 6849 7063 7277 7491 7705 7919 8133 8347 8561 8775 8989 9203 9417 9631 9845 10059 10273 10487 10701 100 Master to Slave Clock Offset 80 60 40 20 0 Series1, 0-20 -40-60 -80-100 46

IEEE 1588 allows precision control over a distributed Ethernet network Precise timing delivery allows drive units to be placed where required Traditional mechanical control mechanisms can limit the placement of systems Timing synchronization at the drive enables flexibility in system configuration Issues due to mismatched cable lengths are minimized Servos can be added or deleted without having to rewire other servos Industrial Control applications typically augment IEEE 1588 hardware to provide trigger inputs and outputs Ethernet E Controller Adapter Motion Controller Master Time Master Time Ethernet E Controller Adapter Motion Controller Servo E Drive Switch Distributed Control Servo E Drive Servo E Drive Servo E Drive Switch Peer Controlling Other Peers Ethernet Ethernet E E Controller Adapter Controller Adapter Motion Controller Motion Controller Servo Servo E E Drive Drive 48

IEEE 1588 allows coordination and control of Test and Measurement equipment over a distributed Ethernet network Spectrum Analyzer Remote Test Controller Trigger In Precise timing delivery allows test equipment to deliver patterns and measure responses at specific times Enables accurate time stamping of measured data Allows coordination of input stimuli and any associated measured data Trigger inputs and outputs enable coordination of other devices Test Board Logic Analyzer Test Point Pattern Generator Ethernet Network Oscilloscope Trigger Out 49

Synch/ Time Server Ethernet Wireline Service Provider Broadband (DSL/Cable) Head End/ Head End/ Aggregation Aggregation Point Point Ethernet Home Femtocell / router Packet Network Ethernet Ethernet Synch/ Time Server IP Network (Ethernet) Head End/ Head End/ Aggregation Aggregation Point Point Home BSC Home Femtocell / router Broadband (DSL/Cable) Femtocell / router 50

Using IEEE 1588 Hardware Assist logic, sub-50ns synchronization can be achieved over the network Hardware support for IEEE 1588 is available in all of the devices of QorIQ communications processor family Currently used in industrial, telecom and consumer (audiovideo sync) applications Synchronized pulses and alarm functionality available in the QorIQ communications processor family Facebook.com/Freescale Tag yourself in photos and upload your own! Tweeting? Please use hashtag #FTF2012 Session materials will be posted @ www.freescale.com/ftf Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter 51

Reference Manuals of QorIQ communications processor AN3423: Application note on IEEE 1588 AN4326: Verification of the IEEE 1588 Interface http://www.nist.gov/el/isd/ieee/ieee1588.cfm 52