Chapter 3 Packet Switching Self-learning bridges: Bridge maintains a forwarding table with each entry contains the destination MAC address and the output port, together with a TTL for this entry Destination MAC address is the key to look for the table If no entries found, the bridge broadcasts to all ports except the one from which the packet comes. Spanning tree algorithm for extended LAN with loops: The bridge with the smallest id is the root Each bridge computes the shortest path to the route; ties are broken by id of the upstream bridge, and the one with smallest id wins Each LAN selects the bridge as its designated bridge; shortest path preferred; smaller ID if path lengths are the same Problem 1: Given the extended LAN shown below, indicate which ports are not selected by the spanning tree algorithm. Assume that bridge B1 suffers catastrophic failure. Indicate which ports are not selected by the spanning tree algorithm after the recovery process and a new tree has been formed. Problem 2: Given the arrangement of learning bridges shown below. Assuming all are initially empty. Give the forwarding tables for each of the bridges B1 B4 after the following transmission sequences: A sends to C; C sends to A; D sends to C
D sends to C; C sends to D; A sends to C Virtual Circuit Switching: 1. For the following example network, give the virtual circuit tables for all the switches after each of the following connections is established. Assume that the sequence of connections is cumulative, that is, the first connection is still up when the second is established, and so on. Also assume that the VCI assignment always picks the lowest unused VCI on each link, starting with 0. (a) D connects to H (b) B connects to G (c) F connects to A (d) H connects to C (e) I connects to E (f) H connects to J
2. Consider the virtual circuit switches in the following figure. The following table lists for each switch what <port VCI> pairs are connected to other. Connections are bidirectional. List all endpoint to endpoint connections. Switch 1: Port i VCI i Port o VCI o 1 2 3 1 1 1 2 3 2 1 3 2 Switch 2: Port i VCI i Port o VCI o 1 1 3 3 1 2 3 2 Switch 3: Port i VCI i Port o VCI o 1 3 2 1 1 2 3 1 A connects to D; A connects to B; B connects to E Cell Switching (ATM): Why use fixed length cells? The implementation of high performance hardware switches is easier o Processing delay of each cell is fixed predicable o Facilitating parallelism Finer control over the behavior of queues o Control delay and delay variation o Eg: for a 4KB packet over a 100Mbps link, the delay is 327.68 microseconds while for a cell (53B), it is only 4.24 microseconds; additionally, the delay variation for fixed cells is very small o Queues of cells tend to be shorter than that of packets It is typical for a switch to wait for the whole packet to arrive before it starts transmitting wait and forward, though the queue is empty. What is the right length of an ATM cell? If too short: overhead will be high due to the header If too long, padding results in bandwidth wastage.
Efficient link utilization and voice traffic should be both considered 48B of payload is a compromise! ATM cell format 1. What percentage of an ATM link s total bandwidth is consumed by the ATM cell headers? [5/53] 2. What percentage of the total bandwidth is consumed by all non payload bits in AAL3/4 and AAL5, when the user data is 512 B in length? AAL3/4 CS PDU format padding to ensure that the trailer is aligned on a 32 bit boundary. From left to the pad field inclusive, it has to be a multiple of 32bits. For a 512B user data, the CS PDU is 520B. 520B divided by 44B, we get 11 44B pieces plus a segment of 36B. They form 12 ATM cells with each 11 having a header/trailer overhead of 9B. The last cell also has a padding of 8B. Therefore 12*9 + 8 + 8= 124B of overhead. The percentage is: 124/(124+512). AAL5 CS PDU format padding to ensure that the trail falls at the tail end of an ATM cell. By encapsulation, we get an AAL5 CS PDU with a length of 528B, which will be segmented into 11 cells. The percentage is (11*5+16)/ [(11*5+16)+512]. 3. Explain why AAL3/4 will not detect the loss of 16 consecutive cells of a single PDU. AAL3/4 relies on a 4bit sequence number to detect unordered/lost cells, which wraps around after 16 cells. There is no CRC checking in the CS PDU. 4. The IP datagram for a TCP ACK message is 40 bytes long: it contains 20 bytes of TCP header and 20 bytes of IP header. Assume that this ACK is traversing an ATM network that uses AAL5 to encapsulate IP packets. How many ATM packets will it take to carry the ACK? What if AAL3/4 is used instead? [one for AAL5 and two for AAL3/4] 5. Suppose a workstation has an I/O bus speed of 1 Gbps and memory bandwidth of 2 Gbps. Assuming DMA in and out of main memory, how many interfaces to 45 Mbps T3 links could a switch based on this workstation handle? [Since the I/O bus speed is less than the memory bandwidth, it is the bottleneck. Effective bandwidth that the I/O bus can provide is 1000/2 Mbps because each packet crosses the I/O bus twice. Therefore, the number of interfaces is 500/45 =11.] 6. Suppose a switch can forward packets at a rate of 100000 per second, regardless (within limits) of size. Assuming the workstation parameters described above. At what packet size would the bus bandwidth become the limiting factor? [The workstation can handle 1000/2 Mbps, as in the previous Exercise. Let the
packet size be x bits; to support 100,000 packets/second we need a total capacity of 100000x bps; equating 10^5 x = 500 10^6 bps, we get x = 5,000 bits/sec = 625 bytes/sec. ]