Digital Integrated Circuit Design II ECE 426/526, Announcements $Date: 2016/06/02 00:31:36 $ Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) Course Website http://ece.pdx.edu/%7eecex26 [Note links are parsed by Adober Reader but may not be parsed by browser viewers] R.Daasch, Por tland State University 1 June 2016
1 June 2016 I was wrong, wrong wrong about final exam start time Final exam is from 7:30PM to 9:20PM 6 June 2016 Thanks goes to Tim N. for his catch New Date to submit Laborator y 2 is 5 June 2016 Link below is a step-by-step guide to create physical layout from schematic Cadence Wiki home page simulation and layout https://projects.cecs.pdx.edu/ projects/cadence/wiki/virtuoso New CAD tools include: SOC Encounter and Mentor Graphics Calibre also checks DRC and LVS Include in your datasheet a comparison of clock timings for schematic and physical (layout) views Reminder : Include units in datasheet for layout view X and Ytwo options are microns µm or λ R.Daasch, Por tland State University 2 June 2016
1 June 2016 In your design test enable can be either TE active LOW or TE active HIGH Submit completed datasheets for adder subtractor design by email Rohan rjagtap@pdx.edu Use correct subject Subject: ECE x26 Laborator y 2 Version {1,2,3} LastName # No late submissions will be accepted R.Daasch, Por tland State University 3 June 2016
23 May 2016 University Closed for Memorial Day, No class Monday 30 May 2016 Final Exam Announcement Final Exam, June 6, 1930-1920 (7:30PM - 9:20PM) Ondine 218 NOTE: Final Exam start time is one hour earlier than class star t time Comprehensive: Chapters 9-15 Laborator y 2 Pre-grade distributed Some did not submit (why hur t yourself?) Points accumulated by pre-grade will be applied to final laborator y score Corrections and additions will be added to final laborator y score R.Daasch, Por tland State University 4 June 2016
23 May 2016 New mater ial will be added to the final laborator y score R.Daasch, Por tland State University 5 June 2016
16 May 2016 Reminder about Ver ilog module identifiers module identifier() Verilog module identifiers begin with either a lowercase letter [a-z], an uppercase letter [A-Z], or the underscore (_) Identifiers of more than one character can include any sequence of letters [a-za-z], digits [0-9], dollar signs ($), and underscore characters (_). Correct module identifiers: AdderSubtractor, _fourbitadder Incorrect module identifiers: 4bitadder, $4bit May 20th or before you may submit one new cell, of your choosing, for early grading. Select and submit only one completed cell datasheet either D Flip-flop Scan Register Design, Overflow and Underflow Combinational Design, or R.Daasch, Por tland State University 6 June 2016
16 May 2016 Scan and Parallel Register Design. Email submit on May 20 one completed datasheet as a PDF to TA, Rohan Jagtap, rjagtap@pdx.edu Subject line Subject: ECE x26 PreLaborator y 2 Cell_NAME LastName # The submitted cell datasheet will be graded and wor th up to 15% of the total Laborator y 2 score You may either accept the grade for the cell or submit a revised datasheet on 29 May 2016 All ear ly grading (errors) have to be fixed to ear n additional score R.Daasch, Por tland State University 7 June 2016
9 May 2016 Pre-submission of one cell of your choice for pre-grading 20 May 2016, submit one cell Submit for one cell a completed datasheet as a PDF by email to TA, Rohan Jagtap. rjagtap@pdx.edu With subject line Subject: ECE x26 PreLaborator y 2 Cell LastName # R.Daasch, Por tland State University 8 June 2016
4 May 2016 Tw o options for place and route structural Ver ilog NC-Ver ilog output with input a structural schematic of standard cells Synthesized output with input a behavioral Ver ilog design Warning: Using structural Ver ilog from synthesis introduces possible inconsistency in Spectre simulation results From CIW -> File -> Import -> Ver ilog R.Daasch, Por tland State University 9 June 2016
2 May 2016 Midter m graded, returned today Each question wor th 20 points ECE 426: 39:67 ECE 526: 55:79 See me during Office hours or by appointment about grading Low scores should set appointment to discuss improving for final exam Combining Laborator y 2 and Laborator y 3 for single due date of final design Combined laborator y descr iption posted by 4 May 2016 Be sure to set transient option to lvl and nestlvl = 1 Completed design submitted 29 May 2016 R.Daasch, Por tland State University 10 June 2016
2 May 2016 Laborator y 2 design a register with both parallel and serial loading options, a one bit-slice and hierarchical design with a 11 bit word Laborator y 3 combines Laborator y 2 register with Addersubtractor R.Daasch, Por tland State University 11 June 2016
25 April 2016 Fortunately the fix is simple for Cadence 6.15 Calculator difference from 6.10 Calculator for the bitgen DC supply in the testbench The trouble is with a single character a / in the name of the current signal name "/Vvdd:p" Removing the / by clicking into the buffer or other editable window and delete the / NO NEED to revert to IC6.1.0 stay with IC 6.1.5 R.Daasch, Por tland State University 12 June 2016
25 April 2016 Red circle arrow on left note / before the /V and / deleted on right in green R.Daasch, Por tland State University 13 June 2016
25 April 2016 Laborator y 1 with power evaluated due date reset to this Fr iday 29 Apr il 2016 Reminder Exam 27 April 2016 Coverage: 9, 10, 11.1,2,10 R.Daasch, Por tland State University 14 June 2016
20 April 2016 Exam 27 April 2016 Entire period Closed book and notes Technology parameters, Equations (e.g. logical effor t) provided on standard cover page Detailed coverage set 25 April 2016; Chapter 9, 10, 11 Spectre notes Limit transient output file sizes by replacing default Options to lvl from allpub Set nestlvl =1 Bitgen buses are noted in schematics as wide-wire bundles R.Daasch, Por tland State University 15 June 2016
20 April 2016 Signal Bitgen Schematic Name Single Bus Bundle Bus A1 A1 A<1:3> A1,A2,A3 A<1> A<1> A<1:3> R.Daasch, Por tland State University 16 June 2016
18 April 2016 Midter m will be 27 April 2016 Coverage 9, 10, 11 Practice Problems for each chapter are available in Assignments Laborator y 1, clarifying FO4 load Nor mally, Sbus is driven by ExOr (or similar gates) and C 4 is NAND The definition of FO4 uses h = C out /C in that is, like gates Use FO4 ExOr loads for Sbus and C4 No new yet for ECE x26 video from Winter 2014, it may be lost R.Daasch, Por tland State University 17 June 2016
13 April 2016 First Call on mid-term exam Tentatively set for 27 April 2016 Midter m no earlier than 27 April For coverage of Chapter 11 be move back to2may R.Daasch, Por tland State University 18 June 2016
11 April 2016 Laborator y 1 bitgen demo PDK 45 Standard cell redefinition that may ease clutter in schematics Not completed yet R.Daasch, Por tland State University 19 June 2016
6 Apr il 2016 Laborator y 1, Standard Cell Place and Route is misnamed and is causing confusion Laborator y 1 prepares the design of the 4-bit adder-subtractor for place and route Place and route (and a new tool Cadence SOC Encounter) is Laborator y 2 To check ifyou have latest revision of the notes the date is added to header page R.Daasch, Por tland State University 20 June 2016
4 Apr il 2016 PDF of syllabus posted Syllabus http://web.cecs.pdx.edu/%7eecex26/ ecex26.cgi?2#2 Laborator y 1 is posted and due 25 April 2016 A standard for mat Word file is used to submit reports. Standard Cell Report http://ece.pdx.edu/ %7Eecex26/doc/Standard_Cell_Report.docx Repor ts do not have to be long. Modeled after the essential elements of standard cell based design documentation. Laborator y 1 http://ece.pdx.edu/%7eecex26/pdf/ laboratory1.pdf Meet Rohan Jagtap, TA R.Daasch, Por tland State University 21 June 2016
4 Apr il 2016 Reminder email subject line use the string ECE x26, Adding course number string to subject reduces the delay for aresponse R.Daasch, Por tland State University 22 June 2016
30 March 2016 TA is Rohan Jagtap, rjagtap@pdx.edu, Office hours in VLSI Lab: Tu Th 2:00-3:00PM or by appointment See Assignments http://ece.pdx.edu/%7eecex26/ ecex26.cgi?3#3/ for chapter reading order Course Coverage of Digital Integrated Circuits II Complete Weste and Harris, CMOS VLSI Design Review ECE x25 Key Chapters: Chapter 4, Chapter 7, Chapter 9 Chapter 10, Sequential Chapter 11, Datapath Chapter 12, Arrays Chapter 13, Special-Purpose R.Daasch, Por tland State University 23 June 2016
30 March 2016 Chapter 15, Test R.Daasch, Por tland State University 24 June 2016
28 March 2016 On email subject line use the string ECE x26, adding this str ing to subject reduces the delay for a response Laborator y 1 is a character ization of standard cells and logic design of a simple adder and subtractor Simplified data sheet for mat PDK cell http:// ece.pdx.edu/%7eecex26/lab/ PDK45_Cell_Datasheet.doc PDK circuit design http://ece.pdx.edu/%7eecex26/lab/ PDK45_Design_Datasheet.doc Points to consider in the shift from logic cells to logic design Input is different for testing a logic design than input for testing a single logic gate Eventually, number of rows in truth table is too large 2 n, n number of inputs Bitgen is a simple Spectre compatible generator for input R.Daasch, Por tland State University 25 June 2016
28 March 2016 Place and route will commence starting with Laborator y 2 R.Daasch, Por tland State University 26 June 2016