Digital Fundamentals Integrated Circuit Technologies 1
Objectives Determine the noise margin of a device from data sheet parameters Calculate the power dissipation of a device Explain how propagation delay affects the frequency of operation or speed of a circuit Interpret the speed-power product as a measure of performance Use data sheets to obtain information about a specific device Explain what the fan-out of a gate means Describe how basic TTL and CMOS gates operate at the component level Recognize the difference between TTL totem-pole outputs and TTL open-collector outputs and understand the limitations and uses of each Connect circuits in a wired-and configuration Describe the operation of tristate circuits Properly terminate unused gate inputs Compare the performance of TTL and CMOS families Handle CMOS devices without risk of damage due to electrostatic discharge State the advantages of ECL Describe PMOS and NMOS circuits Describe an E 2 CMOS cell 2
Basic Operational Characteristics and Parameters for Integrated Circuit Technologies DC Supply Voltage CMOS Logic Levels TTL Logic Levels Noise Immunity Noise Margin Power Dissipation Propagation Delay Speed-Power Product Loading and Fan-Out CMOS Loading 3
Figure 15--1 Example of V CC and ground connection and distribution in an IC package. Other pin connections are omitted for simplicity. 4
Figure 15--2 Input and output logic levels for CMOS. 5
Figure 15--3 Input and output logic levels for TTL. 6
Figure 15--4 Illustration of the effects of input noise on gate operation. 7
Figure 15--5 Illustration of noise margins. Values are for 5 V CMOS, but the principle applies to any logic family. 8
Figure 15--6 Currents from the dc supply. 9
Figure 15--7 Power-versus-frequency curves for TTL and CMOS. 10
Figure 15--8 A basic illustration of propagation delay. 11
Figure 15--9 Propagation delay times. 12
Figure 15--10 Loading a gate output with gate inputs. 13
Figure 15--11 Capacitive loading of a CMOS gate. 14
Figure 15--12 Basic illustration of current sourcing and current sinking in logic gates. 15
Figure 15--13 HIGH-state TTL loading. 16
Figure 15--14 LOW-state TTL loading. 17
CMOS Circuits MOSFET CMOS Inverter CMOS NAND Gate CMOS NOR Open Drain Gates Tristate CMOS Gates 18
Figure 15--15 Basic symbols and switching action of MOSFETs. 19
Figure 15--16 Simplified MOSFET symbol. 20
Figure 15--17 A CMOS inverter circuit. 21
Figure 15--18 Operation of a CMOS inverter. 22
Figure 15--19 A CMOS NAND gate circuit. 23
Figure 15--20 A CMOS NOR gate circuit. 24
Figure 15--21 Open-drain CMOS gates. 25
Figure 15--22 The three states of a tristate circuit. 26
Figure 15--23 A tristate CMOS inverter. 27
Figure 15--24 Handling unused CMOS inputs. 28
TTL circuits Bipolar Junction Transistors TTL Inverter TTL NAND Gate Open-Collector Gate Tristate TTL Gate Schottky TTL 29
Figure 15--25 a BJT. The symbol for 30
Figure 15--26 The ideal switching action of the BJT. 31
Figure 15--27 A standard TTL inverter circuit. 32
Figure 15--28 Operation of a TTL inverter. 33
Figure 15--29 A TTL NAND gate circuit. 34
Figure 15--30 Diode equivalent of a TTL multiple-emitter transistor. 35
Figure 15--31 TTL inverter with open-collector output. 36
Figure 15--32 Open-collector symbol in an inverter. 37
Figure 15--33 Basic tristate inverter circuit. 38
Figure 15--34 An equivalent circuit for the tristate output in the high-z state. 39
Figure 15--35 Schottky TTL NAND gate. 40
Practical Considerations in the use of TTL Current Sinking and Current Sourcing Using Open-Collector Gates for Wired- AND operation Connection of Totem-pole Outputs Open-Collectors Buffer/Drivers Unused TTL Inputs 41
Figure 15--36 Current sinking and sourcing action in TTL. 42
Figure 15--37 A wired-and configuration of four inverters. 43
Figure 15--38 Open-collector wired negative-and operation with inverters. 44
Figure 15 39 Example 15-5: Write the output expression for the wired-and configuration of open-collector AND gates (see below) X = ABCDEFGH 45
Figure 15 40 Example 15-6: a) write the logic expression for X, b) Determine the min value of R p if I OL(max) for each gate is 30 ma and V OL(max) is 0.4V X=ABCDEF I R P = 23.6mA R p = 195Ω 46
Figure 15--41 Totem-pole outputs wired together. Such a connection may cause excessive current through Q 1 of device A and Q 2 of device B and should never be used. 47
Figure 15--42 Some applications of open-collector drivers. 48
Figure 15 43 Example 15-7: Determine the value of the limiting resistor, RL; LED current is 20mA, 1.5V drop in the LED, 0.1V LOW-state output of the gate VR L = 3.4V R L = 170Ω 49
Figure 15--44 Comparison of an open TTL input and a HIGH-level input. 50
Figure 15--45 Methods for handling unused TTL inputs. 51
Comparison of CMOS and TTL Performance 52
Figure 15--46 An ECL OR/NOR gate circuit. 53
Comparison of ECL with TTL and CMOS 54
PMOS, NMOS, and E 2 CMOS PMOS - one of the first high density MOS technologies NMOS circuits were developed as processing technology improved E 2 MOS combined the CMOS and NMOS technologies, this is used in the GALs of chapter 7 and 11 55
Figure 15--47 Basic PMOS gate. 56
Figure 15--48 Two NMOS gates. 57
Figure 15--49 An E 2 CMOS cell. 58
SUMMARY 59