CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng.
CS 265 Midterm #1 Monday, Oct 18, 12:00pm-1:45pm, SCI 163 Questions on essential terms and concepts of Computer Architecture Mathematical questions on binary operations Analysis questions on memory organization Programming questions with vonneumann (ISA) instruction set Exam is open book, open notes, open slides, open assignment and exercise solutions
Lectures covered by Midterm #1 Data Representation (3 lectures) Memory Organization (4 lectures) Classical vonneumann Architecture (2 lectures)
Data Representation
Midterm #1: Data Representation How to do the 4 basic binary arithmetic operations: addition, subtraction, multiplication and division? How to represent signed integer with sign magnitude How to represent signed integer with one s complement How to represent signed integer with two s complement How to represent floating point in computer
Sign magnitude representation First (leftmost significant) bit represents sign Successive bits (for n-bit word, the rightmost N-1 bits) represent absolute value of integer Sample question: what is the 8-bit sign magnitude representation of decimal number -18? +18 = 0 0010010-18 = 1 0010010
One's complement representation Positive number uses positional representation Negative number formed by inverting all bits of positive value, i.e., a 1 is replaced by a 0, and a 0 is replaced by a 1 Sample question: what is the 8-bit one s complement representation of decimal number -18? +18 = 0 0010010-18 = 1 1101101
Two's complement representation Positive number uses positional representation Negative number formed by subtracting 1 from positive value and inverting all bits of result Sample question: what is the 8-bit two s complement representation of decimal number -18? +18 = 0 0010010-18 = 1 1101110
Binary arithmetic operation Sample question: In computer using 8-bit sign magnitude representation, what is the result to subtract binary number 10011000 from 10101011
Binary arithmetic operation Sample question: In computer using 8-bit one s complement representation, what is the 8-bit binary result to add decimal number 23 to decimal number -9
Binary arithmetic operation Sample question: find the sum of decimal number 23 and decimal number -9 in binary using two s complement representation
IEEE Standard 754 IEEE standard 754 defines a generic format to represent single-precision (32 bits) floating point and doubleprecision (64 bits) floating point in modern computer 1 sign bit "biased" exponent (8 bits) "normalized" mantissa (23 bits) Binary floating point = (-1) s x (1.m) x 2 (e-bias) Notice that the 1 in 1.m is always assumed. where, bias = 127
Sample question: express 6.5 in a 32-bit single-precision floating point with the format of IEEE standard 754 Step 1. 6.5 (decimal) = 110.1 (binary) Step 2. Move the radix point until a single 1 appears on the left, and multiply by the corresponding power of 2 1.101 x 2 2 so the sign bit is 0 (positive) the biased exponent is 2 + 127 = 129 = 10000001 = e and the normalized mantissa is 101 (drop the 1, rest zero-fill). 0 10000001 10100000000000000000000 0100 0000 1101 0000 0000 0000 0000 0000 binary or 40D00000 hexadecimal IEEE Standard 754
Memory Organization
Midterm #1: Memory Organization What are the two basic operations on memory? What are the three cache mapping schemes, and how they work to map main memory to cache How to map the virtual memory address to main memory address How CPU get the content of memory with specified address in a computer using cache and virtual memory
Operations on Memory Basic operations to memory Fetch (address): Fetch a copy of the content of memory with the specified address. Store (address, value): Store the specific value into the memory specified by address. A hit is when data is found at a given memory address A miss is when it is not found. hit rate is the percent of time data is found at a given memory address. miss rate is the percentage of time it is not. Miss rate = 1 - hit rate.
direct mapped cache Main memory address is divided in 3 parts Least Significant w bits identify unique byte (or word) Most Significant s bits specify one main memory block The Most Significant s bits are further split into a cache block index field r and a tag of s-r (most significant) Tag Block Word
Direct mapped cache Sample questions: Suppose a computer using direct mapped cache has 2 20 bytes of main memory and a cache of 32 blocks, where each cache block contains 16 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? c) To which cache block will the memory reference 0x0DB63 map?
Fully associative mapped cache In fully associative mapped cache, cache would have to fill up one by one before any blocks are evicted. In fully associative cache, a memory address is partitioned into only two fields: the tag and the word. Tag Word
Fully associative mapped cache Sample questions: Suppose a computer using fully associative cache has 2 16 bytes of main memory and a cache of 64 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields?
Set associative mapped cache An N-way set associative cache mapping is: Similar to direct mapped cache in which a memory reference maps to a particular location in cache. Similar to fully associative cache in which a memory reference maps to a set of several (N) cache blocks, In set associative cache mapping, a memory reference is divided into three fields: tag, set, and word, and the set field determines the set to which the memory block maps. Tag Set Word
Set associative mapped cache Sample question: Suppose a computer using set associative cache has 2 16 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
virtual address vs. physical address virtual address with demand paging is divided into two fields: A page field, and an offset field. Page Offset The page field determines the page location of the virtual address, and the offset indicates the location of the address within the page. The physical address is divided into two fields: A page frame field, and an offset field. Page Frame Offset
virtual address vs. physical address virtual address with demand paging is divided into two fields: A page field, and an offset field. Page Offset The page field determines the page location of the virtual address, and the offset indicates the location of the address within the page. The physical address is divided into two fields: A page frame field, and an offset field. Page Frame Offset
virtual address vs. physical address By checking Translation Lookaside Buffer and updating page table, we can locate the physical memory address behind the virtual address that operated by CPU
Main memory, virtual memory and cache You have a virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. The exact byte in each block is represented by the letter with a number, e,g. 8 bytes stored in letter D are D0,D1,D2,D3,D4,D5,D6 and D7. Two blocks equal one page frame. a) How many bits are in a virtual address for process P? b) How many bits are in a physical address? c) Show the address format for virtual address 18 (decimal) (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: convert 18 to its binary equivalent and divide it into the appropriate fields.), and then give the value stored at memory that fetched by virtual address 18 (decimal)
Main memory, virtual memory and cache
vonneumann Architecture
Midterm #1: vonneumann Architecture What is the general format of a machine instruction? Analysis on the machine instruction code
Format of machine language instruction A machine language instruction consists of: Operation code/opcode, telling which operation to perform Address field(s)/operands, telling the memory addresses of the values on which the operation works. So, a machine language instruction = Opcode + Operands
Format of machine language instruction For Example: ADD X, Y - Opcode ADD tell the ALU to execute the add function - X and Y is the memory address - execute ADD X,Y means ADD content at memory locations X and Y, and store back in memory location Y. Assume: 4-bit opcode for ADD is 9 in decimal, and 8-bit operands, X=99, Y=100 in decimal How to represent the instruction ADD X,Y in computer?
analysis on machine instruction Given the von Neumann Instruction Set illustrated above and a piece of Pseudo instruction code as follows: Address 8L 8R 9L 9R 10L 10R 11L Contents LOAD M(0FA) STOR M(0FB) LOAD M(0FA) JUMP+ M(11,0:19) LOAD M(0FA) STOR M(0FB) Please explain what the program does? Suppose value at 0FA is - 10, what s the value at 0FB after executing the code?
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