Organized by: Dept. of EEE Workshop on Digital Circuit Design in FPGA Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com
Verilog HDL RTL Verilog Code 110101 101010 RTL Verilog Code using Procedural Assignment Structural Verilog coding and Verilog coding using continuous assignment structure are used to design simple digital circuit. This approach is practical when functional complexities are not much (gate count within few hundred). With the increase of functional complexities, the above two approaches are not suitable approach. In designing complex digital circuit, procedural assignment approach is used. In this approach, the functional behavior of the circuit is described using keyword always. Sensitivity list is used with the always statement. Sensitivity list indicates output is sensitive to what?. It contains the list of specific inputs, which have effect on the outputs. Whenever any event (change) occurs in any of the parameter in the sensitivity list, the always loop will be executed. 2
Verilog HDL RTL Verilog Code 110101 101010 How to write RTL Verilog code using Procedural assignment The declaration module, input, output and module are same as used in structural Verilog coding and RTL Verilog coding using continuous assignment structure. It is important to remember that all the outputs have to be declare as register using the keyword reg. The keyword always is used to describe the behavior of the circuit. Sensitivity list has been placed inside the first bracket. The keyword begin and indicates start and completion of the always block respectively. However, the use of begin and is optional. It is just increase the clarity of the code. Within the always block, it is described What does the circuit always do: which is basically the behavior of the circuit. 3
Multiplexer 110101 101010 RTL Verilog code using procedural assignment to design a 4/1 MUX Verilog Code: module multiplexer(a,b,c,d,s,y); input A,B,C,D; input [1:0]S; output Y; reg Y; always @(A or B or C or D or S) begin case(s) 0:Y=A; 1:Y=B; 2:Y=C; 3:Y=D; default: Y=0; case module 4
Seven Segment Decoder 110101 101010 RTL Verilog code using procedural assignment to design a 7-segment Decoder (for common anode display). Verilog Code: 5 module decoder(en, in, out); input en; input [3:0] in; output [6:0] out; reg [6:0] out; always @(en or in) begin if(en==0) out=0; else begin case(in) 4'b0000: out=7'b1000000; 4'b0001: out=7'b1111001; 4'b0010: out=7'b0100100; 4'b0011: out=7'b0110000; 4'b0100: out=7'b0011001; 4'b0101: out=7'b0010010; 4'b0110: out=7'b0000010; 4'b0111: out=7'b1111000; 4'b1000: out=7'b0000000; 4'b1001: out=7'b0010000; default: out=7'b1111111; case module
4-bit up counter and Use of Internal Clock 110101 101010 Internal Clock source of DE2 6
4-bit up counter and Use of Internal Clock 110101 101010 Design of a 4-bit binary up counter. module counter_clk(rst,clk_50,leds); input rst, clk_50; output [3:0]LEDS; reg [27:0]Q; always @(posedge clk_50 or negedge rst) begin if(rst==0) Q=0; else Q=Q+1; assign LEDS=Q[27:24]; module 7
110101 101010 Design of a 4-bit binary up-down counter. 4-bit up-down counter 8
110101 101010 Design a 4-bit Shift Register 4-bit shift register 9 Module shift_4 (IN, OUT, clk, rst); input IN, clk, rst; output OUT; reg M, N, O, OUT; always @(posedge clk or posedge rst) begin if(rst) begin OUT=0; M=0; N=0; O=0; else begin OUT=M; M=N; N=O; O=IN; module
110101 101010 Design of a 128X8 bit RAM RAM module ram_8bit(wr,rd,clk,add,data_in,data_out); input WR,RD,clk; input [6:0]add; input [7:0]data_in; output [7:0]data_out; reg [7:0]data_out; reg [7:0]memory[127:0]; always @(posedge clk) begin if(wr) memory[add]<= data_in; else if(rd) data_out=memory[add]; else data_out=data_out; module 10
110101 101010 Counter with 7-segment decoder Interconnection of Modules 11
110101 101010 Module-1 (Up-Down Counter) Interconnection of Modules (Cont) module count_4updn(rst, sel, clk, Q); input rst, sel, clk; output [3:0] Q; reg [3:0] Q; always @(posedge clk or negedge rst) begin if(rst==0) Q=0; else begin if(sel) Q=Q+1; else Q=Q-1; module 12
110101 101010 Module-2 (Decoder) Interconnection of Modules (Cont) module decoder(en, in, out); input en; input [3:0] in; output [6:0] out; reg [6:0] out; always @(en or in) begin if(en==0) out=0; else begin case(in) 4'b0000: out=7'b1000000; 4'b0001: out=7'b1111001; 4'b0010: out=7'b0100100; 4'b0011: out=7'b0110000; 4'b0100: out=7'b0011001; 4'b0101: out=7'b0010010; 4'b0110: out=7'b0000010; 4'b0111: out=7'b1111000; 4'b1000: out=7'b0000000; 4'b1001: out=7'b0010000; default: out=7'b1111111; case module 13
Interconnection of Modules (Cont) 110101 101010 Interconnection of Module-1 and Module-2 14