Functional Test Generation for Delay Faults in Combinational Circuits

Functional Test Generation for Delay Faults in Combinational Circuits Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242 Abstract We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called is used to control the number of functional faults targeted and thus the number of tests generated. If is unlimited, the functional test set detects every robustly testable path delay fault in any gatelevel implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of are fault simulated on gate-level realizations to demonstrate their effectiveness. 1. Introduction In this work, we consider the modeling of delay faults in combinational circuits at the functional level. We propose a functional fault model for delay faults and describe a functional test generation procedure for this model. We check the validity of this functional approach by applying the test sets it generates to gate-level path delay faults [1]. The path delay fault model is selected since it is the most general delay fault model for gatelevel circuits. Previous works on functional testing of logic faults (such as stuck-at faults) can be found in [2]. The advantages of functional test generation over gate-level test generation are as follows. (1) Functional test generation results in a test set that is independent of the implementation and is applicable to any implementation. (2) The test set can be generated at early design stages and testability problems identified during test generation can be corrected. For path delay faults, functional testing also has an advantage related to the number of faults that need to be targeted. We return to this point in Section 4. The functional fault model proposed here is selected based on two recent works [3,4] that deal with testing of delay faults in circuits containing macros. A macro is a logic block implementing a specific function. Typically, the only information given about a macro is its functional description. Macros are included in a circuit when gate-level descriptions are not available and/or do not accurately describe the operation of a logic block, as well as when tools which are independent of a specific technology or macro library are used. The presence of macros, for which gate-level descriptions are not available, required the development of a functional approach to testing for delay faults inside macros. Several models were developed in [3,4] for this purpose. All the results in [3,4] apply to circuits + Research supported in part by NSF Grant No. MIP-9220549, and in part by NSF Grant No. MIP-9357581 composed of macros, where only individual macros are subject to functional test generation. Moreover, only macros with small numbers of inputs are considered in [4], as the procedure of [4] is based on the truth tables of the macros. In this work, we take a functional approach, independent of implementation, to testing of a complete circuit (and not only individual macros inside the circuit). We propose an appropriate functional fault model, develop a functional test generation procedure for large circuits and demonstrate its results on benchmark circuits. As part of our study, we apply the models of [3,4] to complete circuits (and not only to individual macros inside the circuits as in [3,4]). We show that the models of [3,4] differ in the following parameters. (1) The size of a complete test set for the model, and (2) the coverage of path delay faults in a gate-level implementation of the circuit. We show that the model of [4] covers all path delay faults in an arbitrary gate-level implementation of the circuit. In addition, it covers subsets of path delay faults as defined in [5]. The main disadvantage of the model of [4] is that it results in very large test set sizes. The fault model of [3] results in test sets of practical sizes, however, its coverage of path delay faults in an arbitrary gate-level implementation of the circuit is low. A compromise is also mentioned in [4], that results in fewer tests at the cost of reduced fault coverage. The functional fault model proposed here encompasses the models of [3,4] by using a parameter denoted. When =1, the model reduces to the model of [3]. When is unlimited, the model becomes the complete model of [4]. Intermediate values of allow practical test set sizes to achieve very high fault coverage when applied to gate-level implementations. Only robust tests are considered in this work. The paper is organized as follows. In Section 2 we review the definition of robust propagation in macro-based circuits from [3,4]. In Section 3 we apply the various functional delay fault models of [3,4] to complete circuits. We define a new functional fault model that offers a compromise between test set size and fault coverage, and provide an experimental comparison between the various fault models. In Section 4 we describe a test generation procedure for the proposed functional fault model and provide experimental results. Section 5 concludes the paper. 2. Preliminaries The definitions of robust propagation through a macro given in [3] and [4] are similar. To say that a two-pattern input combination <u,v > robustly propagates a transition from input I to output O of a macro, the value on O must not change before the value on I changes, independent of the order or speed at which other inputs of the macro change (a more formal definition can be found in [4]). To distinguish robust propagation at the gatelevel from robust propagation through a macro (or at the functional level), we refer to the latter as function-robust propagation. The following example from [4] demonstrates the definition of function-robust propagation. Example [4]: Consider the macro M 1 whose truth-table is given

in Table 1. Let the two-pattern input combination (ABC) = <(010), (100)> be applied to M 1. The output value is f = <1,0>. To check whether the rising transition on A function-robustly propagates to f, we keep A at 0, and check whether the changes on the other inputs may cause f to change to 0. B changes from 1 to 0, therefore we must consider both values of B, orb=x. Cis stable at 0, therefore, we need only consider C = 0. The resulting vector is (ABC) = (0x 0), and it covers the two input combinations (000) and (010). For both input combinations, the resulting value on f is 1. Therefore, we conclude that as long as A does not change, f remains at 1 regardless of the speed or order in which the other inputs (B in this case) change. As a result, the transition on A propagates to f function-robustly. Table 1: Macro M 1 A B C f 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Logic hazards must be considered in defining robust propagation. In [4], logic hazards that can potentially occur in the (unknown) physical implementation of a macro are ignored, and the definition of function-robust propagation is based only on the information available from the functional description of the macro. In [3], the existence of hazards is verified by using a gate-level description whenever one is available. If one is not available, it is assumed that logic hazards exist, and only input patterns involving a single-input change are considered for function-robust propagation. However, using input patterns involving a single input change does not guarantee robustness of tests. Additionally, it limits the number of macro input patterns from which a test for the macro can be constructed. 3. Functional delay fault models In this section we apply the fault models proposed in [3] and [4] to functional testing of complete circuits (not only to macros embedded inside a circuit) and propose a new fault model applicable to large circuits. We study the effectiveness of these models by considering circuits with relatively small numbers of inputs. Consideration of circuits with small numbers of inputs allows us to eliminate the effects of incomplete fault coverage due to aborted faults and due to accidental detection, as explained below, and concentrate on the advantages and disadvantages of each model. For each circuit considered, we use a functional description in the form of a truth-table, and two gate-level implementations. The gate-level implementations are used to evaluate the effectiveness of the functional test sets generated for the various models. One of the gate-level implementations (called GL1) is a multi-level implementation obtained using MIS-II [6] and the other (called GL2) is a two-level implementation obtained using ESPRESSO [7]. We use several functional fault models to generate test sets using the functional description of the circuit, and then simulate these test sets on the two gate-level implementations. We also use a gate-level test generation procedure for the gate-level path delay fault model and compare the results to the results of functional test generation. The comparisons allow us to determine the tradeoffs between test generation complexity, test set size and gate-level fault coverage for the various models. The following delay fault models are considered. The first one is the conventional path delay fault model defined on a gate-level description. It is included for comparison purposes. Gate-level (GL) - Every physical path is included twice, with a rising and with a falling transition at the source of the path. The following models were defined for macro-based circuits in [3] and [4]. They are given here for general circuits. Functional 1 (referred to as F1 and derived from [4]) - Every two-pattern input combination that function-robustly propagates an input transition to an output may independently incur an extra delay and corresponds to a delay fault. A complete test set must include every such input combination. Functional 2 (referred to as F2 and derived from [3]) - Four delay faults are associated with every input I and every output O. The four faults correspond to a rising or falling transition on I, function-robustly propagated to O, and causing a rising or a falling transition on O. The four faults for (I,O) result from the four combinations of {falling,rising} transitions on I and O. A complete test set for this model function-robustly propagates one rising and one falling transition from every primary input to every primary output, arriving at the output once as a rising and once as a falling transition. Next, we propose a new fault model, that encompasses both F1 and F2. The model has a parameter, that can be adjusted according to circuit size. Functional 3 (referred to as F3) -4. tests are required for every input I and every output O. For every input transition tri {rising, falling} on I and every output transition tro {rising, falling} ono, different tests are required, that function-robustly propagate a tri transition from I to O, arriving as a tro transition to O. To simplify the presentation, we use the following definition. A two-pattern input combination that functionrobustly propagates a tri transition from input I to output O, arriving at O as a tro transition, is called an (I,O,trI,trO) test. Using this definition, a complete test set for F3 includes (I,O,trI,trO) tests for every input I, output O, input transition tri and output transition tro. The relationships between F1, F2 and F3 are as follows. Setting =1 in F3 yields F2. Removing the bound on (making as large as possible) in F3 yields F1. Test generation procedures for small circuits according to the models above are described next. Consideration of small circuits allows generation of complete tests sets, i.e., test sets that detect every detectable fault. In addition, the test sets generated are as small as possible, to avoid unintentional detection of faults due to the inclusion of tests which are not necessary for the fault model under consideration. All test generation procedures have the following structure. First, an exhaustive test set is obtained, i.e., every two-pattern test is considered and every test that detects any fault is recorded. A covering procedure is then used to select a minimal test set out of the candidate tests. The gate-level test generation procedure for GL proceeds as follows. Procedure 1: Gate-level test generation (1) Set T =φ. (2) For every two-pattern input combination t:

(a) Simulate t on the gate-level circuit to find all the path delay faults it detects robustly. (b) If t detects any fault, store t in T together with the faults it detects. (3) Select a minimal subset T of T that detects all detectable faults. T is the required test set. For F1, a covering procedure is not needed, since every two-pattern test that propagates a transition function-robustly from any input to any output has to be included in the test set. The test generation procedure for F1 proceeds as follows. Procedure 2: Test generation for F1 (1) Set T =φ. (2) For every two-pattern input combination t: (a) Use the truth-table of the circuit to check if t propagates function-robustly any input transition to an output. (b) If t propagates any transition, store t in T. (3) T is the required test set. The test generation procedures for F2 (which is equivalent to F3 with =1) and for F3 with various values of are combined in the next procedure, followed by an example. Procedure 3: Test generation for F2 and F3 (1) Set T =φ. (2) For every two-pattern input combination t: (a) Find from the truth-table of the circuit all the (input,output) pairs (I,O) such that t propagates a transition function-robustly from I to O. Let the transitions on I and O be tri and tro, respectively. (b) If t propagates any transition, store t together with the corresponding tuples (I,O,trI,trO) int. (3) Set T =φ. For every tuple (I,O,trI,trO), set covered [I ][O ][tri ][tro ] = 0(covered [I ][O ][tri ][tro ]is the number of (I,O,trI,trO) tests in T ). (4) For every value of, =1,2,..., max : (a) Call Procedure cover ( ). Procedure cover ( ) adds to T a minimal number of tests to ensure that for every I, O, tri and tro, T contains different (I,O,trI,trO) tests (or a maximum number of (I,O,trI,trO) tests if the maximum is smaller than ). (b) T is the required test set for. Procedure cover () first searches for tests in T that must be included in T to achieve covered [I ][O ][tri ][tro ] = for some tuple (I,O,trI,trO). It then uses a greedy heuristic to select additional tests. Procedure cover ( ): (1) For every I, O, tri and tro, if covered [I ][O ][tri ][tro ] < : (a) Let the number of (I,O,trI,trO) tests in T that have not been selected yet be n. (b) If n +covered [I ][O ][tri ][tro ] : (i) Add to T every (I,O,trI,trO) test t in T. (ii) For every test t added to T and for every tuple (Ĩ,Õ,trĨ,trÕ), if t is an (Ĩ,Õ,trĨ,trÕ) test, then increment covered [Ĩ][Õ][trĨ][trÕ] by1. (2) For every test t / T, count the number of tuples (I,O,trI,trO) such that covered [I ][O ][tri ][tro ] < and t is an (I,O,trI,trO) test. (3) Select the test t for which the count is maximum and add it to T. For every tuple (Ĩ,Õ,trĨ,trÕ), if t is an (Ĩ,Õ,trĨ,trÕ) test, then increment covered [Ĩ][Õ][trĨ][trÕ] by 1. Example : Exhaustive simulation of all two-pattern input combinations of the circuit shown in Figure 1 yields the tests shown in Table 2. For every test we list in Table 2 the tuples it covers. Note that there are some tuples that are never covered, like (A, f,rising, falling). For =1, Step 1 of procedure cover () does not select any tests. This is because every tuple in the table appears at least twice. In Step 2, tests 3, 9, 15 and 18 are selected, since they each cover the maximum number of tuples, 2. For =2, test 4 must be added to obtain covered [B ][f ][falling ][rising ] = 2. Similarly, tests 8, 14 and 21 must be added for (B, f,rising, falling), (B, f, falling, falling) and (B, f,rising,rising), respectively. In addition, we select tests 0, 2, 6 and 19, each testing an additional tuple. A B C Figure 1: An example of Procedure 3 Table 2: A test set for the circuit of Figure 1 test tuples 0 <001,000> (C, f, falling, falling) 1 <101,000> (C, f, falling, falling) 2 <000,001> (C, f,rising,rising) 3 <010,001> (B, f, falling,rising)(c, f,rising,rising) 4 <011,001> (B, f, falling,rising) 5 <100,001> (C, f,rising,rising) 6 <110,010> (A, f, falling, falling) 7 <111,010> (A, f, falling, falling) 8 <001,011> (B, f,rising, falling) 9 <101,011> (A, f, falling, falling)(b, f,rising, falling) 10 <110,011> (A, f, falling, falling) 11 <111,011> (A, f, falling, falling) 12 <001,100> (C, f, falling, falling) 13 <101,100> (C, f, falling, falling) 14 <110,100> (B, f, falling, falling) 15 <111,100> (B, f, falling, falling)(c, f, falling, falling) 16 <000,101> (C, f,rising,rising) 17 <100,101> (C, f,rising,rising) 18 <000,110> (A, f,rising,rising)(b, f,rising,rising) 19 <010,110> (A, f,rising,rising) 20 <011,110> (A, f,rising,rising) 21 <100,110> (B, f,rising,rising) 22 <010,111> (A, f,rising,rising) 23 <011,111> (A, f,rising,rising) Note that by increasing by 1 in every iteration of Step 4, Procedure 3 ensures that if 1 < 2, then the test set T 1 obtained for 1 and the test set T 2 obtained for 2 satisfy T 1 T 2. This ensures that when T 1 and T 2 are simulated on a physical implementation of a circuit (e.g., a gate-level implementation), the fault coverage of T 2 is at least as high as that of T 1. + f

Test generation results obtained by Procedures 1-3 are given in Table 3. In Table 3(a) we give the results for GL and F1. In Table 3(b) we consider all two-pattern input combinations as candidate tests under F2 and F3. In Table 3(c) we consider F2 and F3 using only two-pattern input combinations where the two patterns differ in the value of a single input [3]. The results under column "GL for GL1" include the number of tests, the number of detected faults (det) and the total number of faults (flts) when gate-level test generation (model GL) is carried out on the gate-level description GL1. The results for F1 include the following information. (1) The number of tests. (2) The range of covered [I ][O ][tri ][tro ], i.e., the range of the number of (I,O,trI,trO) tests for the various tuples (I,O,trI,trO). We give the smallest value and the largest value over all tuples (I,O,trI,trO). For example, for adr 4, there are tuples which are never tested and there are tuples tested by 4096 different input combinations. (3) The average value of covered [I ][O ][tri ][tro ], where the average is taken only over tuples where covered [I ][O ][tri ][tro ] > 0. The range and average value of covered are important in deciding on appropriate values of for F3. The results for F2 and F3 include only the number of tests. F3 is computed for various values of. Table 3: Test generation results (a) GL and F1 GL on GL1 F1 circuit inp tests det/flts tests range (average) Z9sym 9 391 644/644 8232 112-1176 (644.0) adr4 8 61 210/210 50140 0-4096 (1049.3) dk27 8 22 128/128 7508 0-1280 (269.5) radd 8 48 170/170 50140 0-4096 (1049.3) rd53 5 89 154/154 265 0-32 (12.0) z4 7 65 190/190 9532 0-760 (239.1) (b) F2 and F3 with multi-input change circuit Z9sym 12 59 116 232 1476 2152 adr4 26 118 236 479 2562 4809 dk27 21 159 290 553 1562 2558 radd 25 119 234 473 2546 4782 rd53 27 135 212 245 265 265 z4 24 113 222 432 2258 4346 (c) F2 and F3 with single input change circuit Z9sym 36 180 360 720 1008 1008 adr4 56 280 544 976 2048 2048 dk27 34 224 308 308 308 308 radd 56 280 544 976 2048 2048 rd53 30 130 160 160 160 160 z4 44 220 416 680 896 896 Results of fault simulation of the functional test sets of Table 3 on the multi-level gate-level implementation GL1 are given in Table 4. The coverage of the GL test set of Table 3 on the GL1 circuits is already given in Table 3. The fault coverage obtained under F1, F2 and F3 should be compared to the fault coverage reported in Table 3(a) under column GL1, which is complete gate-level fault coverage. Table 4: Results of fault simulation on GL1 (a) Multi-input change circuit F1 Z9sym 644/644 21/644 81/644 138/644 248/644 395/644 448/644 adr4 210/210 103/210 154/210 174/210 187/210 204/210 208/210 dk27 128/128 121/128 128/128 128/128 128/128 128/128 128/128 radd 170/170 100/170 128/170 138/170 145/170 166/170 170/170 rd53 154/154 49/154 127/154 154/154 154/154 154/154 154/154 z4 190/190 76/190 123/190 148/190 176/190 187/190 190/190 (b) Single input change circuit Z9sym 36/644 146/644 266/644 492/644 644/644 644/644 adr4 98/210 160/210 188/210 204/210 210/210 210/210 dk27 125/128 128/128 128/128 128/128 128/128 128/128 radd 96/170 116/170 156/170 166/170 170/170 170/170 rd53 56/154 148/154 154/154 154/154 154/154 154/154 z4 74/190 146/190 172/190 186/190 190/190 190/190 Gate-level test generation for another set of gate-level circuits, called GL2, yielded the results shown in Table 5 (note that the results of Table 5 do not involve functional test generation, but only gate-level test generation for the gate-level circuits GL2). Results of simulating the test sets derived in Table 3 on the GL2 circuits are given in Table 6. We used the test sets generated for the gate-level description GL1, as well as the functional test sets under F1, F2 and F3. The fault coverage of Table 6 should be compared to the fault coverage of Table 5, where complete fault coverage is achieved. Table 5: Results of gate-level test generation for GL2 circuit tests Z9sym 1008/1008 485 adr4 680/680 235 dk27 134/134 22 radd 680/680 235 rd53 282/320 160 z4 504/504 185 From Tables 3-6 it can be seen that F1 always yields complete fault coverage for both implementations, however, at the cost of a large number of tests. F2 yields the lowest fault coverage, but also the lowest number of tests. F3 is a compromise between the number of tests of F2 and the fault coverage of F1. In addition, we note that when the test set generated using the gate-level description GL1 is applied to a different gate-level description GL2, the fault coverage is in most cases low. It is also interesting to see that two-pattern tests where the two patterns differ in a single input (Tables 4(b) and 6(c)) yield higher fault coverage than tests that differ in the values of multiple inputs (Tables 4(a) and 6(b)). Furthermore, the number of tests for single input changes is smaller than for multi-input changes for the same value of, when =100,200. Next, we prove that a test set according to F1 will result in complete coverage of every robustly detectable fault in any

Table 6: Results of fault simulation on GL2 (a) GL and F1 circuit GL1 F1 Z9sym 688/1008 1008/1008 adr4 210/680 680/680 dk27 131/134 134/134 radd 165/680 680/680 rd53 170/320 282/320 z4 193/504 504/504 (b) Multi-input change circuit Z9sym 20/1008 98/1008 184/1008 360/1008 600/1008 678/1008 adr4 99/680 211/680 296/680 383/680 538/680 572/680 dk27 122/134 133/134 133/134 134/134 134/134 134/134 radd 94/680 201/680 301/680 380/680 516/680 552/680 rd53 50/320 193/320 282/320 282/320 282/320 282/320 z4 69/504 157/504 234/504 346/504 444/504 488/504 (c) Single input change circuit Z9sym 36/1008 180/1008 360/1008 720/1008 1008/1008 1008/1008 adr4 135/680 297/680 427/680 544/680 680/680 680/680 dk27 130/134 134/134 134/134 134/134 134/134 134/134 radd 150/680 274/680 403/680 522/680 680/680 680/680 rd53 61/320 252/320 282/320 282/320 282/320 282/320 z4 93/504 253/504 383/504 465/504 504/504 504/504 gate-level implementation. Theorem 1: A complete test set according to F1 for a functional description S robustly detects every robustly testable path delay fault in any gate-level implementation of S. Proof: Let T be a complete test set according to F1 for a functional description S. Let C be a gate-level circuit implementing S. Let d be a robustly testable path delay fault in C from input I to output O. Let the path associated with d be p = (I=g 0,g 1,g 2,...,g k =O) and let d be associated with an α β transition on I, that arrives in O as a γ δ transition. Let t = <u,v> be a robust test for d. We show that t T. Since t propagates the transition α β from I along p robustly, g 1 does not change unless I changes, g 2 does not change unless g 1 changes, and so on. In general, g i +1 does not change unless g i changes for 0 i k 1. Consequently, O does not change unless I changes. As a result, t satisfies the conditions of function-robust propagation, and t T. The following example demonstrates that a test set according to F1 also detects faults affecting a subset of paths that have to be tested together, as defined in [5]. In [5], a subset of paths is tested together when no individual path delay fault can be tested, however, a fault affecting all the paths in the subset is testable. This concept was demonstrated in [5] by the circuit shown in Figure 2. The falling path delay fault along path (a,d, f ) and the falling path delay fault along path (c,d, f ) are not robustly testable. However, if both paths are faulty, the twopattern test <(111),(010)> detects the fault. Next, we show that <(111),(010)> is included in a test set under F1. Consider input a. To check if the transition from a is robustly propagated under the two-pattern input combination <(111),(010)>, we set a = 1, b = 1 and c = x. Two input combinations need to be checked, 110 and 111. Both yield f = 1. Therefore, the transition on a is function-robustly propagated to f under <(111),(010)>, and it is included in a test set under F1. a b c a c a c d e g Figure 2: An example from [5] In summary, test sets according to F1 have the important property that they include a robust test for every robustly testable path delay fault in any gate-level implementation. They are also effective for subsets of paths. However, test set sizes for F1 are large, as can be seen from Table 3. The results indicate that F3 with an appropriate value of is a cost-effective way to cover delay faults in an arbitrary implementation. For circuits where there are no subsets of paths that need to be tested together, F1 can be modified to include only twopattern input combinations that differ in the value of a single input. Theorem 1 is valid for such circuits with the reduced test set. 4. Functional testing The effectiveness of the fault model F3 in detecting large numbers of path delay faults was demonstrated in Section 3 for small circuits described using truth tables. In this section, we investigate the use of F3 as a functional delay fault model for large circuits, that do not have compact truth table representations. The circuits are assumed to be described by a set of Boolean equations. We do not impose any constraints on the form in which these equations are given. We only require that it would be possible to evaluate the output values of the circuit for any given input pattern over the values {0,1,x}. Before starting test generation, a fault list is created, containing only (I,O,trI,trO) tuples that can potentially be tested. We describe the construction of the fault list in Section 4.1 The test generation procedure is describe in Section 4.2. Experimental results of this procedure are given in Section 4.3. In this section, we use gate-level circuit descriptions instead of writing equations to describe the circuits, however, these circuits should be viewed as graphical representations of the equations, and are not necessarily the gate-level implementations of the circuits-under-test. 4.1 Fault list construction Before starting test generation, a fault list is created that contains only tuples (I,O,trI,trO) such that an (I,O,trI,trO) test potentially exists. In our implementation, the fault list contains only tuples (I,O,trI,trO) such that there is at least one path from I to O. In addition, we require that at least one path would have a number of inverters that allows a tri transition on input I to arrive at output O as a tro transition. For example, if all the paths from I to O have an even number of inverters (O is positive-unate in I), then only the tuples (I,O,rising,rising) and + f

(I,O, falling, falling) are included in the fault list. The construction of the fault list is illustrated by the following example. Example : Consider the circuit shown in Figure 3. The fault list is constructed as follows. There are both even and odd numbers of inverters on paths from A to f 1 and from B to f 1. Consequently, any combination of tri and tro transitions is possible for A and f 1 and for B and f 1. The fault list contains (A, f 1,rising,rising), (A, f 1,rising, falling), (A, f 1, falling,rising), (A, f 1, falling, falling), (B, f 1,rising,rising), (B, f 1,rising, falling), (B, f 1, falling,rising), (B, f 1, falling, falling). There is no path from C to f 1, therefore, no fault of the form (C, f 1,trC,trf 1 ) is included in the fault list. All the paths from A, B and C to f 2 have even numbers of inverters. Therefore, only the following faults are included in the fault list. (A, f 2,rising,rising), (A, f 2, falling, falling), (B, f 2,rising,rising), (B, f 2, falling, falling), (C, f 2,rising,rising), (C, f 2, falling, falling). A B C Figure 3: An example of fault coverage computation The number of tuples in the fault list is at most 4N I N O, where N I is the number of inputs and N O is the number of outputs. Since each tuple is targeted times, the number of target faults is at most 4N I N O. If N eo (I,O) pairs have paths with even and odd numbers of inverters on them, N e (I,O) pairs have only paths with even numbers of inverters, N o (I,O) pairs have only paths with odd numbers of inverters, and N (I,O) pairs are not connected by any path, then the number of tuples in the fault list is 4N eo +2(N e +N o ). 4.2 Test generation We use the following terminology to describe the test generation procedure. The values on output O under an incompletely specified two-pattern input combination <c 1,c 2 > are said to be compatible with a rising transition if the value of O under c 1 is either 0 or x, and under c 2 it is either 1 or x. Similarly, the values on output O under a two-pattern input combination <c 1,c 2 > are said to be compatible with a falling transition if the value of O under c 1 is either 1 or x, and under c 2 it is either 0 or x. Test generation proceeds in iterations. In each iteration, all the (I,O,trI,trO) tuples in the fault list are considered. For every tuple such that covered [I ][O ][tri ][tro ] <, an attempt is made to generate at least one test. If a test is generated, the values of covered [I ][O ][tri ][tro ] are updated for all (I,O,trI,trO) in the fault list and the next tuple is considered. Test generation is terminated when covered [I ][O ][tri ][tro ] = for every (I,O,trI,trO) or when no test is generated during a complete iteration, for any tuple considered. To generate a test for a given tuple (I,O,trI,trO), several two-pattern input combinations are evaluated. They are created by starting from + + f 1 f 2 <c 1,c 2 > where I assumes a tri transition and the other inputs are unspecified. Additional inputs are then specified to create several different pairs of cubes where I assumes a tri transition. New cubes are generated until a tro transition is created on O. The corresponding pair of cubes is then simulated. In the process of cube generation, any two-pattern input combination <c 1,c 2 > such that c 1 and c 2 differ in more than N inputs (where N is a predetermined constant) is discarded, for the following reason. Let <c 1,c 2 > differ in the values of k inputs, I 1,I 2,...,I k. To check whether <c 1,c 2 > function-robustly propagates a transition from an input I j to an output O, we need to consider 2 k 1 input combinations where I j is kept constant and I 1,...,I j 1,I j+1,...,i k assume every combination of {0,1} values. To restrict the complexity of this check, k is restricted to be at most N (N 8 in our experiments). In Procedure 4 below, a new iteration where all (I,O,trI,trO) tuples are considered is started in Step 2. A new tuple is selected in Step 3. Test generation for a given tuple is carried out in Steps 4-9. An iteration terminates if the check in Step 10 shows that all tuples have been considered in the current iteration, and Step 11 is reached. Procedure 4: Functional test generation (1) Set T =φ. Create the fault list. Set covered [I ][O ][tri ][tro ] = 0 for every (I,O,trI,trO) in the fault list. (2) Unmark all tuples in the fault list. (3) Select from the fault list an unmarked tuple (I,O,trI,trO) such that covered [I ][O ][tri ][tro ] < and mark it. (4) Set T to contain a single pair of cubes <c 1,c 2 > where input I is assigned a tri transition and all other inputs are unspecified (x). (5) Select a pair of cubes <c 1,c 2 > T and an input I j which is not specified in <c 1,c 2 >. (6) Compute the following four pairs of cubes based on <c 1,c 2 >: <c 1,c 2 > 00 where I j = 0 in both c 1 and c 2. <c 1,c 2 > 01 where I j = 0inc 1 and I j = 1inc 2. <c 1,c 2 > 10 where I j = 1inc 1 and I j = 0inc 2. <c 1,c 2 > 11 where I j = 1 in both c 1 and c 2. (7) For every pair of cubes <c 1,c 2 > αβ computed in Step 6, if the cubes differ in the values of at most N inputs: (a) Find the values on O under <c 1,c 2 > αβ. (b) If output O assumes a tro transition: (i) Randomly select a value for every unspecified input and set the input to this value in both c 1 and c 2. (ii) Simulate the resulting two-pattern test t. (iii) If t is effective in function-robustly testing any tuple (Ĩ,Õ,trĨ,trÕ) for which covered [Ĩ][Õ][trĨ][trÕ] < : 1) Add t to T. 2) Increment covered [Ĩ][Õ][trĨ][trÕ] by1for every (Ĩ,Õ,trĨ,trÕ) such that t is an (Ĩ,Õ,trĨ,trÕ) test. Otherwise, if output O is compatible with a tro transition, add the pair <c 1,c 2 > αβ to T. (8) Remove <c 1,c 2 > from T. (9) If no test was added to T, T is not empty, and the number of times Step 5 has been repeated for the current tuple in

the current iteration is smaller than M, go to Step 5 (M = 100 in our experiments). (10) If there is an unmarked tuple in the fault list, go to Step 3. (11) If no test was generated for any tuple since it was last marked in Step 3, stop: T is the required test set. (12) If there exists a tuple (I,O,trI,trO) for which covered [I ][O ][tri ][tro ] <, go to Step 2. The following example illustrates Procedure 4. Example : Consider the circuit of Figure 1 with =3. Iteration 1 starts with the tuple (A, f,rising,rising). Initially, T = {<0xx,1xx>}. The pair of cubes <0xx,1xx> is selected. The input selected to expand the cube pair is B and the following four pairs of cubes are created. p 1 = <00x,10x>, p 2 = <00x,11x>, p 3 = <01x,10x> and p 4 = <01x,11x>. p 1 results in f = <x,x> and it is kept in T. p 2 results in f = <x, 1>and it is kept in T. p 3 results in f = <0,x> and it is kept in T. p 4 results in f = <0,1> and it is therefore used to generate a test, as follows. First, the value of C is randomly set to 0. The two pattern test <(010),(110)> is then simulated. It covers the tuple (A, f,rising,rising), therefore, the test is kept in T. Since a test was generated, the next tuple in the fault list is considered. We omit the description of several tuples and skip to the tuple (B, f,rising,rising). Initially, T = {<x 0x,x 1x>}. The pair of cubes <x 0x,x 1x> is selected. The input selected to expand the cube pair is A and the following four pairs of cubes are created. p 1 = <00x,01x>, p 2 = <00x,11x>, p 3 = <10x,01x> and p 4 = <10x,11x>. p 1 and p 3 result in f = <x, 0>and they are removed from T since they cannot result in a rising transition on f. p 2 and p 4 result in f = <x, 1>and they are kept in T. Since no test was generated, we select one of the cube pairs in T, <10x,11x>. The following new cube pairs are created. p 1 = <100,110>, p 2 = <100,111>, p 3 = <101,110> and p 4 = <101,111>. p 1 results in f = <0,1> and it is therefore simulated. It covers the tuple (B, f,rising,rising), therefore, the test is stored in T. p 2 results in f = <0,1> and it is therefore simulated. It does not cover any tuple. p 3 and p 4 result in f = <1,1> and they are therefore dropped. Since a test was generated, the next tuple in the fault list is considered. We omit the description of the remaining tuples in this iteration. At the end of the first iteration, the values of covered [I ][O ][tri ][tro ] shown in Table 7 are obtained. Note that although each tuple was targeted only once, some tuples are covered twice, due to tests generated for other tuples. Next, all the tuples in the fault list are considered again. The results obtained at the end of the second iteration are also shown in Table 7. The third iteration does not result in any additional tests and Procedure 4 is terminated. Table 7: An example of test generation fault count after I O tri tro Iteration 1 Iteration 2 A f rising rising 1 3 A f falling falling 1 3 B f rising rising 1 2 B f rising falling 1 2 B f falling rising 2 2 B f falling falling 2 2 C f rising rising 2 3 C f falling falling 2 3 4.3 Experimental results We applied Procedure 4 to several benchmark circuits. We allowed at most iterations and terminated Procedure 4 after iterations even if the last iteration was effective in covering new tuples. This was done to ensure a reasonable execution time. We allowed the number of input changes in a test, N, to vary from 1 to 8, to obtain tests with single and multi-input changes. We start with N = 1 since the results of Tables 3, 4 and 6 indicate that tests with single input changes are more effective than tests with multi-input changes, especially for large values of. Nevertheless, we found that it is possible to increase the fault coverage achieved by Procedure 4 if it is allowed to generate additional tests, with larger values of N. One of the parameters we captured was the fault coverage under F3, defined as follows. The denominator of the fault coverage is the size of the fault list multiplied by. The numerator is obtained as follows. For every tuple (I,O,trI,trO) in the fault list, we find covered [I ][O ][tri ][tro ]. If this number is larger than, we replace it by. We then add all the numbers. After applying Procedure 4, we applied gate-level fault simulation to find the fault coverage of gate-level path delay faults. The results are reported in Table 8 as follows. After circuit name, we give the number of inputs and the number of outputs. The results of Procedure 4 are given next, including the number of tests and the fault coverage under F3. Next, we give the results of simulation of the test set generated under F3 on GL1 and GL2. For Berkeley PLAs, GL1 is a multi-level implementation [6] and GL2 is a two-level implementation [7]. For ISCAS89 benchmark circuits, GL1 is an irredundant gate-level circuit, and GL2 is the gate-level circuit obtained from the irredundant implementation after applying resynthesis to reduce the number of gates and the number of paths in the circuit, thus making it more path delay fault testable. For each gate-level circuit, we give in Table 8 the number of detected faults, the total number of faults and the number of tests that were effective in detecting any new gate-level path delay fault. In Table 8(a) we give the results using =100. In Table 8(b) we give the results using =200, but only when an improvement over the results with =100 is obtained. It is interesting to compare the gate-level fault coverage reported in Table 8 to the fault coverage obtained when applying pure random patterns and when applying deterministic test patterns. In Table 9 under column "pure random" we show the fault coverage obtained when applying 100,000 random two-pattern tests to the GL1 circuits of Table 8. Circuit name is followed by the number of faults detected, the number of effective tests, and the last effective test, that detected any fault not detected before. Under column "determ [8]" we show the number of faults detected by the deterministic test generation procedure of [8] in the GL1 circuits. Under column "functional" we repeat the results obtained in Table 8 for the GL1 circuits. It can be seen that in most cases, the patterns generated through functional test generation in Table 8 are significantly more effective than pure random patterns. The functional patterns achieve fault coverage which is very close to the fault coverage achieved by deterministic patterns. Observing that the fault coverage of F3 is very close to the fault coverage of deterministic test generation that targets the circuit-under-test, we are currently investigating the use of F3 as a substitute to gate-level test generation, to alleviate the need to consider large numbers of path delay faults in large circuits. Under F3, we need to target only 4N I N O tuples, which is con-

Table 8: Experimental results of Procedure 4 (a) =100 F3 GL1 GL2 circuit inp out tests f.c. det/flts eff.tsts det/flts eff.tsts Z9sym 9 1 1644 64.17 644/644 644 1008/1008 1008 add6 12 7 10055 95.61 459/498 299 2878/4392 1442 adr4 8 5 4752 91.11 210/210 132 680/680 426 alu1 12 8 6271 99.80 76/76 63 82/82 69 alu2 10 8 9386 83.55 260/260 161 561/584 385 alu3 10 8 9037 81.59 282/282 177 561/572 391 co14 14 1 1013 28.75 144/144 144 392/392 392 dk17 10 11 7282 71.30 340/340 108 386/394 115 dk27 8 9 2672 60.08 128/128 37 134/134 38 dk48 15 17 10219 62.61 572/572 88 574/576 79 mish 94 34 21959 95.74 280/280 237 325/328 268 radd 8 5 4596 90.78 170/170 100 680/680 434 rckl 32 7 18440 91.86 476/476 250 1909/3792 895 rd53 5 3 160 12.00 154/154 98 282/320 160 vg2 25 8 16164 92.35 480/492 287 1243/1608 739 x1dn 27 6 17313 94.02 432/440 308 1368/1928 931 x9dn 27 7 17320 95.30 582/612 316 1663/2276 971 z4 7 4 3136 85.20 190/190 128 504/504 328 irs510 25 13 13030 95.11 699/738 357 699/738 357 irs526 24 27 25444 90.10 689/816 390 679/806 385 irs713 54 42 39159 53.99 1025/3444 675 1056/3290 678 irs820 23 24 19747 88.40 906/984 419 886/964 409 irs953 45 29 30825 93.00 2016/2312 820 2001/2292 815 irs1196 32 31 42857 80.84 3080/6196 1481 3077/6190 1481 irs1488 14 25 25513 94.23 1858/1924 846 1858/1924 846 (b) =200 F3 GL1 GL2 circuit inp out tests f.c. det/flts eff.tsts det/flts eff.tsts add6 12 7 19118 92.61 491/498 331 3332/4392 1820 alu2 10 8 17943 79.55 260/260 161 564/584 388 alu3 10 8 17490 78.68 282/282 177 568/572 398 mish 94 34 43762 95.68 280/280 237 327/328 270 rckl 32 7 35820 90.01 476/476 250 2036/3792 943 vg2 25 8 31874 91.01 485/492 294 1324/1608 797 x1dn 27 6 33695 92.31 432/440 308 1508/1928 1031 x9dn 27 7 33864 93.39 593/612 324 1887/2276 1068 irs510 25 13 25510 94.15 713/738 372 713/738 372 irs526 24 27 49850 89.29 695/816 393 685/806 388 irs713 54 42 76883 53.78 1105/3444 725 1138/3290 729 irs820 23 24 38589 87.57 916/984 431 896/964 421 irs953 45 29 60471 92.11 2053/2312 847 2038/2292 842 irs1196 32 31 84333 80.23 3173/6196 1558 3170/6190 1558 irs1488 14 25 48829 91.82 1868/1924 858 1868/1924 858 siderably smaller than the number of all path delay faults in large circuits, as long as is kept small enough. 5. Concluding remarks We considered the modeling of delay faults in combinational circuits at the functional level. We defined a functional fault model that requires function-robust propagation of transitions of every type from every input to every output. When is set very high, this model results in a test set that detects all path delay faults in any gate-level implementation. However, the resulting test set is very large. Smaller values of allow high-quality test sets to be generated, that include smaller numbers of tests. We described a functional test generation procedure based on the proposed model. We demonstrated the validity of this functional approach by applying the test sets it generates to gate-level path delay faults. As for the selection of an appropriate value of, we offer the following suggestion. Procedure 4 should be run in a loop with increasing values of, to generate increasingly large test sets. If a gate-level description is not given, the procedure can be terminated when a limit on run time or test set size is reached. If a gate-level description is given, the procedure can be repeated until the gate-level fault coverage saturates. References [1] G. L. Smith, "Model for Delay Faults Based Upon Paths," 1985 Intl. Test Conf., pp. 342-349. [2] M. Abramovici, M. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990. [3] B. Underwood, W.-O. Law, S. Kang and H. Konuk, "Fastpath: A Path-Delay Test Generator for Standard Scan Designs", in Proc. 1994 Intl. Test Conf., Oct. 1994, pp. 154-163. [4] I. Pomeranz and S. M. Reddy, "On Testing Delay Faults In Macro-Based Combinational Circuits", 1994 Intl. Conf. on Computer-Aided Design, Nov. 1994, pp. 332-339. [5] W. Ke and P. R. Menon, "Synthesis of Delay-Verifiable Combinational Circuits", IEEE Trans. on Computers, Feb. 1995, pp. 213-222, [6] R. K. Brayton, R. Rudell, A. L. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A multiple-level logic optimization system," IEEE Trans. Computer-Aided Design, Nov. 1987, pp. 1062-1081. [7] R. Brayton, G. D. Hachtel, C. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, MA, 1984. [8] S. Patil, "Automatic Test Pattern Generation for Delay Faults in Logic Circuits," M.S. Thesis, ECE Dept., U. of Iowa, May 1987. Table 9: Results using pure random patterns pure random determ [8] functional circuit det/flts eff.tsts last.eff det/flts det/flts eff.tsts Z9sym 533/644 451 65505 644/644 644/644 644 add6 405/498 270 16299 495/498 491/498 331 adr4 207/210 145 7669 210/210 210/210 132 alu1 76/76 47 451 76/76 76/76 63 alu2 230/260 178 24878 260/260 260/260 161 alu3 254/282 190 30592 282/282 282/282 177 co14 44/144 16 29911 144/144 144/144 144 dk17 254/340 125 32745 340/340 340/340 108 dk27 114/128 58 7657 128/128 128/128 37 dk48 267/572 62 65276 572/572 572/572 88 mish 280/280 147 18329 280/280 280/280 237 radd 170/170 112 7873 170/170 170/170 100 rckl 68/476 46 1787 476/476 476/476 250 rd53 154/154 106 2402 154/154 154/154 98 vg2 325/492 218 65089 492/492 485/492 294 x1dn 283/440 184 65207 440/440 432/440 308 x9dn 329/612 227 62764 605/612 593/612 324 z4 190/190 131 10367 190/190 190/190 128 irs510 722/738 474 64735 729/738 713/738 372 irs526 505/816 239 7994 695/816 695/816 393 irs713 979/3444 480 32720 1938/3444 1105/3444 725 irs820 795/984 489 62522 980/984 916/984 431 irs953 1563/2312 648 64145 2302/2312 2053/2312 847 irs1196 799/6196 336 2038 3580/6196 3173/6196 1558 irs1488 1609/1924 806 32388 1875/1924 1868/1924 858