Slide Set 5. for ENCM 369 Winter 2018 Section 01. Steve Norman, PhD, PEng

Slide Set 5 for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary February 2018

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 2/71 Contents A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 3/71 Outline of Slide Set 5 A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 4/71 A Few Remarks about Chapter 6 Material The next two slides have a few comments about material in Chapter 6 of the main course textbook, specifically... remarks on assembly language programming remarks on Sections 6.7 and 6.8

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 5/71 Concluding remarks about assembly language programming Humans are usually much more productive writing code in high-level languages. (But some people thinking writing A.L. code is fun. Really.) Today the main use of A.L. is as an intermediate format in automatic translation of high-level language code A.L. is the output of a compiler and the input to an assembler. Students learn A.L. primarily because it helps them learn how computer systems work.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 6/71 Textbook Sections 6.7 and 6.8 6.7.1: Pseudoinstructions. We ve already covered this. 6.7.2: Exceptions. We ll look at this topic in detail later in the course. 6.7.3: Signed and unsigned instructions. We ll learn about these as we progress through this slide set. 6.7.4: Floating-point instructions. We ll look at MIPS floating-point instructions near the end of the course, after we cover floating-point number formats.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 7/71 6.8: x86 architecture. This is interesting, but won t be tested on midterm #2 or the final exam. Note also that the 64-bit x86-64 architecture (called AMD64 in the textbook) is significantly different from the 32-bit x86 architecture described in the textbook, and that x86-64 has been, for the last several years, the leading architecture for laptops, desktops, and servers. x86-64 is the instruction set architecture supported by current and important Intel processor chip series such as Core i5, Core i7, and Xeon.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 8/71 Outline of Slide Set 5 A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 9/71 Bit Patterns, Signed and Unsigned Integers Really important definitions: signed and unsigned integer types. Signed: a type with negative, zero, and positive values. Signed does NOT mean negative, it means might be negative. Do NOT say 5 is signed but +5 is unsigned. Both can be numbers in a signed number system. Unsigned: a type with zero and positive values only.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 10/71 Questions about an example 32-bit pattern 10001111101010000000000000001000 Question 1: Is this bit pattern signed or unsigned? Question 2: Why does it not make sense to ask Question 1?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 11/71 n-bit patterns Let s use b n 1, b n 2,..., b 2, b 1, b 0 as names for the bits in an n-bit pattern... bit number: b n 1 n 1 b n 2 b 2 b 1 b 0 n 2 2 1 0 The bits at the ends, b n 1 and b 0, have special names. What are those names? If n-bit patterns are used to encode numbers, how many different numbers can be encoded?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 12/71 Two s complement systems Some of this material is review from ENEL 353 please make sure you know all the two s complement stuff from that course. Some of this material was not taught in ENEL 353. Two s complement is by far the most common system used in computers for signed integer representation. Other systems, such as sign-and-magnitude and one s complement are extremely rarely used in modern equipment.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 13/71 n-bit two s complement systems In an n-bit two s complement number system, the number represented by an n-bit pattern is b n 1 2 n 1 + b n 2 2 n 2 + b n 3 2 n 3 +... + b 2 2 2 + b 1 2 1 + b 0 2 0 The above two s-complement representation formula was not taught in ENEL 353, but it is very handy to know. Example with n = 8: What number does the bit pattern 1100_0011 represent as a two s complement integer?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 14/71 Two s complement in MIPS n = 32: 32-bit two s complement is used for the C int type we have used that a lot in Labs 2 4. n = 16: 16-bit two s complement is important it s used in offsets in machine code for lw, sw, beq, bne, and other instructions, and used for constants in machine code for addi and slti. n = 8: Arrays of 8-bit two s-complement integers are supported by the lb instruction more about that later.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 15/71 n-bit unsigned integer systems Review: Two s complement representation formula... b n 1 2 n 1 + b n 2 2 n 2 + b n 3 2 n 3 +... + b 2 2 2 + b 1 2 1 + b 0 2 0 In an n-bit unsigned integer system, the number represented by an n-bit pattern is b n 1 2 n 1 + b n 2 2 n 2 + b n 3 2 n 3 +... + b 2 2 2 + b 1 2 1 + b 0 2 0 The difference between formulas is just a single sign. Example: What number does the bit pattern 1100_0011 represent as an unsigned integer?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 16/71 The sum of some powers of two Formula for a finite series where terms are 2 i... Proof: k 1 2 i = 2 k 1 i=0 k 1 2 i = 1 + 2 + 4 + + 2 k 2 + 2 k 1 i=0 = (2 1)(1 + 2 + 4 + + 2 k 2 + 2 k 1 ) = (2 + 4 + 8 + + 2 k 1 + 2 k ) (1 + 2 + 4 + + 2 k 2 + 2 k 1 ) = 2 k 1

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 17/71 The sum of some powers of two, continued Formula from previous slide: k 1 2 i = 2 k 1 i=0 Another way to understand this: a = k 1 i=0 2i is one less than b, where unsigned binary representations of a and b are a = 111 111 k 1 s and b = k +1 bits 1 000 000. k 0 s So what does the n-bit pattern 111 111 represent in an n-bit two s-complement system?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 18/71 Ranges of two s complement and unsigned integer types What is the greatest value in an n-bit two s complement system? What is the least value in an n-bit two s complement system? What is the smallest value in an n-bit unsigned system? (Not a hard question, I hope!) What is the largest value in an n-bit unsigned system?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 19/71 32-bit patterns, interpreted as unsigned and signed integers 32-bit hexadecimal unsigned signed pattern rep. interpretation interp. 0000 0000 0x00000000 0 0 0000 0001 0x00000001 1 1.... 0111 1110 0x7ffffffe 2 31 2 = 2,147,483,646 2 31 2 0111 1111 0x7fffffff 2 31 1 = 2,147,483,647 2 31 1 1000 0000 0x80000000 2 31 = 2,147,483,648 2 31 1000 0001 0x80000001 2 31 +1 = 2,147,483,649 2 31 +1.... 1111 1110 0xfffffffe 2 32 2 = 4,294,967,294 2 1111 1111 0xffffffff 2 32 1 = 4,294,967,295 1

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 20/71 Example of MIPS instruction support for unsigned integers: sltu Suppose $s0 contains 0xffff_ffff and $s1 contains 0x0000_0001, and these two instructions are run: slt $t0, $s0, $s1 sltu $t1, $s0, $s1 What values do $t0 and $t1 get? ATTENTION: Later on we ll see that the differences between add/addu, addi/addiu, and sub/subu are not so simple and obvious!

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 21/71 4 Key Facts About Two s Complement Fact 1 is about the sign bit. Fact 2 is about how to negate a number. Fact 3 has to do with sign extension. Fact 4 is about digital circuits for integer addition and subtraction.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 22/71 Two s Complement Fact 1: The MSB is the Sign Bit It s easy to test whether a two s complement integer is negative. If the MSB is 0, the number is 0, so, zero or positive. If the MSB is 1, the number is < 0, so, negative. Remark: It s best to consider zero to be neither positive nor negative.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 23/71 Two s Complement Fact 2: How to Negate a Number Given the bit pattern for a number X, what is the bit pattern for X? The rule is: Invert the bits of X, then do what? (This is review from ENEL 353.) This works for all values of X, positive, zero, or negative, in an n-bit two s complement system, except for one X which X? Let s do some examples with n = 8... Suppose x is an int in $s0 and y is an int in $s1, and we need MIPS A.L. for y = -x; Let s solve this two different ways, with nor and with sub.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 24/71 Two s Complement Fact 3: Sign Extension Sign extension means converting a relatively narrow representation of a number to a relatively wide representation of that same number. Suppose m > n. Given an n-bit two s complement representation of an integer, what is the m-bit representation of that integer? Let s do examples with n = 8 and m = 16. Proof that the method always works: It s obvious if the MSB of the n-bit number is 0... we re just inserting m n leading zeros. If the MSB of the n-bit number is 1, see the algebra on the next slide.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 25/71 All we need to show is that the formula is correct for widening by one bit (for example from 1101_0110 to 1_1101_0110); if that works we can get from n bits to m bits by repeatedly widening by one bit. Let our n-bit negative number be 1 2 n 1 + b n 2 2 n 2 + b n 3 2 n 3 + + b 0 2 0. Then the (n+1) -bit number we get from the sign-extension formula is 1 2 n + 1 2 n 1 + b n 2 2 n 2 + b n 3 2 n 3 + + b 0 2 0. Subtract the (n+1)-bit number from the n-bit number; all the terms with b i cancel, so the difference is 1 2 n 1 ( 1 2 n + 1 2 n 1 ) = 2 n 2 2 n 1 = 0.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 26/71 Remarks on the proof that sign extension works You won t be tested on this proof, but I hope you agree that it s nice to know that the proof exists. Algebra can be used to carefully prove all of the other important facts about two s-complement representation and arithmetic, but to go through all the proofs would really slow down progress in this course.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 27/71 Example of sign-extension with lb // Add up values from an array // of signed bytes... int sum_sb(signed char *a, int n) { int i, sum; sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; } What is the MIPS assembly language for sum += a[i];? (Assume that i is $t8, sum is $t9.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 28/71 Outline of Slide Set 5 A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 29/71 Addition of Unsigned and Signed Integers Section 5.2.1 in the textbook is very good on the organization of adder circuits. Let s start with the 1-bit full adder. (Note: A half adder is a full adder without a carry-in input.) a b carry out + carry in sum The 1-bit full adder is a combinational logic circuit let s write out its truth table.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 30/71 Combining n 1-bit adders to make an n-bit adder Let s sketch out how to put together some 1-bit adders to make an adder that can add two n-bit numbers. The circuit we ve just sketched is called a ripple-carry adder, because carry signals ripple from right to left. A ripple-carry adder is simple but is slower than some more sophisticated adder designs.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 31/71 An n-bit ripple-carry adder is slow because its overall t pd (combinational logic propagation delay) is approximately n times the t pd from carry-in to carry-out of a 1-bit full adder. Later in ENCM 369, if time permits, we might look at faster adder designs, such as carry-lookahead adders and prefix adders. (Prediction: Time will not permit a look at faster adder designs.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 32/71 n-bit addition example Let s do an example with an 8-bit adder: Add a = 00010001 two (which is 17 ten ) and b = 00010010 two (which is 18 ten ). bit number carry in a b sum 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 33/71 Two s Complement Fact 4: About integer addition hardware An n-bit adder, which seems to be designed to add unsigned integers, will also generate correct results when bit patterns are interpreted as two s-complement signed integers. We re not going to prove this fact mathematically, just demonstrate it in a couple of ways. First, let s add two example 8-bit patterns. Then, let s show how a MIPS addi instruction works when its constant operand is negative.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 34/71 Two s Complement Fact 4: An integer adder is just an adder This circuit is NOT specialized for signed or unsigned arithmetic: a n 1 b n 1 a n 2 b n 2 a 1 b 1 a 0 b 0 n-bit integer adder carry in to LSB carry out from MSB sum n 1 sum n 2 sum 1 sum 0 There is NO control input to tell the circuit what the types of the input and output n-bit patterms are!

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 35/71 Remarks related to Fact 4 Fact 4 is an important reason why two s-complement systems are used so widely for signed integers one simple piece of hardware can do both signed and unsigned addition. (That s NOT true for other kinds of signed number systems, such as sign-and-magnitude.) We ll see later on that a small enhancement to an n-bit adder will allow it to do both signed and unsigned subtraction.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 36/71 Out-of-range results in signed addition Any n-bit number system has a finite set of values. Within this set there are many pairs of numbers whose sums are NOT in the set. For example, in an 8-bit signed integer system the set of values is { 128, 127,..., +126, +127}. Think about adding 66 and 80. The sum, in ordinary math, is 146, which is not part of the 8-bit signed integer system. What will an 8-bit adder do with 66 and 80 as inputs?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 37/71 More examples of signed overflow in addition Let s look at trying to add 126 and 127 with an 8-bit adder. Let s build an executable for this C code on a typical system with a 32-bit int type: #include <stdio.h> int main(void) { int x = 1000000000; /* 1 billion */ int y = 2000000000; /* 2 billion */ printf("sum is %d.\n", x + y); return 0; } What will the output be?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 38/71 The word typical on the previous slide is important. Standards for C and C++ say that the effect of signed overflow is undefined behaviour. So a standard-compliant toolchain for C would be allowed to have the program output anything at all! I ve checked the program with current C toolchains for x86-64 on Linux, Mac OS X, and Windows. The result was always the same it was what you would expect from signed overflow in 32-bit two s-complement addition. But don t count on that being true for every standard-compliant C toolchain.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 39/71 Two ways to detect signed overflow in addition Method One: Signed overflow in a + b has happened if and only if the sign bits of a and b are the same but are different from the sign bit of the sum. Let s put this in tabular form. Method One, stated another way: Signed overflow has happened if and only if the sign bit of the sum is obviously wrong. Method Two: Signed overflow has happened if and only if the carry in to the MSB of the adder is different from the carry out of the MSB.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 40/71 MIPS add and addu instructions Both instructions add two GPR values and use a 32-bit adder to produce a 32-bit result. The adder DOES NOT do different things depending on whether the instruction is add or addu! a n 1 b n 1 a n 2 b n 2 a 1 b 1 a 0 b 0 n-bit integer adder carry in to LSB carry out from MSB sum n 1 sum n 2 sum 1 sum 0 So the difference is NOT LIKE the difference between slt, which is always correct for comparison of two signed integers, and sltu, which is always correct for comparison of two unsigned integers.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 41/71 add and addu: What s the difference? addu always copies the 32-bit result to the destination GPR, even if the result is wrong according to normal, everyday math. add checks for signed overflow wrong result, interpreting both source GPRs and the result as signed. If add detects signed overflow, there is no update to the destination GPR. Instead, there is an exception the program that tried the add is suspended, and the operating system kernel takes over. If signed overflow is not detected in add, the destination GPR gets exactly the same value it would have been given by addu!

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 42/71 MIPS addi and addiu instructions In both cases, the constant built in to the instruction is assumed to be signed, and is widened to 32 bits using sign extension. That 32-bit value is added to the source GPR value. After that, addiu is like addu, and addi is like add. Example: $s0 and $s1 both start with 0x8000_0000, and then the processor runs addiu $s0, $s0, -1 addi $s1, $s1, -1 What are the effects of these instructions?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 43/71 What does u mean at the end of a MIPS instruction mnemonic? It s a mistake to think that it always means unsigned! trailing u means interpret bit patterns as unsigned integers sltu sltiu lbu lhu multu divu (and various others... ) trailing u means DON T cause exceptions when signed overflow is detected addu addiu subu

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 44/71 Out-of-range results in unsigned addition From several slides back: Any n-bit number system has a finite set of values. Within this set there are many pairs of numbers whose sums are NOT in the set. Let s do an example with an 8-bit unsigned integer system, for which the set of values is {0, 1, 2,..., 254, 255}.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 45/71 Unsigned overflow and signed overflow are NOT the same thing! Unsigned overflow in addition is an event in which an n-bit adder produces a wrong result (in the sense of ordinary math), when all three numbers two inputs and the sum are interpreted as unsigned. That s NOT the same as signed overflow in addition signed overflow is an event in which an n-bit adder produces a wrong result (in the sense of ordinary math), when all three numbers two inputs and the sum are interpreted as signed.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 46/71 Two ways to detect unsigned overflow in addition Suppose that the n-bit pattern sum is the result of adding a and b with an n-bit adder. 1. Unsigned overflow has occurred if and only if, interpreting numbers as unsigned, sum < a. (If this is true, sum < b will also be true.) 2. Unsigned overflow has occurred if and only if the carry out from the MSB of the adder is 1. (Note that this method can t be used if hardware does not make that carry bit available!)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 47/71 Unsigned overflow and MIPS instructions Remember, add and addi cause exceptions in the case of signed overflow. Are there instructions that cause exceptions in the case of unsigned overflow in addition? No, there are not. Why was MIPS designed that way? I don t know, but here s a guess... At the time the MIPS instruction set was designed, perhaps there was a market advantage for processors which would check all integer additions (and subtractions) for signed overflow, but no such market advantage for checks for unsigned overflow.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 48/71 Warnings about overflow terminology (1) Versions of ENCM 369 in Winter 2013 and earlier did not use the terms signed overflow and unsigned overflow. Here are translations to older terms, which are be important to know about if you look at old midterms and final exams... 2014 and beyond 2013 and earlier signed overflow overflow unsigned overflow wraparound Note that Winter 2018 ENCM 369 terminology is the same as Fall 2013 Fall 2017 ENEL 353 terminology. The word wraparound is related the idea of an odometer wrapping around from 999,999 km to 000,000 km, or a 24-hour clock wrapping around from 23:59 to 00:00.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 49/71 Warnings about overflow terminology (2) Unfortunately, literature on computer systems is not always very precise with the use of the word overflow. It s sometimes suggested that overflow is a single, simple concept, but that s just not true. Here are some things to watch out for: Often the word overflow by itself is used to mean signed overflow. Details of overflow in floating-point computation we ll cover floating-point later in the course are quite different from details of overflow in integer computation.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 50/71 Outline of Slide Set 5 A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 51/71 Subtraction of Unsigned and Signed Integers a b = a + ( b). Can we use this simple idea to turn an adder into a subtractor? b can be generated by inverting all bits of b and adding 1 (Fact 2 about two s complement). We can get the bit inversion with inverters, and add 1 by setting the carry in to the LSB to 1. Note: We would like the adder to remain capable of computing a + b; to do this we will use multiplexers.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 52/71 The 2:1 multiplexer As we saw in ENEL 353, a 2:1 multiplexer ( mux for short) has two data inputs and a third select input: A B 0 1 S Y Y = { A if S = 0 B if S = 1 The mux can be thought of as a switch controlled by S: A B S =0 S =1 Y But of course electronic circuits don t really have moving parts! See textbook Section 2.8.1 to see how to make muxes out of logic gates.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 53/71 The 2:1 multiplexer, continued Usual symbol for a 2:1 mux, used in this year s textbook: A B 0 1 S Symbol used for a 2:1 mux in ENCM 369 textbook in 2013 and before: Y 2:1 mux truth table: S A B Y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 A 0 B 1 S Y Muxes of various dimensions are important components of processor designs in textbook Chapter 7.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 54/71 n-bit integer adder, enhanced to support subtraction a n 1 b n 1 a n 2 b n 2 a 1 b 1 a 0 b 0... + +... + + result n 1 0 1 0 1 0 1 0 1 result n 2 result 1 result 0 mux select input: 0 for addition, 1 for subtraction carry in to LSB: 0 for addition, 1 for subtraction The above circuit uses a ripple-carry adder, but other kinds of integer adder can also be used to make a subtractor. See Sections 5.2.2 and 5.2.4 for the textbook for more details.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 55/71 More about the n-bit integer adder/subtractor It s a fact although we won t prove it that this circuit subtracts correctly both when a, b, and the result are all interpreted as signed, and also when they re all interpreted as unsigned. Let s demonstrate this by computing a b, with n = 8, a = 1111_0000 two, and b = 0000_0101 two. So, like integer adders, integer subtractors are not specialized for signed or unsigned computation.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 56/71 Signed overflow and unsigned overflow in integer subtraction These terms have already been defined for addition... signed overflow: an event in which an n-bit adder produces a wrong result (in the sense of ordinary math), when all three numbers two inputs and the sum are interpreted as signed. unsigned overflow: an event in which an n-bit adder produces a wrong result (in the sense of ordinary math), when all three numbers two inputs and the sum are interpreted as unsigned. These definitions make sense for subtraction as well.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 57/71 Signed overflow in subtraction Example: With 8-bit signed integers, let s try to compute 120 ten 10 ten... Signed overflow in integer subtraction can happen in only two situations: negative number positive number appears to be 0 positive or zero negative number appears to be < 0 In both cases, the sign bit of the result is obviously wrong.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 58/71 Unsigned overflow in subtraction Example: With 8-bit unsigned integers, let s try to compute 17 ten 22 ten... Detection of unsigned overflow: When a b is computed and a, b and the result are all interpreted as unsigned, overflow has occurred if and only if the result appears to be > a. Another way to detect unsigned overflow: In an adder/subtractor circuit like that on slide 54, unsigned overflow has occurred if and only if the carry out of the most significant bit of the adders is 0. (That may be surprising, but it s true.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 59/71 MIPS sub and subu instructions subu: Generate 32-bit subtraction result, copy it to destination GPR even if result is wrong. sub: Generate 32-bit subtraction result, and check for signed overflow (not unsigned overflow). If there was no signed overflow, copy result to destination GPR; on signed overflow, do not update destination GPR and instead cause an exception. This behaviour matches the behaviour of addu vs. add and addiu vs. addi.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 60/71 Subtle, confusing, but important details about MIPS instruction names It is best to think of the u at the end of addu, addiu, and subu as standing for unchecked, NOT unsigned. On the other hand, the u really does mean unsigned in sltu, sltiu, lbu, multu, divu, and just about any other MIPS instruction with a name ending in u.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 61/71 Review: What does u mean at the end of a MIPS instruction mnemonic? It s a mistake to think that it always means unsigned. trailing u means interpret bit patterns as unsigned integers sltu sltiu lbu lhu multu divu (and various others... ) trailing u means DON T cause exceptions when signed overflow is detected addu addiu subu

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 62/71 Review of MIPS integer addition and subtraction instructions: examples $s0 = 0xd800_0000, $s1 = 0xe000_0000. What is the effect of addu $t0, $s0, $s1? Is there any difference if the instruction is changed from addu to add? $s2 = 0x9000_0000, $s3 = 0x2fff_ffff. What is the effect of subu $t1, $s2, $s3? Is there any difference if the instruction is changed from subu to sub?

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 63/71 Outline of Slide Set 5 A Few Remarks about Chapter 6 Material Bit Patterns and Integers Addition of Unsigned and Signed Integers Subtraction of Unsigned and Signed Integers Instructions used by C and C++ compilers for integer addition and subtraction

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 64/71 Instructions used by C and C++ compilers for integer addition and subtraction First, notes about name of C and C++ integer types... unsigned by itself means exactly the same thing as unsigned int: unsigned w; unsigned int x; // x has the same type as w. Plain int and signed int mean exactly the same thing: int y; signed int z; // z has the same type as y. (But you won t often see code that spells out the type as signed int.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 65/71 Addition and subtraction instructions for signed and unsigned arithmetic in C and C++ unsigned u_foo(unsigned a, unsigned b) { return a + 127u - b; } int s_foo(int c, int d) { return c + 127 - d; } What instructions will a typical MIPS C compiler choose for the above two functions? (Reminder: typical is important here.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 66/71 In fact, typical C and C++ compilers for MIPS never use add, addi, or sub! For all addition and subtraction with plain int and unsigned int types, a typical compiler will choose addu, addiu, or subu. For addition and subtraction with pointers, a compiler will use addu, addiu, or subu, along with appropriate adjustments for array element size. (Example: If $s0 is allocated for p, of type int*, the compiler translates p-- as addiu $s0, $s0, -4.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 67/71 So why has ENCM 369 used add, addi, and sub in lectures, tutorials, and Labs 2 5? We have followed what Chapter 6 of your textbook does. The big picture questions in Chapter 6 are What s an instruction? and How can instructions be organized to create procedures? Exact details of addition and subtraction with numbers of large magnitudes would draw attention away from the big picture questions.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 68/71 Why don t C and C++ compilers use add, addi, or sub, or equivalents? For arithmetic with unsigned ints and pointers, it would simply be wrong. For signed arithmetic, instructions like MIPS add, addi, and sub don t exist in most ISA s. (For example, ARM, x86 and x86-64 all have integer add and subtract instructions that work like MIPS addu, not like MIPS add.) Checking for signed overflow after each int addition or subtraction would make programs larger and slower. MIPS compilers give coders the program behaviour they have come to expect from compilers for other platforms.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 69/71 x86-64 instructions for u_foo and s_foo Code from an earlier slide: unsigned u_foo(unsigned a, unsigned b) { return a + 127u - b; } int s_foo(int c, int d) { return c + 127 - d; } Let s see what gcc does with this for the x86-64 architecture.

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 70/71 x86-64 instructions for u_foo and s_foo MACHINE CODE (HEX BYTES) EXPLANATION u_foo: 8d 47 7f r.v. = arg1 + 127 29 f0 r.v. = r.v. - arg2 c3 return s_foo: 8d 47 7f r.v. = arg1 + 127 29 f0 r.v. = r.v. - arg2 c3 return The result is two identical three-instruction sequences just what we saw for MIPS! (gcc version 4.4 used with -O2 optimization selected. Results may vary with other compiler versions.)

ENCM 369 Winter 2018 Section 01 Slide Set 5 slide 71/71 Attention! C and C++ do NOT help coders or users know when values of integers get out of hand! (This is also true for Java.) #include <stdio.h> int main(void) { int balance = 2000000000; // $20M in cents int deposit = 1000000000; // $10M in cents balance += deposit; printf("updated balance: %d cents.\n", balance); return 0; } Output produced on a typical platform with a 32-bit int type... Updated balance: -1294967296 cents.