Wafer Fab process Assembly Process Product Marking Design

Customer Information Notification 201206035I Issue Date: 26-Aug-2012 Effective Date: 27-Aug-2012 Dear Product Data, Here s your personalized quality information concerning products Mouser Electronics purchased from NXP. For detailed information we invite you to view this notification online Management Summary LPC23xx/24xx Errata Sheet Update Change Category Wafer Fab process Assembly Process Product Marking Design Wafer Fab materials Assembly Materials Electrical spec./test coverage Mechanical Specification Wafer Fab location Assembly Location Test Location Packing/Shipping/Labeling LPC23xx/24xx Errata Sheet Update Information Notification LPC23xx/24xx Errata Sheet Update. - The VBAT errata (The VBAT pin cannot be left floating) was updated in the LPC23xx/24xx errata sheets. Why do we issue this Information Notification - To notify customers that the LPC23xx/LPC24xx errata sheets were updated with a functional problem that affects a specific application setup and its mitigation. - Please see the attached LPC23xx/24xx errata sheets for further details. Identification of Affected Products - All the LPC23xx (rev D) and LPC24xx (rev C, D) products. - Rev C or D is visible on Line C of the product top side marking.

Impact The issue as described in the errata sheet will only affect the applications that have the VBAT pin floating. If the VBAT pin is connected to a battery or a supply, there will be no issues. Data Sheet Revision No impact to existing datasheet Disposition of Old Products Not applicable Related Notifications Notification Issue Date Effective DateTitle 200906007F 08-Jun- 2009 Microcontroller products LPC23xx and LPC24xx will be sourced from the new product version Rev. "D" Additional information Additional documents: view online Contact and Support For all inquiries regarding the epcn tool application or access issues, please contact NXP "Global Quality Support Team". For all Quality Notification content inquiries, please contact your local NXP Sales Support team. For specific questions on this notice or the products affected please contact our specialist directly: Name Position e-mail address Emile Busink QA engineering MCU emile.busink@nxp.com At NXP Semiconductors we are constantly striving to improve our product and processes to ensure they reach the highest possible Quality Standards. Customer Focus, Passion to Win. NXP Quality Management Team. About NXP Semiconductors NXP Semiconductors N.V. (NASDAQ: NXPI) provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise. These innovations are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. A global semiconductor company with operations in more than 25 countries, NXP posted revenue of $4.4 billion in 2010. NXP Semiconductors High Tech Campus, 5656 AG Eindhoven, The Netherlands 2006-2010 NXP Semiconductors. All rights reserved.

ES_LPC2361 Errata sheet LPC2361 Rev. 8.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2361 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2361 Errata sheet LPC2361 Revision history Rev Date Description 8.1 20120701 Added Rev D to VBAT.2. Updated CAN.1. 8 20110601 Added USB.1. 7 20110420 Added Note.2. 6 20110301 Added ADC.1. 5 20100607 Removed Ethernet.1; device does not have Ethernet feature. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 3 20100122 Added VBAT.2 2 20090511 Added Rev D 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 2 of 12

ES_LPC2361 Errata sheet LPC2361 1. Product identification The LPC2361 devices typically have the following top-side marking: LPC2361xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2361: Table 1. Device revision table Revision identifier (R) B D Revision description First device revision Second device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational B, D Section 3.1 CAN.1 Data overrun condition can lock the CAN controller B Section 3.2 Core.1 Deep power-down.1 Incorrect update of the Abort Link register in Thumb state B, D Section 3.3 Deep power-down mode is not functional B Section 3.4 USB.1 USB host controller hangs on a dribble bit B, D Section 3.5 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device B Section 3.6 VBAT.2 The VBAT pin cannot be left floating B, D Section 3.7 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations n/a n/a n/a n/a ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 3 of 12

ES_LPC2361 Errata sheet LPC2361 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. B, D Section 5.1 Note.2 On the LPC2361 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 4 of 12

ES_LPC2361 Errata sheet LPC2361 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 5 of 12

ES_LPC2361 Errata sheet LPC2361 3.2 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 6 of 12

ES_LPC2361 Errata sheet LPC2361 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. 3.4 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 7 of 12

ES_LPC2361 Errata sheet LPC2361 3.5 USB.1: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 8 of 12

ES_LPC2361 Errata sheet LPC2361 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. 3.7 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 9 of 12

ES_LPC2361 Errata sheet LPC2361 4. AC/DC deviations detail 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2361 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 10 of 12

ES_LPC2361 Errata sheet LPC2361 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2361 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 11 of 12

ES_LPC2361 Errata sheet LPC2361 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 CAN.1: Data Overrun condition can lock the CAN controller.............................. 6............................6...............................6...........................6 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 7............................7...............................7 Conditions:.............................7...........................7 3.4 Deep power-down.1: Deep power-down mode is not functional.......................... 7............................7...............................7...........................7 3.5 USB.1: USB host controller hangs on a dribble bit................................... 8............................8...............................8...........................8 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 9............................9...............................9...........................9 3.7 VBAT.2: The VBAT pin cannot be left floating.. 9............................9...............................9...........................9 4 AC/DC deviations detail................. 10 4.1 n/a.................................. 10 5 Errata notes detail...................... 10 5.1 Note.1............................... 10 5.2 Note.2............................... 10 6 Legal information....................... 11 6.1 Definitions............................ 11 6.2 Disclaimers........................... 11 6.3 Trademarks........................... 11 7 Contents.............................. 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2361

ES_LPC2362 Errata sheet LPC2362 Rev. 7.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2362 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2362 Errata sheet LPC2362 Revision history Rev Date Description 7.1 20120701 Added Rev D to VBAT.2. Updated CAN.1. 7 20110601 Added USB.1. 6 20110420 Added Note.2. 5 20110301 Added ADC.1. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 3 20100122 Added VBAT.2 2 20090511 Added Rev D 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 2 of 12

ES_LPC2362 Errata sheet LPC2362 1. Product identification The LPC2362 devices typically have the following top-side marking: LPC2362xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2362: Table 1. Device revision table Revision identifier (R) B D Revision description First device revision Second device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational B, D Section 3.1 CAN.1 Data overrun condition can lock the CAN controller B Section 3.2 Core.1 Deep power-down.1 Ethernet.1 Incorrect update of the Abort Link register in Thumb state B, D Section 3.3 Deep power-down mode is not functional B Section 3.4 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent B, D Section 3.5 USB.1 USB host controller hangs on a dribble bit B, D Section 3.6 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device B Section 3.7 VBAT.2 The VBAT pin cannot be left floating B, D Section 3.8 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations n/a n/a n/a n/a ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 3 of 12

ES_LPC2362 Errata sheet LPC2362 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31 (configured as general purpose input pin(s)), current must be limited to less than 4 ma by using a series limiting resistor. B, D Section 5.1 Note.2 On the LPC2362 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 4 of 12

ES_LPC2362 Errata sheet LPC2362 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 5 of 12

ES_LPC2362 Errata sheet LPC2362 3.2 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 6 of 12

ES_LPC2362 Errata sheet LPC2362 In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. 3.4 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. 3.5 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 7 of 12

ES_LPC2362 Errata sheet LPC2362 3.6 USB.1: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 8 of 12

ES_LPC2362 Errata sheet LPC2362 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. 3.8 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 9 of 12

ES_LPC2362 Errata sheet LPC2362 4. AC/DC deviations detail 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin(s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2362 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 10 of 12

ES_LPC2362 Errata sheet LPC2362 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2362 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 11 of 12

ES_LPC2362 Errata sheet LPC2362 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 CAN.1: Data Overrun condition can lock the CAN controller.............................. 6............................6...............................6...........................6 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 6............................6...............................6 Conditions:.............................6...........................7 3.4 Deep power-down.1: Deep power-down mode is not functional.......................... 7............................7...............................7...........................7 3.5 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent.................................. 7............................7...............................7...........................7 3.6 USB.1: USB host controller hangs on a dribble bit................................... 8............................8...............................8...........................8 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 9............................9...............................9...........................9 3.8 VBAT.2: The VBAT pin cannot be left floating.. 9............................9...............................9...........................9 4 AC/DC deviations detail................. 10 4.1 n/a.................................. 10 5 Errata notes detail...................... 10 5.1 Note.1.............................. 10 5.2 Note.2.............................. 10 6 Legal information....................... 11 6.1 Definitions............................ 11 6.2 Disclaimers........................... 11 6.3 Trademarks........................... 11 7 Contents.............................. 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2362

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 Rev. 9.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2364, LPC2366, LPC2368 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 Revision history Rev Date Description 9.1 20120701 Combined ES_LPC2364, ES_LPC2366, and ES_LPC2368 into one document. Added Rev D to VBAT.2. Updated CAN.1. 9 20110420 Added Note.2. 8 20110301 Added ADC.1. 7 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.4 6 20100122 Added VBAT.2 5 20090512 Added Rev D 4 20080602 Added Errata Note.1 3 20080408 Added VBAT.1 2 20070921 Added Rev B Removed Rev A from ESD.1. ESD.1 does not appear in Rev A. It was accidentally listed in version 1.3 1 20070720 Added Ethernet.3 Added Deep Power Down Mode.1 Updated Flash.1 Updated Ethernet.1 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 2 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 1. Product identification 2. Errata overview The LPC2364/66/68 devices typically have the following top-side marking: LPC236Xxxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2364/66/68: Table 1. Device revision table Revision identifier (R) Revision description - Initial device revision A Second device revision B Third device revision D Fourth device revision Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 ADDRx read conflicts with hardware setting of DONE bit - Section 3.1 ADC.2 External sync inputs not operational -, A, B, D Section 3.2 CAN.1 Data overrun condition can lock the CAN controller -, A, B Section 3.3 Core.1 Deep power-down.1 Incorrect update of the Abort Link register in Thumb state -, A, B, D Section 3.4 Deep power-down mode is not functional -, A, B Section 3.5 Ethernet.1 Setting up the Ethernet interface in RMII mode - Section 3.6 Ethernet.2 Ethernet SRAM disabled - Section 3.7 Ethernet.3 RxDescriptor number cannot be greater than 4 - Section 3.8 Ethernet.4 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent -, A, B, D Section 3.9 Flash.1 Operating speed out of on-chip flash is restricted -, A Section 3.10 I2S.1 I 2 S DMA can stall - Section 3.11 MAM.1 Code execution failure can occur with MAM Mode 2 -, A Section 3.12 PLL.1 PLL output is limited to 290 MHz - Section 3.13 SRAM.1 16 kb SRAM can not be used for code execution - Section 3.14 USB.1 USB_NEED_CLK is always asserted - Section 3.15 USB.2 U1CONNECT is not functional - Section 3.16 USB.3 V BUS status input is not functional - Section 3.17 ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 3 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 Table 2. Functional problems table continued Functional problems Short description Revision identifier Detailed description VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device -, A, B Section 3.18 VBAT.2 The VBAT pin cannot be left floating -, A, B, D Section 3.19 WDT.1 Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset - Section 3.20 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations ESD.1 2 kv ESD requirements are not met on the RTCX1 pin - Section 4.1 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. -, A, B, D Section 5.1 Note.2 On the LPC2364/66/68 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 4 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3. Functional problems detail 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit The LPC2364/66/68 has a 10-bit ADC, which can be used to measure analog signals and convert the signals into a 10-bit digital result. There are eight A/D channels and each channel has its own individual A/D Data Register (ADDR0 to ADDR7). The A/D Data Register holds the result when an A/D conversion is complete, and also includes the flags that indicate when a conversion has been completed (DONE bit) and when a conversion overrun has occurred. The DONE bit is cleared when the respective A/D Data Register is read. If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the same register (once a conversion is completed) then the DONE bit gets cleared automatically, thereby clearing the indication that a conversion was completed. For software controlled mode or burst mode with only one channel selected, the DONE bit in the A/D Global Data Register (located at 0xE003 4004) can be used instead of the individual ADDRx result register with no impact on performance. For burst mode with multiple channels selected, the DONE bit together with the CHN field in the A/D Global Data Register can be used with some impact on throughput. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 5 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.2 ADC.2: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 6 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.3 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 7 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 8 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.5 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. 3.6 Ethernet.1: Setting up the Ethernet interface in RMII mode The LPC2364/66/68 has an Ethernet interface, which can be interfaced with an off-chip PHY using the RMII interface. The default configuration of the device does not enable the RMII interface. To use the Ethernet interface in RMII mode write a 1 to bit 12 (P1.16) in PINSEL2 register (located at 0xE002 C008). This workaround only applies for Rev - devices and does not apply for Rev A and newer devices. In order to have both Rev - and other revisions coexist in the same piece of software, the MAC module ID can be used to identify the part and determine if port pin P1.6 needs to be set or not. Here are the steps (along with some sample code) to initialize the MAC based on the module ID: 1. In master header file llpc24xx.h, make sure Module ID is defined (Please note, this ID register is not documented in the User's Manual). #define MAC_BASE_ADDR 0xFFE00000 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 2. In the beginning of the MAC initialization file, add below definition: #define OLD_EMAC_MODULE_ID 0x3902 << 16) 0x2000) 3. In MAC initialization routine, right after setting the EMAC clock in the PCONP register, add a few lines as below: /* Turn on the ethernet MAC clock in PCONP, bit 30 */ regval = PCONP; regval = PCONP_EMAC_CLOCK; PCONP = regval; /*------------------------------------------------------ * Write to PINSEL2/3 to select the PHY functions on P1[17:0] ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 9 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 * P1.6, ENET-TX_CLK, has to be set for Rev '-' devices and it * must not be set for Rev 'A and newer devices *------------------------------------------------------*/ regval = MAC_MODULEID; if ( regval == OLD_EMAC_MODULE_ID ) { /* On Rev. '-', MAC_MODULEID should be equal to OLD_EMAC_MODULE_ID, P1.6 should be set. */ PINSEL2 = 0x50151105; /* selects P1[0,1,4,6,8,9,10,14,15] */ } else { /* on rev. 'A', MAC_MODULEID should not equal to OLD_EMAC_MODULE_ID, P1.6 should not be set. */ PINSEL2 = 0x50150105; /* selects P1[0,1,4,8,9,10,14,15] */ } PINSEL3 = 0x00000005; /* selects P1[17:16] */ 3.7 Ethernet.2: Ethernet SRAM disabled The LPC2364/66/68 has an Ethernet interface, which has a dedicated 16 kb SRAM. When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the Ethernet SRAM is also disabled. Enable the Ethernet block by setting the PCENET bit (bit no. 30) in the PCONP register. The Ethernet SRAM is now enabled. 3.8 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4 The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the number of descriptors in the Descriptor array. Each receive descriptor element in the Descriptor array has an associated status field which consists of the HashCRC word and Status Information word. The status words are updated incorrectly if the number of Descriptors set in the Receive number of Descriptors register is greater than or equal to 5. Define 4 or less in the Receive number of Descriptors register. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 10 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.9 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 11 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.10 Flash.1: Operating speed out of on-chip flash is restricted The operating speed of this device out of internal flash/sram is specified at 72 MHz. Code execution from internal flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (do not use even values for CCLKSEL). 2. Rev - devices: Code execution from internal flash is restricted to a maximum of 60 MHz also. However, this device revision has one more restriction in terms of the PLL output frequency (F CCO - Please refer to PLL.1 above). F CCO is limited to 290 MHz. Considering the same example in PLL.1 (Input crystal-12 MHz, N = 1, M = 12): F CCO =288MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. 3.11 I2S.1: I 2 S DMA interface is non-operational The LPC2364/66/68 has an I 2 S interface, which can be used for audio devices. The I 2 S interface was initially designed to operate with the general purpose DMA controller. The DMA controller cannot access the I 2 S interface. No known workaround. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 12 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.12 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.13 PLL.1: PLL output (F CCO ) is limited to 290 MHz The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value N, which may be in the range of 1 to 256. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value M, in the range of 1 through 32768. The resulting frequency, F CCO must be in the range of 275 MHz to 550 MHz.This frequency can be divided down (using the Clock Divider registers) to get the desired clock frequencies for the core and peripherals. The maximum output of the CCO within the PLL block is limited to 290 MHz. Care should be taken while programming the PLL so that F CCO resides in the desired range. The suggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of 1 and PLL multiplier (M) of 12. Putting the values in the equation: F CCO = (2 M FIN) / N F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev - and Rev A, see Flash.1). ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 13 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.14 SRAM.1: 16 kb SRAM cannot be used for code execution The LPC2364/66/68 has 16 kb of SRAM on the AHB2 bus, which would generally be used by the Ethernet block. The 16 kb of SRAM can only be used as data RAM. Code can not be executed from this memory. No known workaround. 3.15 USB.1: USB_NEED_CLK is always asserted The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power Down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. The USB_NEED_CLK bit of the USBIntSt register (located at 0xE01F C1C0) is always asserted, preventing the chip from entering Power Down mode when the USBWAKE bit is set in the INTWAKE register (located at 0xE01F C144). After setting the PCUSB bit in PCONP (located at 0xE01F C0C4), write 0x1 to address 0xFFE0C008. The USB_NEED_CLK signal will now function correctly. Writing to address 0xFFE0C008 only needs to be done once after each chip reset. 3.16 USB.2: U1CONNECT signal is not functional U1CONNECT Signal (alternate function of P2.9) is part of the SoftConnect USB feature, which is used to switch an external 1.5 KW resistor under the software control. The USB U1CONNECT alternate function does not work as expected. Configure P2.9 as a GPIO pin, and use it to enable the pull-up resistor on the U1D+ pin. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 14 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.17 USB.3: V BUS status input is not functional The V BUS signal indicates the presence of USB bus power. The V BUS status input is not functional. Configure P1.30 as a GPIO pin, and poll it to determine when V BUS goes to 0, signalling a disconnect event. 3.18 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. 3.19 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 15 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.20 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset The Watchdog timer can reset the microcontroller within a reasonable amount of time if it enters an erroneous state. After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to WDFEED may cause an immediate reset. Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and the GPDMA should be disabled while feeding the Watchdog. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 16 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 4. AC/DC deviations detail 5. Errata notes detail 4.1 ESD.1: The LPC2364/66/68 does not meet the 2 kv ESD requirements on the RTCX1 pin The LPC2364/66/68 is rated for 2 kv ESD. The RTCX1 pin is the input pin for the RTC oscillator circuit. The LPC2364/66/68 does not meet the required 2 kv ESD specified. Observe proper ESD handling precautions for the RTCX1 pin. 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2364/66/68 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 17 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 18 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit................... 5............................5...............................5...........................5 3.2 ADC.2: External sync inputs not operational.. 6............................6...............................6...........................6 3.3 CAN.1: Data Overrun condition can lock the CAN controller............................. 7............................7...............................7...........................7 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 8............................8...............................8 Conditions:.............................8...........................8 3.5 Deep power-down.1: Deep power-down mode is not functional.......................... 9............................9...............................9...........................9 3.6 Ethernet.1: Setting up the Ethernet interface in RMII mode............................ 9............................9...............................9...........................9 3.7 Ethernet.2: Ethernet SRAM disabled....... 10...........................10..............................10..........................10 3.8 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4......................... 10...........................10..............................10..........................10 3.9 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent................................. 11...........................11..............................11.......................... 11 3.10 Flash.1: Operating speed out of on-chip flash is restricted............................ 12........................... 12.............................. 12.......................... 12 3.11 I2S.1: I 2 S DMA interface is non-operational. 12........................... 12.............................. 12.......................... 12 3.12 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail.. 13........................... 13.............................. 13.......................... 13 3.13 PLL.1: PLL output (F CCO ) is limited to 290 MHz............................. 13........................... 13.............................. 13.......................... 13 3.14 SRAM.1: 16 kb SRAM cannot be used for code execution............................ 14........................... 14.............................. 14.......................... 14 3.15 USB.1: USB_NEED_CLK is always asserted 14........................... 14.............................. 14.......................... 14 3.16 USB.2: U1CONNECT signal is not functional 14........................... 14.............................. 14.......................... 14 3.17 USB.3: V BUS status input is not functional... 15........................... 15.............................. 15.......................... 15 3.18 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device............... 15........................... 15.............................. 15.......................... 15 3.19 VBAT.2: The VBAT pin cannot be left floating 15........................... 15.............................. 15.......................... 15 continued >> ES_LPC2364_66_68 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 19 of 20

ES_LPC2364_66_68 Errata sheet LPC2364/66/68 3.20 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset................................ 16...........................16..............................16..........................16 4 AC/DC deviations detail................. 17 4.1 ESD.1: The LPC2364/66/68 does not meet the 2 kv ESD requirements on the RTCX1 pin.... 17...........................17..............................17..........................17 5 Errata notes detail...................... 17 5.1 Note.1............................... 17 5.2 Note.2............................... 17 6 Legal information....................... 18 6.1 Definitions............................ 18 6.2 Disclaimers........................... 18 6.3 Trademarks........................... 18 7 Contents.............................. 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2364_66_68

ES_LPC2365_67 Errata sheet LPC2365/67 Rev. 6.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2365, LPC2367 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2365_67 Errata sheet LPC2365/67 Revision history Rev Date Description 6.1 20120701 Added Rev D to VBAT.2. Combined ES_LPC2365 and ES_LPC2367 into one document. 6 20110420 Added Note.2. 5 20110301 Added ADC.1. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 3 20100122 Added VBAT.2 2 20090511 Added Rev D 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 2 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 1. Product identification The LPC2365/67 devices typically have the following top-side marking: LPC236Xxxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2365/67: Table 1. Device revision table Revision identifier (R) A B D Revision description Second device revision Third device revision Fourth device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational A, B, D Section 3.1 Core.1 Deep power-down.1 Ethernet.1 Incorrect update of the Abort Link register in Thumb state A, B, D Section 3.2 Deep power-down mode is not functional A, B Section 3.3 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent A, B, D Section 3.4 Flash.1 Operating speed out of on-chip flash is restricted A Section 3.5 MAM.1 Code execution failure can occur with MAM Mode 2 A Section 3.6 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device A, B Section 3.7 VBAT.2 The VBAT pin cannot be left floating A, B, D Section 3.8 Table 3. AC/DC deviations table AC/DC Short description Revision identifier Detailed description deviations n/a n/a n/a n/a ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 3 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. A, B, D Section 5.1 Note.2 On the LPC2365/67 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 4 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 5 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. 3.3 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 6 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. 3.5 Flash.1: Operating speed out of on-chip flash is restricted The operating speed of this device out of internal flash/sram is specified at 72 MHz. Code execution from internal flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (Do not use even values for CCLKSEL). Considering the example (Input crystal-12 MHz, N = 1, M = 12): F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 7 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 3.6 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 8 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 3.8 VBAT.2: The VBAT pin cannot be left floating 4. AC/DC deviations detail The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2365/67 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 9 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2365_67 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 10 of 11

ES_LPC2365_67 Errata sheet LPC2365/67 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 6............................6...............................6 Conditions:.............................6...........................6 3.3 Deep power-down.1: Deep power-down mode is not functional.......................... 6............................6...............................6...........................6 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent.................................. 7............................7...............................7...........................7 3.5 Flash.1: Operating speed out of on-chip flash is restricted.............................. 7............................7...............................7...........................7 3.6 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail... 8............................8...............................8...........................8 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 8............................8...............................8...........................8 3.8 VBAT.2: The VBAT pin cannot be left floating.. 9............................9...............................9...........................9 4 AC/DC deviations detail.................. 9 4.1 n/a................................... 9 5 Errata notes detail....................... 9 5.1 Note.1............................... 9 5.2 Note.2............................... 9 6 Legal information...................... 10 6.1 Definitions........................... 10 6.2 Disclaimers.......................... 10 6.3 Trademarks.......................... 10 7 Contents............................... 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2365_67

ES_LPC2377 Errata sheet LPC2377 Rev. 6.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2377 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2377 Errata sheet LPC2377 Revision history Rev Date Description 6.1 20120701 Added Rev D to VBAT.2. 6 20110420 Added Note.2. 5 20110301 Added ADC.1. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 3 20100122 Added VBAT.2 2 20090512 Added Rev D 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 2 of 11

ES_LPC2377 Errata sheet LPC2377 1. Product identification The LPC2377 devices typically have the following top-side marking: LPC2377xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2377: Table 1. Device revision table Revision identifier (R) A B D Revision description Second device revision Third device revision Fourth device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational A, B, D Section 3.1 Core.1 Deep power-down.1 Ethernet.1 Incorrect update of the Abort Link register in Thumb state A, B, D Section 3.2 Deep power-down mode is not functional A, B Section 3.3 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent A, B, D Section 3.4 Flash.1 Operating speed out of on-chip flash is restricted A Section 3.5 MAM.1 Code execution failure can occur with MAM Mode 2 A Section 3.6 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device A, B Section 3.7 VBAT.2 The VBAT pin cannot be left floating A, B, D Section 3.8 Table 3. AC/DC deviations table AC/DC Short description Revision identifier Detailed description deviations n/a n/a n/a n/a ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 3 of 11

ES_LPC2377 Errata sheet LPC2377 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. A, B, D Section 5.1 Note.2 On the LPC2377 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 4 of 11

ES_LPC2377 Errata sheet LPC2377 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 5 of 11

ES_LPC2377 Errata sheet LPC2377 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. 3.3 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 6 of 11

ES_LPC2377 Errata sheet LPC2377 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. 3.5 Flash.1: Operating speed out of on-chip flash is restricted The operating speed of this device out of internal flash/sram is specified at 72 MHz. Code execution from internal flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (Do not use even values for CCLKSEL). Considering the example (Input crystal-12 MHz, N = 1, M = 12): F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 7 of 11

ES_LPC2377 Errata sheet LPC2377 3.6 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 8 of 11

ES_LPC2377 Errata sheet LPC2377 3.8 VBAT.2: The VBAT pin cannot be left floating 4. AC/DC deviations detail The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2377 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 9 of 11

ES_LPC2377 Errata sheet LPC2377 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2377 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 10 of 11

ES_LPC2377 Errata sheet LPC2377 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 6............................6...............................6 Conditions:.............................6...........................6 3.3 Deep power-down.1: Deep power-down mode is not functional.......................... 6............................6...............................6...........................6 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent.................................. 7............................7...............................7...........................7 3.5 Flash.1: Operating speed out of on-chip flash is restricted.............................. 7............................7...............................7...........................7 3.6 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail... 8............................8...............................8...........................8 3.7 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 8............................8...............................8...........................8 3.8 VBAT.2: The VBAT pin cannot be left floating.. 9............................9...............................9...........................9 4 AC/DC deviations detail.................. 9 4.1 n/a................................... 9 5 Errata notes detail....................... 9 5.1 Note.1............................... 9 5.2 Note.2............................... 9 6 Legal information...................... 10 6.1 Definitions........................... 10 6.2 Disclaimers.......................... 10 6.3 Trademarks.......................... 10 7 Contents............................... 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2377

ES_LPC2378_88 Errata sheet LPC2378/88 Rev. 6.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2378, LPC2388 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2378_88 Errata sheet LPC2378/88 Revision history Rev Date Description 6.1 20120701 Combined ES_LPC2378 and ES_LPC2388 into one document. Added Rev D to VBAT.2. Updated CAN.1. Added USB.4 (LPC2388 only). 6 20110420 Added Note.2. 5 20110301 Added ADC.2. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.4 3 20100122 Added VBAT.2 2 20090512 Added Rev D 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 2 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 1. Product identification 2. Errata overview The LPC2378/88 devices typically have the following top-side marking: LPC23X8xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2378/88: Table 1. Device revision table Revision identifier (R) Revision description - Initial device revision A Second device revision B Third device revision D Fourth device revision Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 ADDRx read conflicts with hardware setting of DONE bit - Section 3.1 ADC.2 External sync inputs not operational -, A, B, D Section 3.2 CAN.1 Data overrun condition can lock the CAN controller -, A, B Section 3.3 Core.1 Deep power-down.1 EMC.1 Incorrect update of the Abort Link register in Thumb state -, A, B, D Section 3.4 Deep power-down mode is not functional -, A, B Section 3.5 Write operation cannot be performed on the external memory bus - Section 3.6 Ethernet.1 Setting up the Ethernet interface in RMII mode - Section 3.7 Ethernet.2 Ethernet SRAM disabled - Section 3.8 Ethernet.3 RxDescriptor number cannot be greater than 4 - Section 3.9 Ethernet.4 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent -, A, B, D Section 3.10 Flash.1 Operating speed out of on-chip flash is restricted -, A Section 3.11 I2S.1 I 2 S DMA can stall - Section 3.12 MAM.1 Code execution failure can occur with MAM Mode 2 -, A Section 3.13 PLL.1 PLL output is limited to 290 MHz - Section 3.14 SRAM.1 16 kb SRAM can not be used for code execution - Section 3.15 USB.1 USB_NEED_CLK is always asserted - Section 3.16 ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 3 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 Table 2. Functional problems table continued Functional problems Short description Revision identifier Detailed description USB.2 U1CONNECT is not functional - Section 3.17 USB.3 V BUS status input is not functional - Section 3.18 USB.4 VBAT.1 USB host controller hangs on a dribble bit (LPC2388 only) Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device -, A, B, D Section 3.19 -, A, B Section 3.20 VBAT.2 The VBAT pin cannot be left floating -, A, B, D Section 3.21 WDT.1 Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset - Section 3.22 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations ESD.1 2 kv ESD requirements are not met on the RTCX1 pin - Section 4.1 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. -, A, B, D Section 5.1 Note.2 On the LPC2378/88 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 4 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3. Functional problems detail 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit The LPC2378/88 has a 10-bit ADC, which can be used to measure analog signals and convert the signals into a 10-bit digital result. There are eight A/D channels and each channel has its own individual A/D Data Register (ADDR0 to ADDR7). The A/D Data Register holds the result when an A/D conversion is complete, and also includes the flags that indicate when a conversion has been completed (DONE bit) and when a conversion overrun has occurred. The DONE bit is cleared when the respective A/D Data Register is read. If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the same register (once a conversion is completed) then the DONE bit gets cleared automatically, thereby clearing the indication that a conversion was completed. For software controlled mode or burst mode with only one channel selected, the DONE bit in the A/D Global Data Register (located at 0xE003 4004) can be used instead of the individual ADDRx result register with no impact on performance. For burst mode with multiple channels selected, the DONE bit together with the CHN field in the A/D Global Data Register can be used with some impact on throughput. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 5 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.2 ADC.2: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. 3.3 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 6 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 7 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.5 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. 3.6 EMC.1: Write operation cannot be performed on the external memory bus The External Memory Controller supports asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. Write operation is not operational. Using all the EMC pins as GPIO pins, the write operation can be simulated in software. 3.7 Ethernet.1: Setting up the Ethernet interface in RMII mode The LPC2378/88 has an Ethernet interface, which can be interfaced with an off-chip PHY using the RMII interface. The default configuration of the device does not enable the RMII interface. To use the Ethernet interface in RMII mode write a 1 to bit 12 (P1.16) in PINSEL2 register (located at 0xE002 C008). This workaround only applies for Rev - devices and does not apply for Rev A and newer devices. In order to have both Rev - and other revisions coexist in the same piece of software, the MAC module ID can be used to identify the part and determine if port pin P1.6 needs to be set or not. Here are the steps (along with some sample code) to initialize the MAC based on the module ID: 1. In master header file llpc24xx.h, make sure Module ID is defined (Please note, this ID register is not documented in the User's Manual). #define MAC_BASE_ADDR 0xFFE00000 ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 8 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 2. In the beginning of the MAC initialization file, add below definition: #define OLD_EMAC_MODULE_ID 0x3902 << 16) 0x2000) 3. In MAC initialization routine, right after setting the EMAC clock in the PCONP register, add a few lines as below: /* Turn on the ethernet MAC clock in PCONP, bit 30 */ regval = PCONP; regval = PCONP_EMAC_CLOCK; PCONP = regval; /*------------------------------------------------------ * Write to PINSEL2/3 to select the PHY functions on P1[17:0] * P1.6, ENET-TX_CLK, has to be set for Rev '-' devices and it * must not be set for Rev 'A and newer devices *------------------------------------------------------*/ regval = MAC_MODULEID; if ( regval == OLD_EMAC_MODULE_ID ) { /* On Rev. '-', MAC_MODULEID should be equal to OLD_EMAC_MODULE_ID, P1.6 should be set. */ PINSEL2 = 0x50151105; /* selects P1[0,1,4,6,8,9,10,14,15] */ } else { /* on rev. 'A', MAC_MODULEID should not equal to OLD_EMAC_MODULE_ID, P1.6 should not be set. */ PINSEL2 = 0x50150105; /* selects P1[0,1,4,8,9,10,14,15] */ } PINSEL3 = 0x00000005; /* selects P1[17:16] */ 3.8 Ethernet.2: Ethernet SRAM disabled The LPC2378/88 has an Ethernet interface, which has a dedicated 16 kb SRAM. When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the Ethernet SRAM is also disabled. Enable the Ethernet block by setting the PCENET bit (bit no. 30) in the PCONP register. The Ethernet SRAM is now enabled. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 9 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.9 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4 The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the number of descriptors in the Descriptor array. Each receive descriptor element in the Descriptor array has an associated status field which consists of the HashCRC word and Status Information word. The status words are updated incorrectly if the number of Descriptors set in the Receive number of Descriptors register is greater than or equal to 5. Define 4 or less in the Receive number of Descriptors register. 3.10 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 10 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.11 Flash.1: Operating speed out of on-chip Flash is restricted The operating speed of this device out of internal Flash/SRAM is specified at 72 MHz. Code execution from internal Flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (Do not use even values for CCLKSEL). 2. Rev - devices: Code execution from internal flash is restricted to a maximum of 60 MHz also. However, this device revision has one more restriction in terms of the PLL output frequency (F CCO - Please refer to PLL.1 above). F CCO is limited to 290 MHz. Considering the same example in PLL.1 (Input crystal-12 MHz, N = 1, M = 12): F CCO =288MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. 3.12 I2S.1: I 2 S DMA interface is non-operational The LPC2378/88 has an I 2 S interface, which can be used for audio devices. The I 2 S interface was initially designed to operate with the general purpose DMA controller. The DMA controller cannot access the I 2 S interface. No known workaround. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 11 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.13 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in Flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal Flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the Flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.14 PLL.1: PLL output (F CCO ) is limited to 290 MHz The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value N, which may be in the range of 1 to 256. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value M, in the range of 1 through 32768. The resulting frequency, F CCO must be in the range of 275 MHz to 550 MHz.This frequency can be divided down (using the Clock Divider registers) to get the desired clock frequencies for the core and peripherals. The maximum output of the CCO within the PLL block is limited to 290 MHz. Care should be taken while programming the PLL so that F CCO resides in the desired range. The suggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of 1 and PLL multiplier (M) of 12. Putting the values in the equation: F CCO = (2 M FIN) / N F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev - and Rev A, see Flash.1). ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 12 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.15 SRAM.1: 16 kb SRAM cannot be used for code execution The LPC2378/88 has 16 kb of SRAM on the AHB2 bus, which would generally be used by the Ethernet block. The 16 kb of SRAM can only be used as data RAM. Code can not be executed from this memory. No known workaround. 3.16 USB.1: USB_NEED_CLK is always asserted The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power Down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. The USB_NEED_CLK bit of the USBIntSt register (located at 0xE01F C1C0) is always asserted, preventing the chip from entering Power Down mode when the USBWAKE bit is set in the INTWAKE register (located at 0xE01F C144). After setting the PCUSB bit in PCONP (located at 0xE01F C0C4), write 0x1 to address 0xFFE0C008. The USB_NEED_CLK signal will now function correctly. Writing to address 0xFFE0C008 only needs to be done once after each chip reset. 3.17 USB.2: U1CONNECT signal is not functional U1CONNECT Signal (alternate function of P2.9) is part of the SoftConnect USB feature, which is used to switch an external 1.5 KW resistor under the software control. The USB U1CONNECT alternate function does not work as expected. Configure P2.9 as a GPIO pin, and use it to enable the pull-up resistor on the U1D+ pin. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 13 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.18 USB.3: V BUS status input is not functional The V BUS signal indicates the presence of USB bus power. The V BUS status input is not functional. Configure P1.30 as a GPIO pin, and poll it to determine when V BUS goes to 0, signalling a disconnect event. 3.19 USB.4: USB host controller hangs on a dribble bit (LPC2388 only) Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. 3.20 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 14 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.21 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). 3.22 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset The Watchdog timer can reset the microcontroller within a reasonable amount of time if it enters an erroneous state. After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to WDFEED may cause an immediate reset. Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and the GPDMA should be disabled while feeding the Watchdog. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 15 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 4. AC/DC deviations detail 5. Errata notes detail 4.1 ESD.1: The LPC2378/88 does not meet the 2 kv ESD requirements on the RTCX1 pin The LPC2378/88 is rated for 2 kv ESD. The RTCX1 pin is the input pin for the RTC oscillator circuit. The LPC2378/88 does not meet the required 2 kv ESD specified. Observe proper ESD handling precautions for the RTCX1 pin. 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2378/88 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 16 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 17 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit................... 5............................5...............................5...........................5 3.2 ADC.2: External sync inputs not operational.. 6............................6...............................6...........................6 3.3 CAN.1: Data Overrun condition can lock the CAN controller............................. 6............................6...............................7...........................7 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 7............................7...............................7 Conditions:.............................7...........................7 3.5 Deep power-down.1: Deep power-down mode is not functional.......................... 8............................8...............................8...........................8 3.6 EMC.1: Write operation cannot be performed on the external memory bus................. 8............................8...............................8...........................8 3.7 Ethernet.1: Setting up the Ethernet interface in RMII mode............................ 8............................8...............................8...........................8 3.8 Ethernet.2: Ethernet SRAM disabled........ 9............................9...............................9...........................9 3.9 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4......................... 10...........................10..............................10..........................10 3.10 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent................................ 10........................... 10.............................. 10.......................... 10 3.11 Flash.1: Operating speed out of on-chip Flash is restricted............................. 11........................... 11.............................. 11.......................... 11 3.12 I2S.1: I 2 S DMA interface is non-operational.. 11........................... 11.............................. 11.......................... 11 3.13 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail.. 12........................... 12.............................. 12.......................... 12 3.14 PLL.1: PLL output (F CCO ) is limited to 290 MHz. 12........................... 12.............................. 12.......................... 12 3.15 SRAM.1: 16 kb SRAM cannot be used for code execution............................ 13........................... 13.............................. 13.......................... 13 3.16 USB.1: USB_NEED_CLK is always asserted 13........................... 13.............................. 13.......................... 13 3.17 USB.2: U1CONNECT signal is not functional 13........................... 13.............................. 13.......................... 13 3.18 USB.3: V BUS status input is not functional... 14........................... 14.............................. 14.......................... 14 3.19 USB.4: USB host controller hangs on a dribble bit (LPC2388 only)....................... 14........................... 14.............................. 14.......................... 14 continued >> ES_LPC2378_88 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 18 of 19

ES_LPC2378_88 Errata sheet LPC2378/88 3.20 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................ 14...........................14..............................14..........................14 3.21 VBAT.2: The VBAT pin cannot be left floating. 15...........................15..............................15..........................15 3.22 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset 15...........................15..............................15..........................15 4 AC/DC deviations detail................. 16 4.1 ESD.1: The LPC2378/88 does not meet the 2 kv ESD requirements on the RTCX1 pin....... 16...........................16..............................16..........................16 5 Errata notes detail...................... 16 5.1 Note.1............................... 16 5.2 Note.2............................... 16 6 Legal information....................... 17 6.1 Definitions............................ 17 6.2 Disclaimers........................... 17 6.3 Trademarks........................... 17 7 Contents.............................. 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2378_88

ES_LPC2387 Errata sheet LPC2387 Rev. 7.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2387 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table at the end of the document.

ES_LPC2387 Errata sheet LPC2387 Revision history Rev Date Description 7.1 20120701 Added Rev D to VBAT.2. Updated CAN.1. Added USB.4. 7 20110420 Added Note.3. 6 20110301 Added ADC.2. 5 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.4 4 20100122 Added VBAT.2 3 20090512 Added Rev D 2 20081118 Added Errata Note.2 1 20080904 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 2 of 21

ES_LPC2387 Errata sheet LPC2387 1. Product identification 2. Errata overview The LPC2387 devices typically have the following top-side marking: LPC2387xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2387: Table 1. Device revision table Revision identifier (R) Revision description - Initial device revision A Second device revision B Third device revision D Fourth device revision Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 ADDRx read conflicts with hardware setting of DONE bit - Section 3.1 ADC.2 External sync inputs not operational -, A, B, D Section 3.2 CAN.1 Data overrun condition can lock the CAN controller -, A, B Section 3.3 Core.1 Deep power-down.1 Incorrect update of the Abort Link register in Thumb state -, A, B, D Section 3.4 Deep power-down mode is not functional -, A, B Section 3.5 Ethernet.1 Setting up the Ethernet interface in RMII mode - Section 3.6 Ethernet.2 Ethernet SRAM disabled - Section 3.7 Ethernet.3 RxDescriptor number cannot be greater than 4 - Section 3.8 Ethernet.4 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent -, A, B, D Section 3.9 Flash.1 Operating speed out of on-chip flash is restricted -, A Section 3.10 I2S.1 I 2 S DMA can stall - Section 3.11 MAM.1 Code execution failure can occur with MAM Mode 2 -, A Section 3.12 PLL.1 PLL output is limited to 290 MHz - Section 3.13 SRAM.1 16 kb SRAM can not be used for code execution - Section 3.14 USB.1 USB_NEED_CLK is always asserted - Section 3.15 USB.2 U1CONNECT is not functional - Section 3.16 USB.3 V BUS status input is not functional - Section 3.17 ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 3 of 21

ES_LPC2387 Errata sheet LPC2387 Table 2. Functional problems table continued Functional problems Short description Revision identifier Detailed description USB.4 USB host controller hangs on a dribble bit -, A, B, D Section 3.18 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device -, A, B Section 3.19 VBAT.2 The VBAT pin cannot be left floating -, A, B, D Section 3.20 WDT.1 Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset - Section 3.21 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations ESD.1 2 kv ESD requirements are not met on the RTCX1 pin - Section 4.1 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31, (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. -, A, B, D Section 5.1 Note.2 Note.3 Device marked with a date code 0836 or later have USB 2.0 full-speed dual port device/host/otg controller with on-chip PHY and associated DMA controller. On the LPC2387 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. B Section 5.2 D Section 5.3 ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 4 of 21

ES_LPC2387 Errata sheet LPC2387 3. Functional problems detail 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit The LPC2387 has a 10-bit ADC, which can be used to measure analog signals and convert the signals into a 10-bit digital result. There are eight A/D channels and each channel has its own individual A/D Data Register (ADDR0 to ADDR7). The A/D Data Register holds the result when an A/D conversion is complete, and also includes the flags that indicate when a conversion has been completed (DONE bit) and when a conversion overrun has occurred. The DONE bit is cleared when the respective A/D Data Register is read. If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the same register (once a conversion is completed) then the DONE bit gets cleared automatically, thereby clearing the indication that a conversion was completed. For software controlled mode or burst mode with only one channel selected, the DONE bit in the A/D Global Data Register (located at 0xE003 4004) can be used instead of the individual ADDRx result register with no impact on performance. For burst mode with multiple channels selected, the DONE bit together with the CHN field in the A/D Global Data Register can be used with some impact on throughput. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 5 of 21

ES_LPC2387 Errata sheet LPC2387 3.2 ADC.2: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 6 of 21

ES_LPC2387 Errata sheet LPC2387 3.3 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 7 of 21

ES_LPC2387 Errata sheet LPC2387 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 8 of 21

ES_LPC2387 Errata sheet LPC2387 3.5 Deep power-down.1: Deep power-down mode is not functional Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. The power consumption in Deep power-down mode does not meet the specifications. None. 3.6 Ethernet.1: Setting up the Ethernet interface in RMII mode The LPC2387 has an Ethernet interface, which can be interfaced with an off-chip PHY using the RMII interface. The default configuration of the device does not enable the RMII interface. To use the Ethernet interface in RMII mode write a 1 to bit 12 (P1.16) in PINSEL2 register (located at 0xE002 C008). This workaround only applies for Rev - devices and does not apply for Rev A and newer devices. In order to have both Rev - and other revisions coexist in the same piece of software, the MAC module ID can be used to identify the part and determine if port pin P1.6 needs to be set or not. Here are the steps (along with some sample code) to initialize the MAC based on the module ID: 1. In master header file llpc24xx.h, make sure Module ID is defined (Please note, this ID register is not documented in the User's Manual). #define MAC_BASE_ADDR 0xFFE00000 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 2. In the beginning of the MAC initialization file, add below definition: #define OLD_EMAC_MODULE_ID 0x3902 << 16) 0x2000) 3. In MAC initialization routine, right after setting the EMAC clock in the PCONP register, add a few lines as below: /* Turn on the ethernet MAC clock in PCONP, bit 30 */ regval = PCONP; regval = PCONP_EMAC_CLOCK; PCONP = regval; /*------------------------------------------------------ * Write to PINSEL2/3 to select the PHY functions on P1[17:0] ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 9 of 21

ES_LPC2387 Errata sheet LPC2387 * P1.6, ENET-TX_CLK, has to be set for Rev '-' devices and it * must not be set for Rev 'A and newer devices *------------------------------------------------------*/ regval = MAC_MODULEID; if ( regval == OLD_EMAC_MODULE_ID ) { /* On Rev. '-', MAC_MODULEID should be equal to OLD_EMAC_MODULE_ID, P1.6 should be set. */ PINSEL2 = 0x50151105; /* selects P1[0,1,4,6,8,9,10,14,15] */ } else { /* on rev. 'A', MAC_MODULEID should not equal to OLD_EMAC_MODULE_ID, P1.6 should not be set. */ PINSEL2 = 0x50150105; /* selects P1[0,1,4,8,9,10,14,15] */ } PINSEL3 = 0x00000005; /* selects P1[17:16] */ 3.7 Ethernet.2: Ethernet SRAM disabled The LPC2387 has an Ethernet interface, which has a dedicated 16 kb SRAM. When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the Ethernet SRAM is also disabled. Enable the Ethernet block by setting the PCENET bit (bit no. 30) in the PCONP register. The Ethernet SRAM is now enabled. 3.8 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4 The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the number of descriptors in the Descriptor array. Each receive descriptor element in the Descriptor array has an associated status field which consists of the HashCRC word and Status Information word. The status words are updated incorrectly if the number of Descriptors set in the Receive number of Descriptors register is greater than or equal to 5. Define 4 or less in the Receive number of Descriptors register. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 10 of 21

ES_LPC2387 Errata sheet LPC2387 3.9 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 11 of 21

ES_LPC2387 Errata sheet LPC2387 3.10 Flash.1: Operating speed out of on-chip Flash is restricted The operating speed of this device out of internal Flash/SRAM is specified at 72 MHz. Code execution from internal Flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (Do not use even values for CCLKSEL). 2. Rev - devices: Code execution from internal flash is restricted to a maximum of 60 MHz also. However, this device revision has one more restriction in terms of the PLL output frequency (F CCO - Please refer to PLL.1 above). F CCO is limited to 290 MHz. Considering the same example in PLL.1 (Input crystal-12 MHz, N = 1, M = 12): F CCO =288MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. 3.11 I2S.1: I 2 S DMA interface is non-operational The LPC2387 has an I 2 S interface, which can be used for audio devices. The I 2 S interface was initially designed to operate with the general purpose DMA controller. The DMA controller cannot access the I 2 S interface. No known workaround. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 12 of 21

ES_LPC2387 Errata sheet LPC2387 3.12 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in Flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal Flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the Flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.13 PLL.1: PLL output (F CCO ) is limited to 290 MHz The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value N, which may be in the range of 1 to 256. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value M, in the range of 1 through 32768. The resulting frequency, F CCO must be in the range of 275 MHz to 550 MHz.This frequency can be divided down (using the Clock Divider registers) to get the desired clock frequencies for the core and peripherals. The maximum output of the CCO within the PLL block is limited to 290 MHz. Care should be taken while programming the PLL so that F CCO resides in the desired range. The suggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of 1 and PLL multiplier (M) of 12. Putting the values in the equation: F CCO = (2 M FIN) / N F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev - and Rev A, see Flash.1). ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 13 of 21

ES_LPC2387 Errata sheet LPC2387 3.14 SRAM.1: 16 kb SRAM cannot be used for code execution The LPC2387 has 16 kb of SRAM on the AHB2 bus, which would generally be used by the Ethernet block. The 16 kb of SRAM can only be used as data RAM. Code can not be executed from this memory. No known workaround. 3.15 USB.1: USB_NEED_CLK is always asserted The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. The USB_NEED_CLK bit of the USBIntSt register (located at 0xE01F C1C0) is always asserted, preventing the chip from entering Power Down mode when the USBWAKE bit is set in the INTWAKE register (located at 0xE01F C144). After setting the PCUSB bit in PCONP (located at 0xE01F C0C4), write 0x1 to address 0xFFE0C008. The USB_NEED_CLK signal will now function correctly. Writing to address 0xFFE0C008 only needs to be done once after each chip reset. 3.16 USB.2: U1CONNECT signal is not functional U1CONNECT Signal (alternate function of P2.9) is part of the SoftConnect USB feature, which is used to switch an external 1.5 KW resistor under the software control. The USB U1CONNECT alternate function does not work as expected. Configure P2.9 as a GPIO pin, and use it to enable the pull-up resistor on the U1D+ pin. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 14 of 21

ES_LPC2387 Errata sheet LPC2387 3.17 USB.3: V BUS status input is not functional The V BUS signal indicates the presence of USB bus power. The V BUS status input is not functional. Configure P1.30 as a GPIO pin, and poll it to determine when V BUS goes to 0, signalling a disconnect event. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 15 of 21

ES_LPC2387 Errata sheet LPC2387 3.18 USB.4: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. 3.19 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 16 of 21

ES_LPC2387 Errata sheet LPC2387 3.20 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). 3.21 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset The Watchdog timer can reset the microcontroller within a reasonable amount of time if it enters an erroneous state. After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to WDFEED may cause an immediate reset. Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and the GPDMA should be disabled while feeding the Watchdog. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 17 of 21

ES_LPC2387 Errata sheet LPC2387 4. AC/DC deviations detail 5. Errata notes detail 4.1 ESD.1: The LPC2387 does not meet the 2 kv ESD requirements on the RTCX1 pin The LPC2387 is rated for 2 kv ESD. The RTCX1 pin is the input pin for the RTC oscillator circuit. The LPC2387 does not meet the required 2 kv ESD specified. Observe proper ESD handling precautions for the RTCX1 pin. 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 Devices with a date code prior to 0836 (manufactured before week 36 in 2008) have USB 2.0 full-speed dual port device with on-chip PHY and associated DMA controller. Parts marked with date code 0836 or later have USB 2.0 full-speed dual port device/host/otg controller with on-chip PHY and associated DMA controller. Please refer to Section 1 of this document for details on how to identify the date code. 5.3 Note.3 On the LPC2387 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 18 of 21

ES_LPC2387 Errata sheet LPC2387 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 19 of 21

ES_LPC2387 Errata sheet LPC2387 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit................... 5............................5...............................5...........................5 3.2 ADC.2: External sync inputs not operational.. 6............................6...............................6...........................6 3.3 CAN.1: Data Overrun condition can lock the CAN controller............................. 7............................7...............................7...........................7 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 8............................8...............................8 Conditions:.............................8...........................8 3.5 Deep power-down.1: Deep power-down mode is not functional.......................... 9............................9...............................9...........................9 3.6 Ethernet.1: Setting up the Ethernet interface in RMII mode............................ 9............................9...............................9...........................9 3.7 Ethernet.2: Ethernet SRAM disabled....... 10...........................10..............................10..........................10 3.8 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4......................... 10...........................10..............................10..........................10 3.9 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent................................. 11...........................11..............................11.......................... 11 3.10 Flash.1: Operating speed out of on-chip Flash is restricted............................ 12........................... 12.............................. 12.......................... 12 3.11 I2S.1: I 2 S DMA interface is non-operational. 12........................... 12.............................. 12.......................... 12 3.12 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail.. 13........................... 13.............................. 13.......................... 13 3.13 PLL.1: PLL output (F CCO ) is limited to 290 MHz............................. 13........................... 13.............................. 13.......................... 13 3.14 SRAM.1: 16 kb SRAM cannot be used for code execution............................ 14........................... 14.............................. 14.......................... 14 3.15 USB.1: USB_NEED_CLK is always asserted 14........................... 14.............................. 14.......................... 14 3.16 USB.2: U1CONNECT signal is not functional 14........................... 14.............................. 14.......................... 14 3.17 USB.3: V BUS status input is not functional... 15........................... 15.............................. 15.......................... 15 3.18 USB.4: USB host controller hangs on a dribble bit.................................. 16........................... 16.............................. 16.......................... 16 3.19 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device............... 16........................... 16.............................. 16.......................... 16 continued >> ES_LPC2387 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 20 of 21

ES_LPC2387 Errata sheet LPC2387 3.20 VBAT.2: The VBAT pin cannot be left floating. 17...........................17..............................17..........................17 3.21 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset................................ 17...........................17..............................17..........................17 4 AC/DC deviations detail................. 18 4.1 ESD.1: The LPC2387 does not meet the 2 kv ESD requirements on the RTCX1 pin....... 18...........................18..............................18..........................18 5 Errata notes detail...................... 18 5.1 Note.1............................... 18 5.2 Note.2............................... 18 5.3 Note.3............................... 18 6 Legal information....................... 19 6.1 Definitions............................ 19 6.2 Disclaimers........................... 19 6.3 Trademarks........................... 19 7 Contents.............................. 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2387

ES_LPC2420 Errata sheet LPC2420 Rev. 7.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2420FBD208; LPC2420FET208, LPC2420 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2420 Errata sheet LPC2420 Revision history Rev Date Description 7.1 20120701 Added VBAT.1. 7 20110601 Added USB.1. 6 20110420 Added Note.2. 5 20110301 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added ADC.1. 4 20100209 Added date code info for IRC.2. 3 20090814 Added IRC.2. 2 20090511 Added Rev D. 1 20081126 First version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 2 of 11

ES_LPC2420 Errata sheet LPC2420 1. Product identification The LPC2420 devices typically have the following top-side marking: LPC2420xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2420: Table 1. Device revision table Revision identifier (R) C D Revision description Second device revision Third device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational C, D Section 3.1 Core.1 Incorrect update of the Abort Link register in Thumb state C, D Section 3.2 USB.1 USB host controller hangs on a dribble bit C, D Section 3.3 VBAT.1 The VBAT pin cannot be left floating C, D Section 3.4 Table 3. AC/DC deviations table AC/DC Short description Revision identifier Detailed description deviations IRC.1 Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/- 1 % specification only at extreme temperatures. C Section 4.1 IRC.2 Accuracy of the internal RC oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of spec between 20 C and 40 C D Section 4.2 ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 3 of 11

ES_LPC2420 Errata sheet LPC2420 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. C, D Section 5.1 Note.2 On the LPC2420 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 4 of 11

ES_LPC2420 Errata sheet LPC2420 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 5 of 11

ES_LPC2420 Errata sheet LPC2420 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 6 of 11

ES_LPC2420 Errata sheet LPC2420 3.3 USB.1: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. 3.4 VBAT.1: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 7 of 11

ES_LPC2420 Errata sheet LPC2420 4. AC/DC deviations detail 4.1 IRC.1: Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/ 1 % specification only at extreme temperatures The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ 1 % accuracy over the entire voltage and temperature range. During In-System Programming (ISP), the auto-baud routine is expecting the IRC frequency to be 4 MHz +/ 1 % and is used to synchronize with the host via serial port 0. On the LPC2420 Rev C device only, the accuracy of internal RC oscillator (IRC) frequency meets 4 MHz +/ 1 % specification only at room temperature however, at extreme temperatures, the accuracy of internal RC oscillator (IRC) frequency may be 4MHz +/ 10 %. As a result, at extreme temperatures, this may affect the auto-baud routine's ability to synchronize with the host via serial port 0 during In-System Programming (ISP) at higher baud rates. None ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 8 of 11

ES_LPC2420 Errata sheet LPC2420 4.2 IRC.2: Accuracy of the Internal RC oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of the 4MHz +/ 1 % specification only at temperatures between 20 C and 40 C The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ 1 % accuracy over the entire voltage and temperature range. During In-System Programming (ISP), the auto-baud routine is expecting the IRC frequency to be 4 MHz +/ 1 % and is used to synchronize with the host via serial port 0. On the LPC2420 Rev D device (only with date codes 0949 and before), the accuracy of internal RC oscillator (IRC) frequency does not meet the 4 MHz +/ 1 % specification for temperatures between 20 C and 40 C and the accuracy of internal RC oscillator (IRC) frequency is 4 MHz +/ 5 % instead. As a result, only at these temperatures, this may affect the auto-baud routine's ability to synchronize with the host via serial port 0 during In-System Programming (ISP) at higher baud rates. For temperatures above 20 C, the accuracy of internal RC oscillator (IRC) frequency meets the 4 MHz +/ 1 % specification. None 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2420 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 9 of 11

ES_LPC2420 Errata sheet LPC2420 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2420 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 7.1 1 July 2012 10 of 11

ES_LPC2420 Errata sheet LPC2420 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 6............................6...............................6 Conditions:.............................6...........................6 3.3 USB.1: USB host controller hangs on a dribble bit................................... 7............................7...............................7...........................7 3.4 VBAT.1: The VBAT pin cannot be left floating.. 7............................7...............................7...........................7 4 AC/DC deviations detail.................. 8 4.1 IRC.1: Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/- 1 % specification only at extreme temperatures... 8............................8...............................8...........................8 4.2 IRC.2: Accuracy of the Internal RC oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of the 4 MHz +/- 1 % specification only at temperatures between -20 C and -40 C............................ 9............................9...............................9...........................9 5 Errata notes detail....................... 9 5.1 Note.1................................ 9 5.2 Note.2................................ 9 6 Legal information....................... 10 6.1 Definitions............................ 10 6.2 Disclaimers........................... 10 6.3 Trademarks........................... 10 7 Contents.............................. 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2420

ES_LPC2458 Errata sheet LPC2458 Rev. 6.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2458 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2458 Errata sheet LPC2458 Revision history Rev Date Description 6.1 20120701 Added Rev D to VBAT.2. Updated CAN.1. 6 20110601 Added USB.1. 5.1 20110316 Added Note.2. 5 20110301 Added ADC.1. 4 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 3 20100122 Added VBAT.2 2 20090508 Added Rev D 1 20080812 First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 2 of 13

ES_LPC2458 Errata sheet LPC2458 1. Product identification The LPC2458 devices typically have the following top-side marking: LPC2458xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2458: Table 1. Device revision table Revision identifier (R) B D Revision description Initial device revision Second device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational B, D Section 3.1 CAN.1 Data overrun condition can lock the CAN controller B Section 3.2 Core.1 Ethernet.1 Incorrect update of the Abort Link register in Thumb state Ethernet TxConsumeIndex register does not update correctly after the first frame is sent B, D Section 3.3 B, D Section 3.4 USB.1 USB host controller hangs on a dribble bit B, D Section 3.5 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device B Section 3.6 VBAT.2 The VBAT pin cannot be left floating B, D Section 3.7 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations n/a n/a n/a n/a ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 3 of 13

ES_LPC2458 Errata sheet LPC2458 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. B, D Section 5.1 Note.2 On the LPC2458 Rev D, design changes to the Memory Accelerator Module are made to enhance timing and general performance. D Section 5.2 ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 4 of 13

ES_LPC2458 Errata sheet LPC2458 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 5 of 13

ES_LPC2458 Errata sheet LPC2458 3.2 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 6 of 13

ES_LPC2458 Errata sheet LPC2458 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 7 of 13

ES_LPC2458 Errata sheet LPC2458 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 8 of 13

ES_LPC2458 Errata sheet LPC2458 3.5 USB.1: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 9 of 13

ES_LPC2458 Errata sheet LPC2458 3.7 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 10 of 13

ES_LPC2458 Errata sheet LPC2458 4. AC/DC deviations detail 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2458 Rev D, design changes to the Memory Accelerator Module are made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 11 of 13

ES_LPC2458 Errata sheet LPC2458 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2458 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 6.1 1 July 2012 12 of 13

ES_LPC2458 Errata sheet LPC2458 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 CAN.1: Data Overrun condition can lock the CAN controller............................. 6............................6...............................6...........................6 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 7............................7...............................7 Conditions:.............................7...........................7 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent.................................. 8............................8...............................8...........................8 3.5 USB.1: USB host controller hangs on a dribble bit 9............................9...............................9...........................9 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 9............................9...............................9...........................9 3.7 VBAT.2: The VBAT pin cannot be left floating 10...........................10..............................10..........................10 4 AC/DC deviations detail................. 11 4.1 n/a.................................. 11 5 Errata notes detail...................... 11 5.1 Note.1............................... 11 5.2 Note.2............................... 11 6 Legal information....................... 12 6.1 Definitions............................ 12 6.2 Disclaimers........................... 12 6.3 Trademarks.......................... 12 7 Contents.............................. 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2458

ES_LPC2460 Errata sheet LPC2460 Rev. 9.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2460 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2460 Errata sheet LPC2460 Revision history Rev Date Description 9.1 20120701 Added Rev C and Rev D to VBAT.2. Updated CAN.1. 9 20110601 Added USB.1. 8 20110420 Added Note.2. 7 20110301 Added ADC.1. 6 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 5 20100209 Added date code info for IRC.2 4 20100122 Added VBAT.2 3 20090814 Added IRC.2 2 20090511 Added Rev D 1 20080812 First version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 2 of 13

ES_LPC2460 Errata sheet LPC2460 1. Product identification The LPC2460 devices typically have the following top-side marking: LPC2460xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2460: Table 1. Device revision table Revision identifier (R) B C D Revision description Initial device revision Second device revision Third device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational B, C, D Section 3.1 Core.1 Incorrect update of the Abort Link register in Thumb state B, C, D Section 3.2 CAN.1 Data overrun condition can lock the CAN controller B Section 3.3 Ethernet.1 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent B, C, D Section 3.4 USB.1 USB host controller hangs on a dribble bit B, C, D Section 3.5 VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device B Section 3.6 VBAT.2 The VBAT pin cannot be left floating B, C, D Section 3.7 Table 3. AC/DC deviations table AC/DC Short description Revision identifier Detailed description deviations IRC.1 Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/- 1 % specification only at extreme temperatures. C Section 4.1 IRC.2 Accuracy of the internal RC oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of spec between 20 C and 40 C D Section 4.2 ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 3 of 13

ES_LPC2460 Errata sheet LPC2460 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. B, C, D Section 5.1 Note.2 On the LPC2460 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 4 of 13

ES_LPC2460 Errata sheet LPC2460 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 5 of 13

ES_LPC2460 Errata sheet LPC2460 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 6 of 13

ES_LPC2460 Errata sheet LPC2460 3.3 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 7 of 13

ES_LPC2460 Errata sheet LPC2460 3.5 USB.1: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 8 of 13

ES_LPC2460 Errata sheet LPC2460 3.7 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 9 of 13

ES_LPC2460 Errata sheet LPC2460 4. AC/DC deviations detail 4.1 IRC.1: Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/ 1 % specification only at extreme temperatures The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ 1 % accuracy over the entire voltage and temperature range. During In-System Programming (ISP), the auto-baud routine is expecting the IRC frequency to be 4 MHz +/ 1 % and is used to synchronize with the host via serial port 0. On the LPC2460 Rev C device only, the accuracy of internal RC oscillator (IRC) frequency meets 4 MHz +/ 1 % specification only at room temperature however, at extreme temperatures, the accuracy of internal RC oscillator (IRC) frequency may be 4MHz +/ 10 %. As a result, at extreme temperatures, this may affect the auto-baud routine's ability to synchronize with the host via serial port 0 during In-System Programming (ISP) at higher baud rates. None ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 10 of 13

ES_LPC2460 Errata sheet LPC2460 4.2 IRC.2: Accuracy of the Internal RC Oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of the 4MHz +/ 1 % specification only at temperatures between 20 C and 40 C The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ 1 % accuracy over the entire voltage and temperature range. During In-System Programming (ISP), the auto-baud routine is expecting the IRC frequency to be 4 MHz +/ 1 % and is used to synchronize with the host via serial port 0. On the LPC2460 Rev D device (only with date codes 0949 and before), the accuracy of internal RC oscillator (IRC) frequency does not meet the 4 MHz +/ 1 % specification for temperatures between 20 C and 40 C and the accuracy of internal RC oscillator (IRC) frequency is 4 MHz +/ 5 % instead. As a result, only at these temperatures, this may affect the auto-baud routine's ability to synchronize with the host via serial port 0 during In-System Programming (ISP) at higher baud rates. For temperatures above 20 C, the accuracy of internal RC oscillator (IRC) frequency meets the 4 MHz +/ 1 % specification. None 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2460 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 11 of 13

ES_LPC2460 Errata sheet LPC2460 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2460 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 9.1 1 July 2012 12 of 13

ES_LPC2460 Errata sheet LPC2460 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: External sync inputs not operational.. 5............................5...............................5...........................5 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 6............................6...............................6 Conditions:.............................6...........................6 3.3 CAN.1: Data Overrun condition can lock the CAN controller............................. 7............................7...............................7...........................7 3.4 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent.................................. 7............................7...............................7...........................7 3.5 USB.1: USB host controller hangs on a dribble bit 8............................8...............................8...........................8 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device................. 8............................8...............................8...........................8 3.7 VBAT.2: The VBAT pin cannot be left floating. 9............................9...............................9...........................9 4 AC/DC deviations detail................. 10 4.1 IRC.1: Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/- 1 % specification only at extreme temperatures.. 10...........................10..............................10..........................10 4.2 IRC.2: Accuracy of the Internal RC Oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of the 4 MHz +/- 1 % specification only at temperatures between -20 C and -40 C............................ 11........................... 11.............................. 11.......................... 11 5 Errata notes detail....................... 11 5.1 Note.1............................... 11 5.2 Note.2............................... 11 6 Legal information...................... 12 6.1 Definitions........................... 12 6.2 Disclaimers.......................... 12 6.3 Trademarks.......................... 12 7 Contents.............................. 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2460

ES_LPC2468 Errata sheet LPC2468 Rev. 11.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2468 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2468 Errata sheet LPC2468 Revision history Rev Date Description 11.1 20120701 Added Rev D to VBAT.2. Updated CAN.1. 11 20110601 Added USB.5. 10 20110420 Added Note.2. 9 20110301 Added ADC.2. 8 20100513 Added VBAT.2 7 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.4 6 20090508 Added Rev D 5 20080602 Added Note.1 4 20080408 Added VBAT.1 3 20080212 USB.4 was added 2 20070921 Added Rev. B Removed Rev A from ESD.1. ESD.1 does not appear in Rev A. It was accidentally listed in version 1.2 1 20070720 Added Ethernet.3 Updated Ethernet.1 Updated Flash.1 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 2 of 21

ES_LPC2468 Errata sheet LPC2468 1. Product identification 2. Errata overview The LPC2468 devices typically have the following top-side marking: LPC2468xxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2468: Table 1. Device revision table Revision identifier (R) Revision description - Initial device revision A Second device revision B Third device revision D Fourth device revision Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 ADDRx read conflicts with hardware setting of DONE bit - Section 3.1 ADC.2 External sync inputs not operational -, A, B, D Section 3.2 CAN.1 Data overrun condition can lock the CAN controller -, A, B Section 3.3 Core.1 Incorrect update of the Abort Link register in Thumb state -, A, B, D Section 3.4 Ethernet.1 Setting up the Ethernet interface in RMII mode - Section 3.5 Ethernet.2 Ethernet SRAM disabled - Section 3.6 Ethernet.3 RxDescriptor number cannot be greater than 4 - Section 3.7 Ethernet.4 Ethernet TxConsumeIndex register does not update correctly after the first frame is sent -, A, B, D Section 3.8 Flash.1 Operating speed out of on-chip flash is restricted -, A Section 3.9 I2S.1 I 2 S DMA can stall - Section 3.10 MAM.1 Code execution failure can occur with MAM Mode 2 -, A Section 3.11 PLL.1 PLL output is limited to 290 MHz - Section 3.12 SRAM.1 16 kb SRAM can not be used for code execution - Section 3.13 USB.1 USB_NEED_CLK is always asserted - Section 3.14 USB.2 U1CONNECT is not functional - Section 3.15 USB.3 V BUS status input is not functional - Section 3.16 USB.4 USB_PWRDx pin(s) does not function as intended - Section 3.17 USB.5 USB host controller hangs on a dribble bit -, A, B, D Section 3.18 ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 3 of 21

ES_LPC2468 Errata sheet LPC2468 Table 2. Functional problems table continued Functional problems Short description Revision identifier Detailed description VBAT.1 Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of device -, A, B Section 3.19 VBAT.2 The VBAT pin cannot be left floating -, A, B, D Section 3.20 WDT.1 Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset - Section 3.21 Table 3. AC/DC deviations table AC/DC Short description Product version(s) Detailed description deviations ESD.1 2 kv ESD requirements are not met on the RTCX1 pin - Section 4.1 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. -, A, B, D Section 5.1 Note.2 On the LPC2468 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 4 of 21

ES_LPC2468 Errata sheet LPC2468 3. Functional problems detail 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit The LPC2468 has a 10-bit ADC, which can be used to measure analog signals and convert the signals into a 10-bit digital result. There are eight A/D channels and each channel has its own individual A/D Data Register (ADDR0 to ADDR7). The A/D Data Register holds the result when an A/D conversion is complete, and also includes the flags that indicate when a conversion has been completed (DONE bit) and when a conversion overrun has occurred. The DONE bit is cleared when the respective A/D Data Register is read. If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the same register (once a conversion is completed) then the DONE bit gets cleared automatically, thereby clearing the indication that a conversion was completed. For software controlled mode or burst mode with only one channel selected, the DONE bit in the A/D Global Data Register (located at 0xE003 4004) can be used instead of the individual ADDRx result register with no impact on performance. For burst mode with multiple channels selected, the DONE bit together with the CHN field in the A/D Global Data Register can be used with some impact on throughput. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 5 of 21

ES_LPC2468 Errata sheet LPC2468 3.2 ADC.2: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 6 of 21

ES_LPC2468 Errata sheet LPC2468 3.3 CAN.1: Data Overrun condition can lock the CAN controller Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 7 of 21

ES_LPC2468 Errata sheet LPC2468 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 8 of 21

ES_LPC2468 Errata sheet LPC2468 3.5 Ethernet.1: Setting up the Ethernet interface in RMII mode The LPC2468 has an Ethernet interface, which can be interfaced with an off-chip PHY using the RMII interface. The default configuration of the device does not enable the RMII interface. To use the Ethernet interface in RMII mode write a 1 to bit 12 (P1.16) in PINSEL2 register (located at 0xE002 C008). This workaround only applies for Rev - devices and does not apply for Rev A and newer devices. In order to have both Rev - and other revisions coexist in the same piece of software, the MAC module ID can be used to identify the part and determine if port pin P1.6 needs to be set or not. Here are the steps (along with some sample code) to initialize the MAC based on the module ID: 1. In master header file llpc24xx.h, make sure Module ID is defined (Please note, this ID register is not documented in the User's Manual). #define MAC_BASE_ADDR 0xFFE00000 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 2. In the beginning of the MAC initialization file, add below definition: #define OLD_EMAC_MODULE_ID 0x3902 << 16) 0x2000) 3. In MAC initialization routine, right after setting the EMAC clock in the PCONP register, add a few lines as below: /* Turn on the ethernet MAC clock in PCONP, bit 30 */ regval = PCONP; regval = PCONP_EMAC_CLOCK; PCONP = regval; /*------------------------------------------------------ * Write to PINSEL2/3 to select the PHY functions on P1[17:0] * P1.6, ENET-TX_CLK, has to be set for Rev '-' devices and it * must not be set for Rev 'A and newer devices *------------------------------------------------------*/ regval = MAC_MODULEID; if ( regval == OLD_EMAC_MODULE_ID ) { /* On Rev. '-', MAC_MODULEID should be equal to OLD_EMAC_MODULE_ID, P1.6 should be set. */ PINSEL2 = 0x50151105; /* selects P1[0,1,4,6,8,9,10,14,15] */ } else { /* on rev. 'A', MAC_MODULEID should not equal to ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 9 of 21

ES_LPC2468 Errata sheet LPC2468 OLD_EMAC_MODULE_ID, P1.6 should not be set. */ PINSEL2 = 0x50150105; /* selects P1[0,1,4,8,9,10,14,15] */ } PINSEL3 = 0x00000005; /* selects P1[17:16] */ 3.6 Ethernet.2: Ethernet SRAM disabled The LPC2468 has an Ethernet interface, which has a dedicated 16 kb SRAM. When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the Ethernet SRAM is also disabled. Enable the Ethernet block by setting the PCENET bit (bit no. 30) in the PCONP register. The Ethernet SRAM is now enabled. 3.7 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4 The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the number of descriptors in the Descriptor array. Each receive descriptor element in the Descriptor array has an associated status field which consists of the HashCRC word and Status Information word. The status words are updated incorrectly if the number of Descriptors set in the Receive number of Descriptors register is greater than or equal to 5. Define 4 or less in the Receive number of Descriptors register. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 10 of 21

ES_LPC2468 Errata sheet LPC2468 3.8 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to 2). This only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been reached) Software can correct this situation in many ways; for example, sending a dummy frame after initialization. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 11 of 21

ES_LPC2468 Errata sheet LPC2468 3.9 Flash.1: Operating speed out of on-chip flash is restricted The operating speed of this device out of internal flash/sram is specified at 72 MHz. Code execution from internal flash is restricted depending upon the device revision: 1. Rev A devices: Code execution from internal flash is restricted to a maximum of 60 MHz. For example, use a PLL output frequency of F CCO = 360 MHz and divide it by 6 (CCLKSEL = 5) to generate 60 MHz CPU clock (Do not use even values for CCLKSEL). 2. Rev - devices: Code execution from internal flash is restricted to a maximum of 60 MHz also. However, this device revision has one more restriction in terms of the PLL output frequency (F CCO - Please refer to PLL.1 above). F CCO is limited to 290 MHz. Considering the same example in PLL.1 (Input crystal - 12 MHz, N = 1, M = 12): F CCO =288MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 6 (CCLKSEL = 5) to achieve a maximum of 48 MHz. Since this register only accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option. In both the above revisions, code can still execute out of SRAM at up to 72 MHz. None. 3.10 I2S.1: I 2 S DMA interface is non-operational The LPC2468 has an I 2 S interface, which can be used for audio devices. The I 2 S interface was initially designed to operate with the general purpose DMA controller. The DMA controller cannot access the I 2 S interface. No known workaround. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 12 of 21

ES_LPC2468 Errata sheet LPC2468 3.11 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail The MAM block maximizes the performance of the ARM processor when it is running code in flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled). Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal flash can fail. The conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. If the above problem is encountered then Mode 2 should not be used. Instead, partially enable the MAM using Mode 1. 3.12 PLL.1: PLL output (F CCO ) is limited to 290 MHz The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value N, which may be in the range of 1 to 256. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value M, in the range of 1 through 32768. The resulting frequency, F CCO must be in the range of 275 MHz to 550 MHz.This frequency can be divided down (using the Clock Divider registers) to get the desired clock frequencies for the core and peripherals. The maximum output of the CCO within the PLL block is limited to 290 MHz. Care should be taken while programming the PLL so that F CCO resides in the desired range. The suggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of 1 and PLL multiplier (M) of 12. Putting the values in the equation: F CCO = (2 M FIN) / N F CCO = 288 MHz The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide this frequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev - and Rev A, see Flash.1). ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 13 of 21

ES_LPC2468 Errata sheet LPC2468 3.13 SRAM.1: 16 kb SRAM cannot be used for code execution The LPC2468 has 16 kb of SRAM on the AHB2 bus, which would generally be used by the Ethernet block. The 16 kb of SRAM can only be used as data RAM. Code can not be executed from this memory. No known workaround. 3.14 USB.1: USB_NEED_CLK is always asserted The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power Down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. The USB_NEED_CLK bit of the USBIntSt register (located at 0xE01F C1C0) is always asserted, preventing the chip from entering Power Down mode when the USBWAKE bit is set in the INTWAKE register (located at 0xE01F C144). After setting the PCUSB bit in PCONP (located at 0xE01F C0C4), write 0x1 to address 0xFFE0C008. The USB_NEED_CLK signal will now function correctly. Writing to address 0xFFE0C008 only needs to be done once after each chip reset. 3.15 USB.2: U1CONNECT signal is not functional U1CONNECT Signal (alternate function of P2.9) is part of the SoftConnect USB feature, which is used to switch an external 1.5 KW resistor under the software control. The USB U1CONNECT alternate function does not work as expected. Configure P2.9 as a GPIO pin, and use it to enable the pull-up resistor on the U1D+ pin. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 14 of 21

ES_LPC2468 Errata sheet LPC2468 3.16 USB.3: V BUS status input is not functional The V BUS signal indicates the presence of USB bus power. The V BUS status input is not functional. Configure P1.30 as a GPIO pin, and poll it to determine when V BUS goes to 0, signalling a disconnect event. 3.17 USB.4: USB_PWRDx pin(s) does not function as intended The device has a USB_PWRD1 signal for USB port 1 and a USB_PWRD2 signal for USB port 2. Both signals monitor the status of V BUS (USB bus power) and are active high signals. On the Rev -, the USB_PWRDx signals are implemented as active low signals and as a result, they are unable to monitor the status of V BUS without external inverter. An external inverter is needed on the USB_PWRDx pin(s) to be able to monitor the V BUS status. 3.18 USB.5: USB host controller hangs on a dribble bit Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. None. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 15 of 21

ES_LPC2468 Errata sheet LPC2468 3.19 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. 3.20 VBAT.2: The VBAT pin cannot be left floating The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. The VBAT should be connected to a battery or the same supply used by rest of the device (V DD(3V3) pin, V DD(DCDC)(3V3) pin). ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 16 of 21

ES_LPC2468 Errata sheet LPC2468 3.21 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset The Watchdog timer can reset the microcontroller within a reasonable amount of time if it enters an erroneous state. After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to WDFEED may cause an immediate reset. Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and the GPDMA should be disabled while feeding the Watchdog. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 17 of 21

ES_LPC2468 Errata sheet LPC2468 4. AC/DC deviations detail 5. Errata notes detail 4.1 ESD.1: The LPC2468 does not meet the 2 kv ESD requirements on the RTCX1 pin The LPC2468 is rated for 2 kv ESD. The RTCX1 pin is the input pin for the RTC oscillator circuit. The LPC2468 does not meet the required 2 kv ESD specified. Observe proper ESD handling precautions for the RTCX1 pin. 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi V DD I/O + 0.5 V. Care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 Note.2 On the LPC2468 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 18 of 21

ES_LPC2468 Errata sheet LPC2468 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 19 of 21

ES_LPC2468 Errata sheet LPC2468 7. Contents 1 Product identification.................... 3 2 Errata overview......................... 3 3 Functional problems detail................ 5 3.1 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit................... 5............................5...............................5...........................5 3.2 ADC.2: External sync inputs not operational.. 6............................6...............................6...........................6 3.3 CAN.1: Data Overrun condition can lock the CAN controller............................. 7............................7...............................7...........................7 3.4 Core.1: Incorrect update of the Abort Link register in Thumb state......................... 8............................8...............................8 Conditions:.............................8...........................8 3.5 Ethernet.1: Setting up the Ethernet interface in RMII mode............................ 9............................9...............................9...........................9 3.6 Ethernet.2: Ethernet SRAM disabled....... 10...........................10..............................10..........................10 3.7 Ethernet.3: Receive Status registers will not function correctly if RxDescriptor number is greater than 4......................... 10...........................10..............................10..........................10 3.8 Ethernet.4: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent................................. 11...........................11..............................11..........................11 3.9 Flash.1: Operating speed out of on-chip flash is restricted............................. 12...........................12..............................12.......................... 12 3.10 I2S.1: I 2 S DMA interface is non-operational. 12........................... 12.............................. 12.......................... 12 3.11 MAM.1: Under certain conditions in MAM Mode 2 code execution out of internal flash can fail.. 13........................... 13.............................. 13.......................... 13 3.12 PLL.1: PLL output (F CCO ) is limited to 290 MHz. 13........................... 13.............................. 13.......................... 13 3.13 SRAM.1: 16 kb SRAM cannot be used for code execution............................ 14........................... 14.............................. 14.......................... 14 3.14 USB.1: USB_NEED_CLK is always asserted 14........................... 14.............................. 14.......................... 14 3.15 USB.2: U1CONNECT signal is not functional 14........................... 14.............................. 14.......................... 14 3.16 USB.3: V BUS status input is not functional... 15........................... 15.............................. 15.......................... 15 3.17 USB.4: USB_PWRDx pin(s) does not function as intended............................. 15........................... 15.............................. 15.......................... 15 3.18 USB.5: USB host controller hangs on a dribble bit 15........................... 15.............................. 15.......................... 15 3.19 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device............... 16........................... 16.............................. 16.......................... 16 continued >> ES_LPC2468 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 11.1 1 July 2012 20 of 21

ES_LPC2468 Errata sheet LPC2468 3.20 VBAT.2: The VBAT pin cannot be left floating 16...........................16..............................16..........................16 3.21 WDT.1: Accessing non-watchdog APB registers in the middle of the feed sequence causes a reset 17...........................17..............................17..........................17 4 AC/DC deviations detail................. 18 4.1 ESD.1: The LPC2468 does not meet the 2 kv ESD requirements on the RTCX1 pin....... 18...........................18..............................18..........................18 5 Errata notes detail...................... 18 5.1 Note.1............................... 18 5.2 Note.2............................... 18 6 Legal information....................... 19 6.1 Definitions............................ 19 6.2 Disclaimers........................... 19 6.3 Trademarks........................... 19 7 Contents.............................. 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: ES_LPC2468

ES_LPC2470_78 Errata sheet LPC2470/78 Rev. 8.1 1 July 2012 Errata sheet Document information Info Keywords Abstract Content LPC2470/78 errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2470_78 Errata sheet LPC2470/78 Revision history Rev Date Description 8.1 20120701 Added VBAT.1. 8 20110601 Added USB.1. 7 20110420 Added Note.2. 6 20110301 Added ADC.1. 5 20100401 The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 4 20100209 Added date code info for IRC.2 3 20090814 Added IRC.2 2 20090511 Added Rev D 1 20081126 First version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC2470_78 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 2 of 13

ES_LPC2470_78 Errata sheet LPC2470/78 1. Product identification The LPC2470/78 devices typically have the following top-side marking: LPC247Xxxx xxxxxxx xxyywwr[x] The last/second to last letter in the third line (field R ) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2470/78: Table 1. Device revision table Revision identifier (R) C D Revision description Initial device revision Second device revision 2. Errata overview Field YY states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Table 2. Functional problems table Functional Short description Revision identifier Detailed description problems ADC.1 External sync inputs not operational C, D Section 3.1 Core.1 Ethernet.1 Incorrect update of the Abort Link register in Thumb state Ethernet TxConsumeIndex register does not update correctly after the first frame is sent C, D Section 3.2 C, D Section 3.3 USB.1 USB host controller hangs on a dribble bit C, D Section 3.4 VBAT.1 The VBAT pin cannot be left floating C, D Section 3.5 Table 3. AC/DC deviations table AC/DC Short description Revision identifier Detailed description deviations IRC.1 Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/- 1 % specification only at extreme temperatures. C Section 4.1 IRC.2 Accuracy of the internal RC oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of spec between 20 C and 40 C D Section 4.2 ES_LPC2470_78 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 3 of 13

ES_LPC2470_78 Errata sheet LPC2470/78 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 When the input voltage is Vi V DD I/O + 0.5 V on each of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, P1.31, P0.12, and P0.13 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. C, D Section 5.1 Note.2 On the LPC2470/78 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. D Section 5.2 ES_LPC2470_78 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 4 of 13

ES_LPC2470_78 Errata sheet LPC2470/78 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: For PCLK_ADC = 72 MHz, probability error = 12 % For PCLK_ADC = 50 MHz, probability error = 6 % For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2470_78 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Errata sheet Rev. 8.1 1 July 2012 5 of 13