Keysight Technologies FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment Application Note
02 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note Introduction The Keysight Technologies, Inc. M3602A FPGA Design Environment simplifies the development of custom processing functions for the following PXIe modules: M3100A, M3102A, M3201A, M3202A, M3300A, M3302A with -FP1 (FPGA Programming) option enabled and one of the options -K32 (Kintex-7 K325T FPGA) or -K41 (Kintex-7 K410T FPGA) for the logic. The user-friendly graphical environment simplifies the development of custom DSP for the FPGA device enabling special modes of operation or new control structures. This application note demonstrates the implementation of a signal transformation using a lookup table (LUT). The LUT is filled with the first-order Taylor s polynomial coefficients (y = ax + b) to implement a piecewise first-order linear approximation of any nonlinear function. As a simple example, this demo implements a sin(x) function into the lookup table to transform a sawtooth source signal into a sinus output signal. This demo runs on the following Keysight PXIe modular AWGs (Arbitrary Waveform Generators) with option -FP1 (enabled FPGA programming): M3201A (500 MS/s, 16 bits, 200 MHz BW), M3202A (1 GS/s, 14 bits, 400 MHz BW), M3300A and M3302A (500 MS/s, 16 bits, 200 MHz BW AWG part of the AWG + digitizer combos) The following applications are required for this demonstration: Keysight M3602A 1.91.30 or later. Keysight instrument driver 1.91.30 or later. M3201A with option -FP1 and options -K32 or -K41 (FW version: 3.04.00), or M3202A with option -FP1 and options -K32 or -K41 (FW versions 3.42.00). Later firmware version requires user firmware regeneration. Free version of the design suite Vivado HL WebPACK Edition 2015.2 (required for user firmware regeneration). (Optionally) Matlab R2013 with System Generator 14 (ISE). (Optionally) Matlab R2014 with System Generator 15 (Vivado). Demonstration Files This demonstration includes the following files: LUT.FPGAblk : M3602A block which implements the LUT functionality using M3602A IP library. look_up_table_ise.slx and look_up_table_vivado_v2.slx : Simulink projects which implement the LUT functionality. LUT.FPGAprj and LUT_MatlabXilinxSysGen.FPGAprj : M3602A projects with the LUT integration on the AWG hardware. firmware_lut_2016-05-09t16_09_38.sbp and firmware_lut_ MatlabXilinxSysGen_2016-05-09T18_45_54.sbp : generated firmware to program the Keysight module. firmware_lut_2016-06-15t17_33_40.sbp and firmware_lut_ MatlabXilinxSysGen_2016-06-15T17_38_16.sbp : generated firmware to program the Keysight M3202A AWG module. firmware_lut_2016-06-15t17_35_08.sbp and firmware_lut_ MatlabXilinxSysGen_2016-06-15T17_32_03.sbp : generated firmware to program the Keysight M3201A AWG module. CSVManagerPC.exe : User program executable file to load and read the LUT coefficients. Source code is also included. waveform_ramp_-1to1_10240p.csv : ramp waveform data file. coeff_sin.csv : sinusoidal coefficients data file which will be written to the LUT. coeff_ramp.csv : 1 to 1 signal translation coefficients data file which will be written to the LUT.
03 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note Lookup Table Implementation First of all, the lookup table functionality needs to be implemented. M3602A FPGA Design Environment provides a library of building blocks and IP Cores with the possibility to include Xilinx VIVADO/ISE projects and Xilinx CORE Generator IP Cores. It is also possible to include custom code developed in VHDL/Verilog or MATLAB/ SIMULINK. Three of these different approaches are presented here: 1. M3602A block using Keysight s M3602A Block Editor ( LUT.FPGAblk ) Figure 1.
04 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note 2. Simulink Model using Matlab R2013 and ISE System Generator 14 ( look_up_table_ise.slx ) Figure 2. 3. Simulink Model using Matlab R2014 and Vivado System Generator 15 ( look_up_table_ vivado_v2.slx ). The Simulink block diagram is the same as the one for Matlab R2013.
05 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note Hardware M3602A Project The second step is to build a hardware project with the M3602A software in order to integrate the lookup table function into the AWG module. This demonstration runs on M3201A or M3202A PXIe AWG modules with option -FP1. In order to write/read the lookup table functions, a PC port is added to the M3602A project which enables reading and writing data from/to the PC by means of the Keysight SW libraries. Two projects are presented which use different implementations of the Lookup table: 1. Hardware project with the lookup table implemented by means of a M3602A block ( LUT.FPGAprj ) Figure 3.
06 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note 2. Hardware project with the lookup table implemented using Xilinx System Generator for Matlab-Simulink ( LUT_SIM.FPGAprj ) Figure 4. The two projects are already compiled and the generated firmware files can be found in <project_file_path>/<project_name>.data/bin location.
07 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note User Firmware Generation The user can regenerate the user firmware file by opening the M3602A project and selecting Module -> Generate firmware. Figure 5. A pop-up window will appear with the last output (if a previous user firmware generation has been done). Clicking the run button, M3602A launches the FW generation and the output is placed in the folder./<project_name>.data/bin/firmware_<project_ name>_<date_and_time>.sbp (the root folder is the one containing the.fpgaprj file). Figure 6.
08 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note Demo Software Application In order to access the PC ports included in the hardware projects to load/read the lookup tables, a graphical application which uses Keysight SW libraries is included. This application, named PCportManager, allows to read and to write to/from the PC ports a simple double word or a complete CSV file. The following source code snippet from the demo application shows how reads and writes to the PC ports are programmed. Figure 7.
09 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note Running the Demonstration This section describes the necessary steps to set up and run this demonstration: 1. Insert the module M3201A or M3202A with option -FP1 inside of chassis. 2. Turn on the chassis and open Keysight SD1 SFP (ready to use Software Front Panels) for the module. 3. Program the firmware file to the FPGA-programmable AWG module: 3.1. In the M3201A or M3202A module tab, open the firmware programmer dialog from the menu FPGA->Load Firmware. Figure 8. 3.2. Select the firmware file and press Load button. Figure 9.
10 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note 4. Connect the AWG channels to an oscilloscope (or a Keysight digitizer module). In our case, we use the Keysight digitizer M3100A module. 5. Using The Keysight SD1 SFP, load the ramp waveform into the AWG and setup all the channels to output the AWG waveform. The waveform source file is waveform_ramp_-1to1_10240p.csv. 6. Load the lookup table data: 6.1. Open the PCportManager program and open the AWG module (depends on the slot number). 6.2. Enter the number of the PC port that interacts with the Lookup table function. 6.3. Load the coeff_sin.csv file and press Write button Figure 10. 7. Analyze the different outputs between channels that are connected to Lookup table function and the ones not connected.
11 Keysight FPGA Implementation of a LUT-Based Digital Pre-Distortion Using M3602A FPGA Design Environment - Application Note The image below shows the AWG outputs when the LUT firmware is programmed. The LUT is added in the data paths of channels 0 and 2, and as a consequence the sawtooth AWG signal is mapped into the sinusoidal outputs shown in magenta and yellow. While in channel 1 and 3, without the LUT, the sawtooth source signal is seen at the output without any transformation. Just for display purposes to avoid signals overlapping, channel 0 and 2 as well as 1 and 3 are configured with delay time of 100 ns. Figure 11.
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