EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA

Indian Streams Research Journal ORIGINAL ARTICLE ISSN:-2230-7850 EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA Nitin B. Kodam and P. C. Bhaskar Mtech Student, Electronics Technology, Department of Technology, Shivaji University, Maharashtra, India. P.G Coordinator, Electronics Technology, Department of Technology, Shivaji University, Maharashtra, India. Abstract: The Conventional digital circuits dissipate (ktln2) joules of heat energy when losing one bit of information. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically because the energy dissipation in any conventional system is proportional to the number of bits lost during processing of bit. The reversible circuits do not lose any bits of information because there is one-to-one mapping between inputs and outputs. In the reversible logic we can, not only get the output from input but we can also retrieve input from output. Thus we designed an Efficient Computational system of reversible circuits for an acquisition of analogy data converting into digital data, computing the data and storing a data on FPGA. The system is based on reversible logic hence it dissipate less power than the conventional logical system. The system consist of ADC unit hence the real time data can be converted to digital data and further processed by ALU unit,the required data can be stored and retrieved into 64 bit designed memory unit. Hence this can be used in many day to day real life electronics application.such as Voice recording system, automation system, monitoring system, live video streaming system, etc. Keywords: Reversible Logic, Computational system, Data acquisition unit, ALU (Arithmetic and logical) unit, Memory unit. www.isrj.net

I.INTRODUCTION The reversible logic has gathered a great attention in these recent years because of its reducing power dissipation in many applications. The reversible logic can be used in many application such as in low power CMOS design, Quantum computing machines, communication, and optical communication nanotechnology and in many for applications. In the conventional digital circuits when one bit of information is loosed then it dissipate (ktln2) joules of heat energy[1] Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically because the amount of energy loss is exactly equal to the number of bit loosed. The reversible circuit do not loss any bit of information during computation of bits hence there will be no any loss of energy. In reversible circuit there is a one-to-one mapping between inputs and outputs. In order to achieve low power designs reversible circuits are used.an Efficient Computational system design of reversible circuits consist of a data acquisition, Computation and storage unit [2][3].A reversible data acquisition system consists of a reversible analog-to digital converter which will convert analog signal into digital form, were 8:3 reversible priority encoder encodes the 8 bit digital data into 3 bits [4][5].The Reversible Computation design is basically an ALU. In which various sub modules such as adder/subtractor, multiplier and a logical unit are designed. The storage unit is 64 bit were reversible logic designed D FF is used which is used to store the computation unit outputs. On the basis of control signal, the required result is provided at the output.[6]. REVERSIBLE GATE Reversible logic has the feature to generate one to one correspondence between its input and output and a reversible gate is an n n data stripe block which uniquely maps between input vectors Iv= (I0, I1,..., In) and output vector O v= (O0, O1,..., On) denoted as Iv O v Other Basic Reversible Gate NOT Gate, Feynman / CNOT, Toffoli Gate (TG), FeynmanDouble Gate (F2G), Reversible Toffoli gate (DPG), Peres Gate (PG), Fredkin Gate (FRG), Double Peres (Dperes) Gate [9]. 2.PROPOSED SYSTEM Figure 1. Proposed computational system 2

The many existing irreversible circuits when losing one bit of information dissipates (ktln2) joules of heat energy similarly the traditional data acquisition system and Computational unit consume more power than reversible system. While designing these irreversible circuits we require more gates and almost all the millions of gates used to perform logical operations in a conventional computer are irreversible. So any lose of information will drastically increases power consumption in a conventional system. The increase in clock frequency to achieve greater speed and increase in number of transistors packed onto a chip to achieve complexity of a conventional system results in increased power consumption.these existing circuits also require more constant inputs and these circuits generate more garbage outputs than this reversible gates.to mitigate this problem we suggest the Reversible Computational system logic design which individually has less power dissipation and than the conventional system. The proposed work consist of designing data acquisition, Computational unit (ALU) and Storage system 4. HARDWARE IMPLEMENTATION The hardware designed on FPGA Spartan 3E and the system design incorporates three parts 1.Data acquisition unit 2. Computation (ALU) unit 3. Storage unit a)hardware for Computation system Here the Spartan 3E board has been used to develop the computational unit. The unit takes the input from a comparator circuit and do future reversible processing. The Reversible system consists a comparator circuit that compares the analogy input provided by potentiometer with the reference voltage and generates eight bit binary output.and this output is further encoded by reversible priority encoder that encodes this data into three bits.for Further computation with this data in (ALU) the second three bit operand is provided by three sliding switches and the operation for computation is decided by next three sliding switch. The designed eight byte reversible memory stores this computational output in eight different locations. The system also consist of two more sliding switches in which one switch is used to show the priority encoded data on to the three of eight LEDs and the last sliding switch is use for generating clock or enable signal for the system. The computation output stored in differed memory location can be retrieve by sliding switch as per the corresponding memory location address 5.SOFTWARE IMPLEMENTATION For any hardware to work correctly as desired it is necessary to embed required code written in particular language using associated software. As in this system FPGA is incorporated, software s used to write code are namely Xilinx version is used. The design consists of three blocks manly data acquisition unit, ALU unit and memory unit. For designing this system different reversible logic gates are used and the individual gates have its quantum cost. 3

6.RESULT Figure 2. Snapshot of RTL schematic of system Figure 3. Behavioral simulation results of system To acquiring the results from designed computational system varies I/P are applied and required O/P is tested.here Structural modeling has been used for programming. Figure shows the simulated waveform for each and every input and output signals of the system.this results can be used by other developer for there future work.the system quantum cost is shown in table and power of utilisation of system is 0.082W which is analysed by Xpower estimator of xilinx tool Figure 4.Xpower estimator values 4

Figure 5.Quantum cost of system 7. CONCLUSION The system consists of real time units such as analog to digital converter, ALU and memory unit. As this system is design based on reversible logic it minimize the power dissipation, so this unit in and all can be used in many real time applications such as Video recording, digital Cameras, mobiles, and in wide variety of applications domains like Nano-technology, Digital signal, processing, Cryptography, Communications. Optical computing, advanced computing 8.REFERENCES 1.Landauer R., (1961) Irreversibility and heat generation in the computing process. IBM J. Research and Development, 5(3): 183-191 2.Lafifa Jamal, Farah Sharmin,Md. Abdul Mottalib, Hafiz Md. Hasan Babu Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System IJET Volume 2 No. 1, January, 2012 3. Jun-Chao Wang I, Yu Pang I, Yang Xia A Bcd Priority Encoder Designed By Reversible Logic National Natural Science Foundation of China under the grant No. 61102075, and by the Natural Science Foundation of Chongqing under the grant No. CSTC 2011 BB 2142 and No. KJl20507. 4.Majid Haghparast, Somayyeh Jafarali Jassbi, Keivan Navi and Omid Hashemipour,' Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology World Applied Sciences Journal 3 (6): 974-978, 2008 ISSN 1818-4952 IDOSI Publications, 2008 5.Raghava Garipelly, P.Madhu Kiran, A.Santhosh Kumar,' A Review on Reversible Logic Gates and their Implementation. Volume 3, Issue 3, March 2013 6.Md. Sazzad Hossain, Md. Rashedul Hasan Rakib, Md. Motiur Rahman,A. S. M. Delowar Hossain and Md. Minul Hasan A New Design Technique Of Reversible BCD adder Based On Nmos Withpass Transistor Gates 7.Lafifa Jamal,2Farah Sharmin,3Md. Abdul Mottalib,4Hafiz Md. Hasan BabuDesign and Minimization of Reversible Circuits for a Data Acquisition and Storage System, International Journal of engineering and Technology Volume 2 No. 1, January, 2012 8.Md. Saiful Islam, Muhammad Mahbubur Rahman, Zerina begum, and Mohd. Zulfiquar Hafiz Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry- Skip Adders, MASAUM Journal of Basic and Applied Sciences, Vol. 1, No. 3, October 2009 9.Reversible Logic Gates and their Implementation ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 3, March 2013 10.Saiful Islam and Rafiqul Islam Minimization of Reversible Adder circuits, Asian Journal of Information Technology4 (12) 1146-1151, 2005. 11.Rangaraju H G et al, Low Power Reversible Parallel Binary Adder/Subtractor, International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September2010. 12.Himanshu Thapliyal and M B Srinivas, Novel Design and Reversible Logic Synthesis of Multiplexer Based Full Adder and Multipliers, Forty Eight Midwest Symposium on Circuits and Systems, vol. 2, pp. 1593 20061596. 13.Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, A Novel Multiplexer-Based Low-Power Full Adder, IEEE Transactions on circuits and systems -II: express briefs,vol. 51,No. 7 July 200414 14.Dmitri Maslov and Gerhard W. Dueck, Reversible Cascades With Minimal Garbage, IEEE 5

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