2-7-27 Computer Organization (Autonomous) UNIT IV Sections - A & D SYLLABUS The Memory System: Memory Hierarchy, - RAM and ROM Chips, Memory Address Maps, Memory Connection to, Auxiliary Magnetic Disks, Magnetic Tape, Associative Memory Hardware Organization, Match Logic, Cache Memory Associative Mapping, Direct Mapping, Set- Associative Mapping, Writing into Cache, Virtual Memory Address Space and Memory Space, Address Mapping using Pages, Associative Memory Page Table, Page Replacement. Prepared by Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. 2 INDEX Memory Organization 2-4 Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory 3 The system can be characterized with Location: Where it can be located, Processor, Internal, External. Capacity: size in terms of bytes, KB, MB, GB, etc Unit of transfer: How many bits can be moved like bytes, words, Blocks, etc. Access method: How you pick of data Sequential, Direct, Random, etc Performance: Transfer rate n terms of bps Physical type: Which material we are using like semiconductor, Magnetic, Optical, etc Physical characteristics: like power consumption, information loss, volatile, etc Organization: How it stored like continues, interleaved, etc.
2-7-27 Memory Organization 2-5 2-6 2- Memory Hierarchy Memory hierarchy in a computer system Main Memory : unit that communicates directly with the (RAM) Auxiliary Memory : device that provide backup storage (Disk Drives) Cache Memory : special very-high-speed to increase the processing speed (Cache RAM) Auxiliary Magnetic tapes Magnetic disks I/O processor Main Cache Multiprogramming enable the to process a number of independent program concurrently. 2-7 2-8 2-2 Main Memory Bootstrap Loader A program whose function is to start the computer software operating when power is turned on RAM and ROM Chips Typical RAM chip» 28 X 8 RAM : 2 7 = 28 (7 bit lines) Typical ROM chip Chip select Chip select 2 52 X 8 ROM : 2 9 = 52 (9 bit lines) 7 bit 288 RAM (a) Block diagram Memory function State of data bus 8 bit data bus Input data to RAM Output data from RAM Chip select Chip select 2 9 bit AD9 528 ROM 8 bit data bus Memory Address Map Memory Configuration : 52 bytes RAM + 52 bytes ROM» x 52 byte ROM + 4 x 28 bytes RAM Memory Address Map» Address line 9 8 RAM : - 7F RAM : 8 - FF RAM : - 7F RAM : 8 - FF» Address line ROM : 2-3FF Memory Connection to» 2 x 4 Decoder : RAM select ()» Address line RAM select : ROM select : Invert Address bus 6-9 8 7 - Decoder 3 2-7 8 9 288 RAM 288 RAM 2 288 RAM 3 288 RAM 4 288 ROM AD9 bus (b) Function table 2
text 32K2 Cache 522 2-7-27 2-9 2-2-3 Auxiliary Memory Tracks Magnetic Disk : FDD, HDD Magnetic Tape : Backup or Program Optical Disk : CDR, ODD, DVD 2-4 Associative Memory Content Addressable Memory (CAM) A unit accessed by content Block Diagram Sector / head Argument (A) Word A K C A j K j C j A n K n C n M Key (K) A Register K Register Argument Key (Mask) Match Word i C i C ij C in M i Word M = Word 2 M = Match Logic Input Associative array and logic m words n bits per word M Word m C m C mj C mn Bit Bit j Bit n Mm M = Output 2-2-2 2-5 Cache Memory Locality of Reference the references to tend to be confined within a few localized areas in Cache Memory : a fast small keeping the most frequently accessed instructions and data in the fast cache Cache cache size : 256 K byte mapping method : ) associative, 2) direct, 3) set-associative replace algorithm : ) LRU, 2) LFU, 3) FIFO write policy : ) write-through, 2) write-back Hit Ratio the ratio of the number of hits divided by the total references (hits + misses) to» hit : the finds the word in the cache (.9)» miss : the word is not found in cache ( must read main ) cache access time = ns, main access time = ns, hit ratio =.9» miss : x ns + penalty time( x ns)» 9 hit : 9 x ns Mapping The transformation of data from main to cache» ) Associative mapping» 2) Direct mapping» 3) Set-associative mapping Example of cache main : 32 K x 2 bit word (5 bit lines) cache : 52 x 2 bit word» sends a 5-bit to cache Hit : accepts the 2-bit data from cache Miss : reads the data from main (then data is written to cache) Associative mapping Cache associative Address Cache Tag field (n - k) field (k) 2 k words cache + 2 n words main Tag = 6 bit (5-9), = 9 bit Cache Coherence (Sec. 3-5) (5 bits) Argument Address 3 4 5 2 7 7 7 6 7 2 2 3 4 5 2 3 4 3
2-7-27 2-3 2-4 Tag (6 bit) - 63 (9 bit) - 5 Direct mapping cache organization 6 bits 9 bits Tag Hex Address 3F FF 32K2 Address = 5 bits = 2 bits Memory Octal Memory data 2 2 FF 522 Cache Address = 9 bits = 2 bits Tag 2 2 Direct mapping cache with block size of 8 words 64 block x 8 word = 52 cache words size 8 word block update Block Tag 7 7 3 4 5 6 5 7 8 6 6 3 Tag Block Word Tag Tag 3 4 5 2 5 6 7 2 3 4 3 4 5 4 5 6 2 6 7 Block 63 77 2 2 6 7 2 6 7 2 3 4 2 5 6 7 (b) Cache 2 6 7 Set-associative mapping : Fig. 2-5 (two-way) Direct mapping tag ( 2, ) (a) 2-5 2-6 Replacement Algorithm : cache miss or full ) LRU (Least Recently Used): On a miss, the frame that was least recently used in replaced. 2) LFU (Least Frequently Used): It looks forward in time to see which frame to replace on a cache miss. 3) FIFO (First-In First-Out): On a miss, the frame that has been in the longest is replaced. Ex: 2 3 2 5 2 6 2 5 6 3 3 6 2 4 3 Writing to Cache : Cache Coherence» ) -through» 2) -back Cache Initialization Cache is initialized» ) when power is applied to the computer» 2) when main is loaded with a complete set of programs from auxiliary valid bit» indicate whether or not the word contains valid data 2-6 Virtual Memory Virtual Memory : Auxiliary Translate program-generated (Aux. Memory) into main location» Give programmers the illusion that they have a very large, even though the computer actually has a relatively small main Intel Pentium Processor» Physical Address Lines = A - A 3 : 2 32 = 2 3 X 2 2 = 4 Giga» Logical Address = 46 bits : 2 46 = 2 4 X 2 6 = 64 Tera Auxiliary Address Space & Memory Space Address Space : Virtual Address» Address used by a programmer Program Program Memory Space : Physical Address(Location),» Address in main,2 Figure, space (N) = 24 K = 2 2 Program 2» Auxiliary Memory space (M) = 32 K = 2 5» main Memory 2, Address space N = 24K = 2 2 Memory space M = 32K = 2 5 4
2-7-27 2-7 2-8 Memory table for mapping a virtual Translate the 2 bits Virtual into the 5 bits Physical Virtual Memory table in a paged system Line number Virtual Virtual Memory maping (2 bits) table Memory table buffer Address Mapping Using Pages Address mapping Address space space fixed size Address space : K page Memory space : k block (5 bits) Main buffer Page Page Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Address space N = 8K = 2 3 Block Block 2 Block 3 Memory space M = 4K = 2 2 Table Memory page table Presence bit Block Block 2 Block 3 MBR 2-9 Associative page table Associative block number() Virtual Line number Argument Key Associative Block no. Page(Block) Replacement Page Fault : the page referenced by the is not in main» a new page should be transferred from auxiliary to main Replacement algorithm 5