Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2013-2014 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 12, 2013 Place: Room 2535 Engineering Hall Time: 7:15-8:30 PM Duration: 75 minutes PROBLEM TOPIC 1 General Questions 10 2 Test Economics 16 3 Modeling 11 4 Fault Simulation 14 5 SCOAP Computation 10 6 Test Generation - Comb 14 7 Test Generation - Seq 10 8 Checking Sequence 15 TOTAL 100 POINTS SCORE Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): First Name: ID Number: 1 Fall 2013 (Lec: Saluja)
1. (10 points) General Questions Answer the following in brief and to the point. You must not use more than two to three lines of explanation where an an explanation is needed. (a) (1 point) Memory usage by a concurrent fault simulator is smaller than the memory usage by a deductive fault simulator. Answer True of False. (b) (1 point) Memory usage by a serial fault simulator is smaller that the memory usage by a deductive fault simulator. Answer True or False. (c) (2 point) A gate level fanout-free realization of a circuit has 20 inputs and 2 outputs. What is the maximum number of tests we will need to test this circuit. Hint: think checkpoints. (d) (2 points) If a fault f 1 dominates fault f 2, and the fault f 2 dominates a fault f 3. which of these faults can be deleted to reduce the fault list for fault detection. Give reason. (e) (1 point) Method of Boolean Difference can be used to determine if a fault in a combinational circuit is redundant. Answer True or False. (f) (1 points) Easy/Hard heuristic can only be used in PODEM during backtrace and it can not be used during D-drive. Answer True or False. (g) (1 points) If SCOAP CC0 value of a line in a circuit is 25 then it means that this line can always be set to 0 by assigning appropriate values to the inputs to the circuit. Answer True or False. (h) (1 points) If SCOAP CC1 value of a line in a circuit is inf then it means that this line can never be set to 1 no matter what values are assigned to the inputs to the circuit. Answer True or False. 2 Fall 2013 (Lec: Saluja)
2. (16 points) Test Economics A chip manufacturer is to produce ICs in a very large quantity and it has worked out its cost as follows:. Cost of design (amortized on each IC) = $ 5.00. Production cost of each IC = $ 1.00. Test cost for each IC = $ 2.00 Test as filter has the following properties based on the quality of test:. 95% of the truly good devices will pass the test.. 96% of the bad devices will fail the test. Based on the technology used, it is known that the true yield of ICs being fabricated is 80%. Now answer the following questions: (a) (1 point) What percentage of good devices will fail the test? (b) (1 point) What percentage of bad devices will pass the test? (c) (3 point) Determine the Yield of the above devices. You must show your work. (d) (3 point) Determine the Defect Level (DL) of the above devices. You must show your work and write the value of defect level in parts per million? 3 Fall 2013 (Lec: Saluja)
(e) (3 point) Determine the Yield loss due to above testing. You must show your work. (f) (5 points) Assuming that the manufacturer will have to pay $50.00 for every bad device sold to a customer (because customer will return a bad IC), at what price should an IC be sold so that the manufacture breaks even. 4 Fall 2013 (Lec: Saluja)
3. (11 points) Modeling A library cell of a design library realizes a function f(a,b,c) = A. B. C. A designer, makes a mistake, while building this cell and makes incorrect connections and realizes the function A. C. B. Answer the following and you must show your work for full credit. (a) (3 points) Write all primitive cubes of f. (b) (4 points) Write two propagation D-cubes of f: i. a propagation D cube with at least one of the inputs to be logic 1: ii. a propagation D cube with at least one of the inputs to be logic 0: (c) (4 points) Write two primitive cubes of failure for the mistake specified in the problem description. 5 Fall 2013 (Lec: Saluja)
4. (14 points) Fault Simulation - Deductive The circuit of Fig 1 is to be simulated using the pattern given below: pattern = A B C D E F = 0 1 1 1 1 0 A B u C j k 1 1 1 l p D h o s E i m n t r F Figure 1: Circuit for deductive fault simulation The fault list that needs to be simulated for this pattern is given below: A/1 B/1 C/0 D/0 E/0 F/1 h/0 i/0 k/0 n/0 s/0 Note: During fault simulation, list associated with any line or gate must not contain a fault that is not in the above list. (a) (2 points) Indicate the true signal values in every gate of the circuit. For your convenience, I have already provided values in one of the gates. 6 Fall 2013 (Lec: Saluja)
(b) (10 points) In the table below, provide the deductive fault lists associated with every line in the circuit. Again to get you started, I have already completed the entries associated with all primary input lines. Line Name fault list Line Name fault list A A/1 l B - - m C C/0 n D D/0 o E E/0 p F F/1 r h s i t j u k (c) (2 points) Now, indicate which of the faults will be detected and at which output. Faults detected at output u: Faults detected at output t: 7 Fall 2013 (Lec: Saluja)
5. (10 points) SCOAP Computation Consider the circuits shown in Figure 2 for SCOAP computations. This circuit is a part of a larger combinational circuit. A (30,15) G1 (40,31) 30 Z1 B C B1 B2 (70,13) G2 D G12 (19,73) (38,46) (105,20) G3 (, ) 50 Z2 Figure 2: Combinational Circuit for SCOAP Computations In this circuit some of the SCOAP values, i.e the CC0, CC1 and CO values, are already computed and shown in the circuit. The notation used is (CC0,CC1) CO. While many other values need to be computed. You are to compute all the remaining values, i.e. CC0, CC1 and CO values which are not shown in the figure. Enter these values in the table below. I have already entered the values shown in the figure in this table, therefore you need only to complete the blank entries. Line Controllability Observability Line Controllability Observability CC0 CC1 CO CC0 CC1 CO A 30 15 G1 B G12 B1 G2 38 46 B2 Z1 40 31 30 C 70 13 G3 105 20 D 19 73 Z2 50 8 Fall 2013 (Lec: Saluja)
6. (14 points) Combinational Test Generation A PODEM like test generator is used to generate a test of for the line 20 s-a-1 in the circuit of Figure 3. 1 A B C D 4 5 8 6 3 7 10 9 11 12 13 14 15 16 19 20 21 22 24 25 26 2 27 28 29 E F 30 31 17 23 18 Figure 3: Circuit for test generation It is still in the process of test generation and has made the assignments at some of the primary inputs as follows and in the order shown: B = 1 C = 0 C = 1 A = 1 A = 0 (a) (3 points) Construct the decision tree for the completed work this far. 9 Fall 2013 (Lec: Saluja)
(b) (7 points) In the table below indicate all the implications of the above assignments and the D frontier. I have already filled in a few implications for some signal lines. Assignments Implications D frontier Comments B=1, C=1, A=0 Lines 2, 5, 8 are 1; Lines 1, 3, 4, 6 are 0; (c) (4 points) If the next assignment is D = 1, will that cause a back track or lead to a next new assignment? Show your work in the table above. 10 Fall 2013 (Lec: Saluja)
7. (10 points) Sequential Test Generation Consider the sequential circuit given in Figure 4 containing two D-type flip-flops and a logic gate. A FF1 B FF2 D Q D Q Z Q Q Figure 4: Figure for a sequential circuit (a) (2 points) In the Figure 5 I have provided two FFs and a box for the combinational part of the circuit. Redraw the combinational part of circuit in the box and make all the connections. Note the FF labels: FF2 is drawn above FF1. B A Z Q D FF2 Q D FF1 Figure 5: Figure for combinational part of the sequential circuit 11 Fall 2013 (Lec: Saluja)
(b) (4 points) Draw the time frame expansion of this circuit for three time frames. Clearly draw the timeframe boundaries and label them. Mark the inputs, outputs, pseudo primary inputs and pseudo primary outputs appropriately in the model you draw. (c) (4 points) Derive a test sequence that will detect a stuck-at 1 fault at the output of OR gate. You can use any method you like. Use the time frame expansion drawn by you to show clearly the values of the inputs and the time the values are applied. You must also indicate the time the fault is detected and what will be the expected output and the output of the faulty circuit for the input sequence obtained by you. 12 Fall 2013 (Lec: Saluja)
8. (15 points) Checking Experiment State table of a finite state machine with four states, A, B, C, and D; and a binary input alphabet consisting of 0, and 1; is given in Table 1. Table 1: State Machine for Problem 8 Input 0 1 A A/0 C/0 B A/1 D/1 C B/0 D/0 D B/1 D/1 Now consider applying the sequence 0 1 1 1 to this machine. Note when this sequence is applied the initial state of the machine is not known. (a) (2 points) What will be the output sequence. When the output is not known write an X for that. (b) (2 points) What will be the state sequence. When the state is not known just indicate the state ambiguity. Assume before the sequence is applied the state ambiguity is (ABCD). (c) (1 points) Does this machine initialize to some state during the application of the above sequence. (d) (2 points) Find a shortest synchronizing sequence for this machine. You must show your work otherwise no points will be awarded. 13 Fall 2013 (Lec: Saluja)
(e) (4 points) Now consider a fault which causes the above machine to change to the state table shown in Table 2. Note that there is only one change due the fault and that is next state of B with input 0 is C instead of A. Table 2: State Machine of the Faulty Machine for Problem 8 Input 0 1 A A/0 C/0 B C/1 D/1 C B/0 D/0 D B/1 D/1 Will the above sequence detect this fault? You must show your work otherwise no credit will be given. (f) (4 points) Append a shortest possible sequence to the above sequence to detect the fault described above. Again, you must show your work otherwise no credit will be given. 14 Fall 2013 (Lec: Saluja)