Bluetooth Module - Part ode LM-0 Bottom view Top view ontents:. Device Overall Description. Features. Applications. Bluetooth Block Diagram. Power onsumption. 7. 8. Schematic 9. Pinout for module Side view LM0 Page of
Device Overall Description The LM0 is Bluetooth.0 + EDR module with external SMA connector. The Bluetooth function is based on SR Blueore 0 chipset which implements full speed lass bluetooth operation with a support of upto simultaneous connections while running full Bluetooth stack in the module. The interface to the host system is UART. This module is suitable for serial port application which require 00-00 m range (depending on the antenna) and comes with Bluetooth.0+EDR compliant SPP firmware. Features - Used in LM Technologies Ltd Bluetooth Ethernet access point (LM00) - SR Blueore chipset - Bluetooth.0 + EDR support - Full bluetooth data rate upto Mbps - Supports simultaneous SPP connections while running complete bluetooth stack in the module - External SMA antenna connector - Hexadecimal ommand set available for module configuration -.0 to. V operation - SPP firmware - Support 80. o-existence - RoHS ompliant - Low Power onsumption: Hold, Sniff, Park, Deep Sleep mode - Small Outline: x x mm (without SMA onnector), x x mm (with SMA connector) - Interoperability with laptops, PDAs, Phones etc Applications - Serial ommunications - Serial Device Server Bluetooth Block Diagram H/W Flow ontrol External SMA Antenna SMA onnector B0 lass Module UART SPI Host 0 pin Header PIO VDD LM0 Page of
Power onsumption Absolute Maximum Ratings Parameter Min. Max. Unit Storage Temperature - 0 + 8 Supply Voltage (VDD).7. D V Supply Voltage (PV).0. DV Other Pin Voltage Vss-0. VDD+0. DV Recommended Operating onditions Parameter Min. Max. Unit Temperature -0 +70 Supply Voltage for UART.0. DV Supply Voltage for USB.0. DV General Electrical Specification Parameter Description Min. Typ. Max. Unit arrier Frequency.0.80 GHz RF Output Power Measured in 0ohm. 8 dbm Rx Sensitivity - -88-8 dbm Load Impedance No abnormal Oscillation : Input Low Voltage RESET,UART,GPIO,PM -0.0-0.80 DV Input High Voltage RESET,UART,GPIO,PM 0.7VDD - VDD+0. DV Output Low Voltage UART,GPIO,PM - - 0.0 DV Output High Voltage UART,GPIO,PM VDD-0. - - DV Average urrent onsumption Receive DM ma LM0 Page of
Pinout and Definition for Header J VDD TXD RXD SPISB RSTL PIO SPIMOSI SPILK DTR GND 7 8 9 0 Pin No Pin name Direc on Descrip on Signal Level VDD Input D Input ( ~.V) Power TXD Output UART Data output TTL RXD Input UART Data Input TTL SPISB Input SPI hip Select TTL RSTL Input Reset (Ac ve Low) TTL PIO Input/output Programmable IO TTL 7 SPIMOSI Input SPI Master Output Slave Input TTL 8 SPILK Input SPI lock TTL 9 DTR Output UART Data Terminal Ready TTL 0 GND Ground Ground Pinout and Definition for Header J PIO RTS PIO PIO PIO7 TS SPIMISO PIO PIO9 PIO8 7 8 9 0 Pin No Pin name Direc on Descrip on Signal Level PIO Input/output Programmable IO TTL RTS Output UART Request to Send TTL PIO Input/output Programmable IO TTL PIO Input/output Programmable IO TTL PIO7 Input/output Programmable IO TTL TS Input UART lear to Send TTL 7 SPIMISO Output SPI Master Input Slave Output TTL 8 PIO Input/output Programmable IO TTL 9 PIO9 Input/output Programmable IO TTL 0 PIO8 Input/output Programmable IO TTL LM0 Page of
LM0 Page of Schematic 00 00 00 00 00 P0 P FLMD0 P0 P0 P0 P P P P P P P7 P0 P0 R00 L00 UART_IN UART_OUT UART_RTS UART_TS SPIMOSI SPIMISO SPILK UART_DTR UART_OUT UART_IN RESET_L UART_DTR UART_RTS UART_TS SPIMOSI SPILK SPIMISO PIO PIO PIO PIO PIO PIO PIO PIO7 PIO PIO8 SPISB PIO PIO9 RESET_L SPISB PIO PIO7 PIO8 PIO9 V V V V 00N U LM07 7 8 9 0 7 8 9 0 7 8 9 0 7 8 9 0 AIO0 AIO PIO0 PIO PIO PIO PIO GND PIO PIO PIO7 PIO8 PIO9 RESET V GND GND USBDP USBDN PM_SYN PM_IN PM_OUT PM_LK UART_RX UART_TX UART_RTS GND UART_TS SPIMOSI SPISB SPILK SPIMISO PIO PIO0 RFIO GND GND GND7 +V_PA GND0 R 0K 00N J 0 way 7 8 9 0 J 0 way 7 8 9 0 L N7 P P J way J SMA END MOUNT H 00N
Pinout for module PinNo. PinName PinType Description GND GND ommon ground P V Power Power Amp. Power Supply(.V) AIO (0) Bi -directional Programmable I/O terminal, KHz sleep clock input AIO () Bi -directional Programmable I/O terminal P IO (0) Bi -directional Programmable I/O terminal, RX Enable PIO () Bi -directional Programmable I/O terminal, TX Enable 7 PIO () Bi -directional Programmable I/O terminal, USB_PULL_UP, LK_REQ _O UT 8 PIO () Bi -directional Programmable I/O terminal, USB_WAK E_UP, LK_REQ _IN 9 PIO () Bi -directional Programmable I/O terminal, USB_O N, BT_Priority/ h_ lk output for co-existence signalling 0 GND GND ommon ground PIO () Bi -directional Programmable I/O terminal, USB_DETA H, BT_Active output for co - existence signalling PIO () Bi -directional Programmable I/O terminal, LK_REQ, WLAN_Active/ h_data input for for co -existence signalling PIO (7) Bi -directional Programmable I/O terminal PIO (8) Bi -directional Programmable I/O terminal PIO (9) Bi -directi onal Programmable I/O terminal RESET MO S input Reset input of module, Active low reset 7 V Power Module power supply input 8 GND GND ommon ground 9 GND GND ommon ground 0 USB_DP Bi -directional USB data plus USB_DN Bi -directional USB da ta minus P M_SYN Bi -directional Synchronous data sync P M_IN MO S input Synchronous data input PM_O UT MO S output Synchronous data output P M_ LK Bi -directional Synchronous data clock UART_RX MO S input UART data input 7 UART_TX MO S output UART data output 8 UART_RTS MO S output UART request to send(active low) 9 GND GND ommon ground 0 UART_ TS MO S input UART clear to send(active low) SPI_MO SI MO S input Serial Peripheral Interface data input SPI_ SB MO S input hip select for Synchronous Serial Interface(active low) SPI_ LK MO S input Serial Peripheral Interface clock SPI_MISO MO S output Serial Peripheral Interface data output PIO () Bi -directional Programmable I/O terminal PIO (0) Bi -directional Programmable I/O terminal 7 RF_IO Analogue Antenna interface 8 GND GND ommon ground LM0 Page of