Outline EES 5 omponents and Design Techniques for Digital Systems ec 9 Putting it all together 9257 David uller Electrical Engineering and omputer Sciences University of alifornia, erkeley http://www.eecs.berkeley.edu/~culler http://inst.eecs.berkeley.edu/~cs5 Toptobottom What have we covered so far? ombo ock example FSM to logic Mapping to FPGs nnouncements ounters revisited nother example nt rain 9/25/7 EES5 fa7 9/25/7 EES5 fa7 2 Digital design as we ve seen it System specification (in words) T T Datapath specification ontroller specification ec 3,8: ogic ec 67: Modeling FSMs omb. logic operations FSM generation ec 4: HDs, abs ec 5,6,7: FSM Verilog dataflow STT / STD / Encoding ec 2, 3: MOS, FPG ec 3,8: ogic min. Gates / UTs ogic: nextstate/outputs ec 4: HD, abs Verilog behavior ec 2, 3: MOS, FPG Gates / UTs / FF 9/25/7 EES5 fa7 3 Where are we now? (Synchronous) Sequential systems Given datapath and control specifications Generate comb. logic for datapath» Minimize logic for efficient implementation Generate FSM for controller» hoose implementation, encoding» Generate logic for nextstate and output Describe datapath and controller in Verilog» structure, dataflow and behavior» Map onto gates or UTs Seems like a good point to test your understanding! 9/25/7 EES5 fa7 4
epresentation of digital designs Physical devices (transistors, relays) Switches Truth tables oolean algebra Gates Waveforms Finite state behavior egistertransfer behavior oncurrent abstract specifications scope of S 5 more depth than 6 focus on building systems ogic Functions and oolean lgebra ny logic function that can be expressed as a truth table can be written as an expression in oolean algebra using the operators: ', +, and X Y X Y X Y X' X' Y X Y X' Y' X Y X' Y' ( X Y ) + ( X' Y' ) ( X Y ) + ( X' Y' ) X = Y 9/25/7 EES5 fa7 5 oolean expression that is true when the variables X and Y have the same value X, Y are oolean algebra variables and false, otherwise 9/25/7 EES5 fa7 6 Waveform View of ogic Functions Just a sideways truth table ut note how edges don't line up exactly It takes time for a gate to switch its output! time n algebraic structure n algebraic structure consists of a set of elements binary operations { +, } and a unary operation { ' } such that the following axioms hold:. set contains at least two elements, a, b, such that a b 2. closure: a + b is in a b is in 3. commutativity: a + b = b + a a b = b a 4. associativity: a + (b + c) = (a + b) + c a (b c) = (a b) c 5. identity: a + = a a = a 6. distributivity: a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c) 7. complementarity: a + a' = a a' = change in Y takes time to "propagate" through gates 9/25/7 EES5 fa7 7 9/25/7 EES5 fa7 8
Timing Methodologies (cont d) Definition of terms clock: periodic event, causes state of storage element to change; can be rising or falling edge, or high or low level setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th) input clock T su T h there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized data clock data clock D Q stable changing D Q 9/25/7 EES5 fa7 9 xioms & theorems of oolean algebra Identity. X + = X D. X = X Null 2. X + = 2D. X = Idempotency: 3. X + X = X 3D. X X = X Involution: 4. (X')' = X omplementarity: 5. X + X' = 5D. X X' = ommutativity: 6. X + Y = Y + X 6D. X Y = Y X ssociativity: 7. (X + Y) + Z = X + (Y + Z) 7D. (X Y) Z = X (Y Z) 9/25/7 EES5 fa7 xioms and theorems of oolean algebra (cont d) Distributivity: 8. X (Y + Z) = (X Y) + (X Z) 8D. X + (Y Z) = (X + Y) (X + Z) Uniting: 9. X Y + X Y' = X 9D. (X + Y) (X + Y') = X bsorption:. X + X Y = X D. X (X + Y) = X. (X + Y') Y = X Y D. (X Y') + Y = X + Y Factoring: 2. (X + Y) (X' + Z) = 2D. X Y + X' Z = X Z + X' Y (X + Z) (X' + Y) oncensus: 3. (X Y) + (Y Z) + (X' Z) = 3D. (X + Y) (Y + Z) (X' + Z) = X Y + X' Z (X + Y) (X' + Z) xioms and theorems of oolean algebra (cont ) de Morgan's: 4. (X + Y +...)' = X' Y'... 4D. (X Y...)' = X' + Y' +... generalized de Morgan's: 5. f'(x,x2,...,xn,,,+, ) = f(x',x2',...,xn',,,,+) establishes relationship between and + 9/25/7 EES5 fa7 9/25/7 EES5 fa7 2
ecall: What makes Digital Systems tick? ombinational ogic Sequential ogic Implementation Models for representing sequential circuits Finitestate machines (Moore and Mealy) epresentation of memory (states) hanges in state (transitions) clk time Design procedure State diagrams Implementation choice: counters, shift registers, FSM State transition table State encoding ombinational logic» Next state functions» Output functions 9/25/7 EES5 fa7 3 9/25/7 EES5 fa7 4 bstraction of State Elements Divide circuit into combinational logic and state ocalize feedback loops and make it easy to break cycles Implementation of storage elements leads to various forms of sequential logic Forms of Sequential ogic synchronous sequential logic state changes occur whenever state inputs change (elements may be simple wires or delay elements) Synchronous sequential logic state changes occur in lock step across all storage elements (using a periodic waveform the clock) Inputs ombinational ogic Outputs State Inputs Storage Elements State Outputs 9/25/7 EES5 fa7 5 lock 9/25/7 EES5 fa7 6
FSM epresentations States: determined by possible values in sequential storage elements Transitions: change of state lock: controls when state can change by controlling storage elements In = In = In = In = Sequential ogic Sequences through a series of states ased on sequence of values on input signals lock period defines elements of sequence Example: FSM Design ombo lock ombination lock value 2 3 multiplexer comparator control datapath not new controller open/ not clock not ontroller E S S2 S3 OPEN open = =2 =3 9/25/7 EES5 fa7 7 9/25/7 not new not new EES5 fa7not new 8 ombo lock controller implementation Implementation of the controller control new controller open/ clock control special circuit element, called a register, for remembering inputs when told to by clock new comb. logic open/ state clock 9/25/7 EES5 fa7 9 ombo ock State Encoding new state nstate open/ S S S S E S S2 2 S2 S2 2 S2 E S2 S3 3 Symbolic states S3 S3 3 and outputs S3 E S3 OPEN OPEN OPEN open E E One possible encoding Mux control: oncrete encoding out= =, 2 =, 3 = (preestablished) not not not State encoding: S =, S2 =, S3 =, out= out= out= OPEN =, Error = out= = = = Output encoding: losed =, Open = 9/25/7 not new EES5 not fa7new not new 2
FSM implementation Example: ombo ock Steps for the hardware designer: Word specification FSM design Encoding Verification! t this point, hand over to synthesis tools: Describe FSM behavior in Verilog Synthesize controller Good encoding etter performance Fewer state bits Possibility of state minimization Tools also try to figure this out 9/25/7 EES5 fa7 2 (r) new (n) (e) state (s 2 s s ) nstate (n 2 n n ) (m m ) open (o) Next state and output logic nextstate (n2 n n): n2 = ~r (n e s s + s2) n = ~r (n e s + e s + ~n s + s2) n = r + s2 + n e s + ~n s outputs (m, m): m = s m = s open (o): o = s2 Take advantage of Ds! How do we get these: Kmaps? Tools For this example, go through the logic synthesis steps Espresso (ideally, tools take care of all this) 9/25/7 EES5 fa7 Synplicity 22 r ogic Implementation (on P) n e s2 s s Next state and output logic nextstate (n2 n n): n2 = ~r (n e s s + s2) n = ~r (n e s + e s + ~n s + s2) n = r + s2 + n e s + ~n s outputs (m, m): m = s m = s lternate logic implementations Ps Multilevel circuits ibrary of gates for implementation technology UTs on FPG open (o): o = s2 n2 n n m m o s2 s s 9/25/7 EES5 fa7 23 9/25/7 EES5 fa7 24
lternate ogic epresentations * Theorem: ny oolean function that can be expressed as a truth table can be written as an expression in oolean lgebra using ND, O, NOT. not unique? oolean Expression [convenient for manipulation] Truth Table unique gate representation (schematic) 9/25/7 EES5 fa7 25? To design is to represent [close to implementaton] How do we convert from one to the other? not unique hoosing different realizations of a function Z twolevel realization (we don't count NOT gates) multilevel realization (gates with fewer inputs) XO gate (easier to draw but costlier to build) 9/25/7 EES5 fa7 26 Which realization is best? educe number of inputs literal: input variable (complemented or not)» approximate cost of logic gate is 2 transistors per literal Fewer literals means less transistors smaller circuits Fewer inputs implies faster gates Fanins (# of gate inputs) are limited in some technologies educe number of gates Fewer gates (and the packages they come in) means smaller circuits educe number of levels of gates Fewer level of gates implies reduced signal propagation delays How do we explore tradeoffs between increased circuit delay and size? utomated tools to generate different solutions ogic minimization: reduce number of gates and complexity ogic optimization: reduction while trading off against delay lternate Implementation: ontroller based on Shift egister Previous implementation omb. logic as gates (P) State bits in latches lternative Shift reg to manipulate state Simplify comb. logic in clock comb. logic state new D n D *** nbit shift register clk load shft open out 9/25/7 EES5 fa7 27 9/25/7 EES5 fa7 28
(r) ontroller using Shift egister new (n) (e) state (s 3 s 2 s s ) nstate (n 3 n 2 n n ) (m m ) not new not new not new 9/25/7 EES5 fa7 29 open (o) Onehot encoding scheme: state transition is a shift right Mux control: =, 2 =, 3 = (preestablished) State encoding: S =, S2 =, S3 =, OPEN =, Error = Output encoding: losed =, Open = not not not E S S2 S3 OPEN open = =2 =3 ombo lock controller on shift reg in clock comb. logic new state 4bit shift register open out clk load shft ~out new open 4bit shift register: [D3, D2, D, D] [,,, ] Shift eg ontroller clk clock shft (~out new) (~ new ~out ) load in out open Mux control (read register contents): m = ~s3 m = ~s2 clock new not new not new not new 9/25/7 EES5 fa7 3 not not not E S S2 S3 OPEN open = =2 =3 How does the combo lock look on an FPG? Inside the FPG atches implement shift register (chain of 4 latches) UTs ombinational logic for out and control outing fabric onnect logical nets between s Network of ombinational logic blocks, memory and I/O rich interconnect network special units multipliers, carrylogic s 3 or 4input look up table (UT) implements combinational logic functions egister optionally stores output of UT ogic on FPG onfigure UTs (table of entries) onfigure latches in Program interconnect INPUTS ogic lock 4UT FF latch set by configuration bitstream OUTPUT 9/25/7 EES5 fa7 3 4input "look up table" 9/25/7 EES5 fa7 32
UT as general logic gate n nlut as a direct implementation of a function truthtable. Each latch location holds the value of the function corresponding to one input combination. Example: 2lut INPUTS ND O Implements any function of 2 inputs. How many of these are there? How many functions of n inputs? Example: 4lut INPUTS F(,,,) F(,,,) F(,,,) F(,,,) store in st latch store in 2nd latch 9/25/7 EES5 fa7 33 User Programmability atchbased (Xilinx, ltera, ) + reconfigurable volatile relatively large. latch atches are used to:. make or break crosspoint connections in the interconnect 2. define the function of the logic blocks 3. set user options:» within the logic blocks» in the input/output blocks» global /clock onfiguration bit stream can be loaded under user control: ll latches are strung together in a shift chain: 9/25/7 EES5 fa7 34 4UT Implementation onfiguring s 6 latch latch latch latch INPUTS 6 x OUTPUT nbit UT is implemented as a 2 n x memory: inputs choose one of 2 n memory locations. memory locations (latches) are normally loaded with values from user s configuration bit stream. Inputs to control are the inputs. esult is a general purpose logic gate. nut can implement any function of n inputs! atches programmed as part of configuration bitstream inputs 2 INPUTS NND gate in FPG 2 FF ogic lock 3UT FF out latch 3input "look up table" inputs 2 2 set by configuration bitstream OUTPUT Nextstate bit in FPG FF out 9/25/7 EES5 fa7 35 out = ~( 2 3) nextstate = 2 xor 9/25/7 EES5 fa7 36
onfiguring outes Sequential Systems more examples 2 2 FF 2 2 FF eat the combo lock example to death Direct FSM implementation Shift register» Multiple logic representations» gates to UTs Up next few quick counter examples nother design problem nt rain out = ~( 2 3) nextstate = 2 xor 9/25/7 EES5 fa7 37 in 9/25/7 EES5 fa7 38 nnouncements/eminders First mid term Thursday 9/27 No notes ( to discuss) eview materials are in the HW4 eview session tonight 8 642WK (9255) Trying to make the exams routine Feel free to approach us with questions No discussion Thurs, yes friday ab 5 Where s the music? Normal lab lecture on Friday an ny Sequential System be epresented with a State Diagram? Shift egister Input value shown on transition arcs Output values shown within state node IN K OUT OUT2 OUT3 D Q D Q D Q 9/25/7 EES5 fa7 39 9/25/7 EES5 fa7 4
ounter Example Shift egister Input determines next state In 2 3 N N2 N3 N := In N2 := N3 := 2 OUT OUT2 OUT3 IN DQ DQ DQ K 9/25/7 EES5 fa7 4 ounters are Simple Finite State Machines ounters Proceed thru welldefined state sequence in response to enable Many types of counters: binary, D, Graycode 3bit upcounter:,,,,,,,,,... 3bit downcounter:,,,,,,,,,... 3bit upcounter module binary_upcntr (q, clk) inputs clk; outputs [2:] q; reg [2:] q, p; always @(q) // Next state case (q) 3 b: p = 3 b; 3 b: p = 3 b; 3 b: p = 3 b; endcase always @(posedge clk) // Update state q <= p; 9/25/7 EES5 endmodule fa7 42 More omplex ounter Example omplex ounter epeats five states in sequence Not a binary number representation Step : Derive the state transition diagram ount sequence:,,,, Step 2: Derive the state transition table from the state transition diagram More omplex ounter Example (cont d) Step 3: Kmaps for Next State Functions + X X X + X X X + X X X Present State Next State + + + note the don't care conditions that arise from the unused state codes 9/25/7 EES5 fa7 43 + := + := ' + '' + := ' 9/25/7 EES5 fa7 44
SelfStarting ounters (cont d) ederiving state transition table from don't care assignment + + + SelfStarting ounters Startup States t powerup, counter may be in an unused or invalid state Designer must guarantee it (eventually) enters a valid state Selfstarting Solution Design counter so that invalid states eventually transition to a valid state May limit exploitation of don't cares Present State Next State + + + 9/25/7 EES5 fa7 45 implementation on previous slide 9/25/7 EES5 fa7 46 Final Example: nt rain (Ward, MIT) nt ehavior Sensors: touching wall ctuators: Goal: Strategy: and antennae, if in F forward step, T/T turn left/right slightly find way out of maze keep the wall on the right : Following wall, touching Go forward, turning left slightly : Following wall, not touching Go forward, turning right slightly : reak in wall Go forward, turning right slightly D: Hit wall again ack to state E: Wall in front Turn left until... F:...we are here, same as state OST: Forward until we touch something G: Turn left until... 9/25/7 EES5 fa7 47 9/25/7 EES5 fa7 48
Designing an nt rain Synthesizing the nt rain ircuit State Diagram OST (F) + E G (T) (T, F) + (T, F) (T, F) Encode States Using a Set of State Variables rbitrary choice may affect cost, speed Use Transition Truth Table Define next state function for each state variable Define output function for each output Implement next state and output functions using combinational logic 2level logic (OM/P/P) Multilevel logic Next state and output functions can be optimized together 9/25/7 EES5 fa7 49 9/25/7 EES5 fa7 5 Transition Truth Table Using symbolic states and outputs OST (F) + E/G (T) + (T, F) state next state outputs OST OST F (T, F) (T, F) OST E/G F OST E/G F T, F T, F E/G T, F T, F T, F............... 9/25/7 EES5 fa7 5 Synthesis 5 states : at least 3 state variables required (X, Y, Z) State assignment (in this case, arbitrarily chosen) state next state outputs X,Y,Z X', Y', Z' F T T.............................. it now remains to synthesize these 6 functions OST E/G 9/25/7 EES5 fa7 52
Synthesis of Next State and Output Functions state inputs next state outputs X,Y,Z X +,Y +,Z + F T T e.g. T = X + Y Z X + = X + Y Z = T ircuit Implementation Outputs are a function of the current state only Moore machine output logic next state logic urrent State Next State X + Y + Z + X Y Z F T T 9/25/7 EES5 fa7 53 9/25/7 EES5 fa7 54 Verilog Sketch module ant_brain (F, T, T,, ) inputs, ; outputs F, T, T; reg X, Y, Z; assign F = function(x, Y, Z,, ); assign T = function(x, Y, Z,, ); assign T = function(x, Y, Z,, ); always @(posedge clk) begin X <= function (X, Y, Z,, ); Y <= function (X, Y, Z,, ); Z <= function (X, Y, Z,, ); end endmodule 9/25/7 EES5 fa7 55 Don t ares in FSM Synthesis What happens to the "unused" states (,, )? Exploited as don't cares to minimize the logic If states can't happen, then don't care what the functions do if states do happen, we may be in trouble (F) + + (T) (T, F) (T, F) (T, F) nt is in deep trouble if 9/25/7 it gets in this state EES5 fa7 56
State Minimization nt rain evisited Fewer states may mean fewer state variables Highlevel synthesis may generate many redundant states Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same ny equivalent states? OST (F) + E/G (T) + (T, F) Two conditions for two states to be equivalent: ) Output must be the same in both states 2) Must transition to equivalent states for all input combinations (T, F) (T, F) 9/25/7 EES5 fa7 57 9/25/7 EES5 fa7 58 New Improved rain New rain Implementation Merge equivalent and states ehavior is exactly the same as the 5state brain We now need only 2 state variables rather than 3 OST (F) + E/G (T) / (T, F) + (T, F) state inputs next state outputs X,Y X',Y' F TT F X Y X+ Y X T X Y Y+ Y X T X Y 9/25/7 EES5 fa7 59 9/25/7 EES5 fa7 6
Sequential ogic Implementation Summary Models for representing sequential circuits bstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Design hierarchy code registers datapath multiplexer comparator system state registers control combinational logic register logic switching networks 9/25/7 EES5 fa7 6 9/25/7 EES5 fa7 62 Final Word: locking Vs Nonlocking Two types of procedural assignments locking Nonlocking Good luck on the Midterm Why do we need them Express parallelism (not straight line ) Synchronous system ll flipflops clock data simultaneously How do we express parallelism in this operation? 9/25/7 EES5 fa7 63 9/25/7 EES5 fa7 64
Simple Shift egister The ircuit reg a, b, c; begin a = ; b = a; c = b; end Probably not what you want! reg a, b, c; a = ; b = a; c = b; What order does this run? a b c reg a, b, c; begin a = ; b = a; c = b; end reg a, b, c; begin a <= ; b <= a; c <= b; end This works reg a, b, c; a <= ; b <= a; c <= b; This works too 9/25/7 EES5 fa7 65 a b c reg a, b, c; begin a <= ; b <= a; c <= b; end Nonlocking: HS computed at beginning of execution instance. HS updated after all events in current instance computed. 9/25/7 EES5 fa7 66