Frequently asked questions from the previous class survey CS 7: OPERATING SYSTEMS [MEMORY MANAGEMENT] Shrideep Pallickara Computer Science Colorado State University TLB Does the TLB work in practice? n Hit time:.5 - clock cycle n Miss penalty: - clock cycles n Miss rate:. - % Source: Wikipedia/ Computer Organization : Morgan Kaufmann [ th edition] Is it implemented as a hash? How many bits are used to encode address space identifiers size For a given optimal page size, is it better to round up or down to compute practical page size? Shared paging: Who decides which pages will be shared? L. L. Topics covered in this lecture Structure of s Hierarchical Paging Hashed Tables Inverted Tables Segmentation STRUCTURE OF THE PAGE TABLE L. L. Typical use of the page Paging Hardware: Paging is a form of dynamic relocation Process refers to addresses through pages virtual address Process has page Table has entries for pages that process uses One slot for each page n Irrespective of whether it is valid or not number Logical Address CPU p d offset p f Physical Address f f d f Frame f sorted by virtual addresses Table L.5 L.6 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.
Structure of the Table Hierarchical Paging Hashed Tables Inverted Tables Hierarchical Paging Logical address spaces: ~ 6 size: KB = x = Number of page entries? Logical address space size/page size / = million entries entry = bytes for process = x = MB L.7 L.8 Issues with large page s Cannot allocate page contiguously in memory Two-level Paging number offset Solution: Divide the page into smaller pieces n the page- -bit logical address L.9 L. Two-level Paging Address translation in two-level paging Outer Inner offset p p d p Actual Physical address -bit logical address Outer page Track pages of page- p of page d Physical memory frame L. L. SLIDES CREATED BY: SHRIDEEP PALLICKARA L.
Two-level s: The outer page GB address space split into chunks Two-level s: Case where only a few entries are needed GB address space split into chunks Each entry represents MB Unused by program Each entry represents MB Outer Inner Outer Inner offset offset size is KB size is KB L. L. Two-level s Address space has a million pages But ONLY page s are actually needed Second level page s Computing number of page s in hierarchical paging Outer Inner offset There is outer with entries Each outer entry points to an inner page So there are inner page s Total number of page s = + Total number of entries = + x L.5 L.6 Let s try -level paging for a 6-bit logical address space Outer page nd Outer page Outer page Inner page Inner page offset Outer page has entries! Divide the outer page into smaller pieces? offset Why hierarchical s are inappropriate for 6-bit architectures In our previous example There would be entries in the outer page We could keep going -level page s But all this results in a prohibitive number of memory accesses L.7 L.8 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.
Hashed page s An approach for handling address spaces > HASHED PAGE TABLES Virtual page number is hashed Hash used as key to enter items in the hash The value part of is a linked list Each entry has: Virtual page number Value of the mapped page frame Pointer to next element in the list L.9 L. Searching through the hashed for the frame number Virtual page number is hashed Hashed key has a corresponding value in n Linked List of entries Traverse linked list to Find a matching virtual page number Hash s and 6-bit address spaces Each entry refers to several pages instead of a single page Multiple page-frame mappings per entry Clustered page s Useful for sparse address spaces where memory references are non-contiguous (and scattered) L. L. Inverted page Only page in the system Has an entry for each memory frame Each entry tracks Process that owns it (pid) Virtual address of page (page number) INVERTED PAGE TABLES L. L. SLIDES CREATED BY: SHRIDEEP PALLICKARA L.
Inverted Profiling the inverted page Logical Address Physical Address i CPU pid p d i d Frame i Decreases the amount of memory needed Search time increases During page dereferencing search pid p i Stored based on frames, but searched on pages Whole might need to be searched! Table Stored based on frames L.5 L.6 Other issues with the inverted page Shared paging Multiple pages mapped to same physical memory Shared paging NOT possible in inverted s Only virtual page entry per physical page n Stored based on frames x86-6 Intel: IA-6 Itanium Not much traction AMD: x86-6 Intel adopted AMD s x86-6 architecture 6-bit address space: 6 (6 exabytes) Currently x86-6 provides 8 bit virtual address sizes: KB, MB, and GB -level paging hierarchy L.7 L.8 ARM architectures iphone and Android systems use this -bit ARM KB and 6 KB pages MB and 6 MB pages -level paging -level paging There are two levels for TLBs: A separate TLB for data Another for instructions SEGMENTATION L.9 L. SLIDES CREATED BY: SHRIDEEP PALLICKARA L.5
In our discussions so far Virtual memory is one-dimensional Logical addresses go from to some max value Many problems can benefit from having two or more separate virtual address spaces A compiler has many s that are built up as compilation proceeds Source Text Symbol Names and attributes of variables Constants Table Integer and floating point constants Parse tree Syntactic analysis of program Stack Procedure calls within the compiler Grows continuously as compilation proceeds Grows and shrinks in unpredic ways during compilation L. L. One dimensional address space with growing s Address space being used Free Symbol Table Source Constant Parse tree Call Program has an exceptional number of variables Address space allocated to the constant One dimensional address space with growing s Address space being used Free Symbol Table Source Constant Parse tree Call Program has an exceptional number of variables Symbol has BUMPED INTO the source Address space allocated to the constant L. L. Options available to the compiler Say that compilation cannot continue Not cool What would be really cool Free programmer from having to manage expansion and contraction of s Play Robin Hood Take space from s with room Give to s with little room L.5 L.6 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.6
But how? Provide many completely independent address spaces Segments A segment has linear sequence of addresses to max Other things about segments Different segments can and do have different lengths Segments grow and shrink independently without affecting each other Size increase: something pushed on segment Size decrease: something popped off of segment L.7 L.8 Users view memory as a collection of variable-sized segments Segmentation Symbol Segment Source Segment Segment5 Parse tree Segment Constants Segment Logical address space is a collection of segments Segments have name and length Addresses specify Segment name Offset within the segment Tuple: <segment-number, offset> L.9 L. Segmentation Addressing Example Segmentation Hardware Symbol Segment Source Segment Segment5 Parse tree Segment Limit Base Constants Segment 6 8 7 8 Segment Segment Segment Segment CPU s d Logical Address s < limit Segment Table base + Physical Address 58 6 Segment 67 L. NO TRAP: Addressing Error L. SLIDES CREATED BY: SHRIDEEP PALLICKARA L.7
Rationale for Paging and Segmentation Get a large linear address space without having to buy more physical memory PAGING Comparison of Paging and Segmentation Consideration Paging Segmentation How many linear address spaces are there? Many Allow programs and data to be broken up into logically independent address spaces Aids Sharing AND Protection n Segmentation Can total address space exceed physical memory Can procedures and data be distinguished and protected separately? NO Can fluctuating sizes be accommodated? NO L. L. Comparison of Paging and Segmentation Consideration Paging Segmentation Should the programmer be aware the the technique is being used? Is sharing of procedures between users facilitated? Why was this technique invented? NO NO To get a large linear address space without having to buy more physical memory To allow programs and data to be broken up into logically independent address spaces and to allow sharing and protection Segmentation with Paging Multics: Each program can have up to 56K independent segments Each with 6K 6-bit words Intel Pentium 6K independent segments Each segment has 9 -bit words Few programs need more than segments, but many programs need large segments L.5 L.6 Memory Management: Why? Main objective of system is to execute programs Programs and data must be in memory (at least partially) during execution To improve CPU utilization and response times Several processes need to be memory resident Memory needs to be shared VIRTUAL MEMORY L.7 L.8 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.8
Requiring the entire process to be in physical memory can be limiting Limits the size of a program To the size of physical memory BUT the entire program is not always needed Situations where the entire program need not be memory resident Code to handle rare error conditions Data structures are often allocated more memory than they need Arrays, lists Rarely used features L.9 L.5 What if we could execute a program that is partially in memory? Program is not constrained by amount of free memory that is available max Logical view of a process in memory {Function parameters, return addresses, and local variables} Each program uses less physical memory So, more programs can run Less I/O to swap programs back and forth L.5 low heap data {Global variables} L.5 Logical view of a process in memory Sparse address spaces max Virtual address spaces with holes low heap data Requires actual physical space ONLY IF heap or grows L.5 Harnessed by Heap or segments Dynamically linked libraries L.5 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.9
The contents of this slide-set are based on the following references Avi Silberschatz, Peter Galvin, Greg Gagne. Operating Systems Concepts, 9 th edition. John Wiley & Sons, Inc. ISBN-: 978-86. [Chapter 8] Andrew S Tanenbaum. Modern Operating Systems. th Edition,. Prentice Hall. ISBN: 596X/ 978-596. [Chapter ] L.55 SLIDES CREATED BY: SHRIDEEP PALLICKARA L.