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Module 1: Introduction and Course Overview... 11 Abbreviations Used in This Course... 12 Overview of Capital Products... 13 Overview of Capital Logic Course... 15 Introduction to Capital Logic... 15 General Terminology... 16 Logical (or Functional) Design... 17 Wiring Design... 18 Example Design Types... 19 Getting Started... 20 Capital Logic`s User Interface... 22 Module 1 Lab: Introduction to Capital Logic... 25 Module 2: Creating Logical & Wiring Designs... 27 Design Abstractions... 28 Flows Starting with Logical Designs... 29 Example of Logical Diagram... 30 Creating & Opening Projects... 30 Creating Designs... 31 Managing Diagrams... 34 Grid Preferences... 35 Borders... 36 Style Sets... 37 Adding Devices... 39 Replacing Device Symbols... 41 I
Adding Nets... 42 Converting Nets to Wires... 44 Module 2 Lab: Exercises #1 & #2... 46 Adding Connectors... 46 Adding/Moving Pins on Parameterized Objects... 48 Moving/Deleting Pins on a Parameterized Device... 49 Adding Part Numbers... 50 Interactive Plug Maps... 51 Manage Inline Connectors... 54 Pin Properties and Graphics... 55 Device/Connector Association... 55 Object Names in Capital Logic... 56 Ring Terminals... 57 Saving Your Work... 58 Module 2 Lab: Exercise #3... 58 Moving Objects... 59 Associating Graphical Objects with Devices... 61 Wires... 61 Splices... 63 Conductor Routing... 64 Grip Points... 65 Moving Conductors... 66 Design Rule Checks (DRCs)... 67 Report Generation... 68 Filtering the Project and Design Views... 69 II
Printing Designs... 69 Module 2 Lab: Exercise #4... 70 Module 3: Introduction to Capital Project... 71 Capital Project Concepts... 72 Capital Project Process... 74 Getting Started with Capital Project... 75 Project Templates... 77 System vs. Project Parameters... 79 Release Levels... 80 Release Level Behaviors... 82 Release Level Transitions... 83 Design Abstractions... 84 Audit Trails... 86 Exporting a Project... 86 Export / Import Project... 87 Close Project... 88 Module 3 Lab: Exercise #1... 88 Naming Conventions... 89 Object Type Information... 90 Default Names... 92 Duplicate Object Names... 95 Module 3 Lab: Exercise #2... 96 Advanced Naming Overview... 96 Advanced Naming Counters... 98 Creating an Advanced Naming Composition... 99 III
Advanced Naming Condition... 101 Applying the Advanced Naming Compositions... 102 Batch Generation of Object Names... 103 Language Translation... 104 Project Preferences... 106 Project Export Facility for Data Corruption... 108 Module 3 Lab: Exercise #3... 108 Module 4: Devices... 109 Devices... 110 Associating a Library Part with a Device... 112 Auto Generation of Connectors on Devices... 114 Associating a Connector with a Device... 115 Device Pin Generation... 115 Device Pin Mating... 116 Convert Device Symbol to Parameterized... 116 Inline Connectors... 117 Modular Connectors... 118 Module 4 Lab: Exercise #1... 119 Properties, Attributes and Graphics... 120 Top-Down vs. Bottom-Up Design... 123 Placing Library Parts onto a Diagram... 124 Batch Update Library Parts... 126 Module 4 Lab: Exercises #2 - #4... 127 Footprints... 128 Device-Side Connector Footprints... 130 IV
Find and Replace... 131 Module 4 Lab: Exercise #5... 132 Module 5: Advanced Wiring... 133 Highways... 134 Wire Manipulation... 136 Wire Module Codes... 137 Splices... 137 Center Strip Splices... 138 Module 5 Lab: Exercise #1... 138 Adding Generic Multicores... 139 Associate a Library Part with a Generic Multicore... 140 Adding Multicores Directly from Library... 141 Shield Terminations... 142 Multi-Level Multicores... 144 Customizing Multicore Indicators... 145 Daisy Chained Multicores... 145 Module 5 Lab: Exercise #2... 147 Assemblies... 147 Stacked Pins... 149 Adding Images to Diagrams... 150 Block Diagrams vs. Block Views... 151 Module 5 Lab: Exercise #3... 153 Module 6: Shared Objects... 155 Design Wide Objects... 156 Join Command... 159 V
Cross-Reference Text... 160 Changing the Home Instance... 162 Module 6 Lab: Exercise #1... 162 Concurrency... 163 Shared Nets/Wires... 165 Shared Objects... 166 Shared Objects in Capital Logic... 169 Locating Shared Objects in a Project... 170 Finding, Navigating & Unsharing Shared Objects... 171 Module 6 Lab: Exercise #2... 172 Shared Objects Pin Management... 172 Shared Pin Lists in Capital Project... 173 Creating an SPL with a Plug Map... 174 Shared Object Names... 177 Placing a Shared Device on a Design... 177 Shared Inline Connectors... 179 Shared Conductors... 180 Module 6 Lab: Exercise #3... 184 Shared Object Usages Report... 184 Revisions of Shared Objects... 186 Swapping Out Shared Object Revisions... 187 Module 6 Lab: Exercises #4 & #5... 189 Freezing/Unfreezing Shared Objects... 190 Composite Symbols as Shared Objects... 191 Build Lists... 193 VI
Module 6 Lab: Exercise #6... 198 Module 7: Symbols and Borders... 199 Symbol Overview... 200 Creating a Symbol Library... 200 Elements of a Symbol... 201 Symbol Creation Process... 202 Changing a Pin`s Name, Attributes & Properties... 206 Adding a Property to a Pin... 208 Symbol Properties... 209 Additional Symbol Tasks... 210 Symbol Library Management... 211 Module 7 Lab: Exercise #1... 212 Composite Symbols... 213 Composite Symbols in Capital Logic... 214 Connectivity in Symbols... 216 Module 7 Lab: Exercise #2... 218 Borders... 219 Border Preferences... 220 Creating a Border... 221 Adding Zones to a Border Symbol... 222 Inserting Images... 224 Properties... 225 Intelligent Text... 226 Module 7 Lab: Exercise #3... 231 Module 8: Options... 233 VII
Options Overview... 234 Defining Options... 235 Assigning Options to Designs... 237 Mandating Applicable Options... 237 Deleting Options... 238 Assigning Options to Objects... 238 Configurations... 239 Filtered Configuration Views... 241 Option Combinations... 242 Module Code Definition... 242 Module 8 Lab: Options... 243 Module 9: Design Validation... 245 Design Rule Checks... 246 Design Rule Checks: Manually Run... 248 Design Rule Checks: Background Run... 249 Design Rule Checks: Release Design... 250 Types of DRCs... 251 Defining and Applying Design Rules... 256 Module 9 Lab: Exercise #1... 256 Design Revisions... 257 Engineering Change Orders... 259 Setting & Tracking ECO Progress... 260 Compare Designs... 261 To Do Lists... 263 Module 9 Lab: Exercise #2... 263 VIII
Signal Tracing... 264 Harness Attributes on Designs... 265 Design & Project Exports/Imports... 266 Capital Bridges... 268 Module 9 Lab: Exercise #3... 268 Module 10: Design Management... 269 Design Folder Editing... 270 Design Abstractions... 272 Storing Circuit Information as a Composite Symbol... 273 Copying Designs Within a Project... 274 Copying Designs to Another Project... 275 Moving Diagram Content... 278 Style Sets... 278 Releasing Designs... 281 Capital Logic and Rules... 282 Printing Logic Diagrams... 284 Domains... 286 Design Scope... 288 Simulation of Electrical Schematics... 289 Capital Logic Bridges... 291 Module 10 Lab: Design Management... 292 Module 11: Wiring Challenge... 293 Module 11 Lab: Advanced Logic... 294 Module 12: Capital AutoView Assist for Logic (CAVAL)... 295 Logic Assist... 296 IX
Generating Diagrams using Logic Assist... 297 Generated Diagrams Dialog Diagrams Tab... 297 Component Styling... 300 Layout Styling... 301 Autoview Query and Generate... 302 Bulk CAVAL Processing... 304 Module 12 Lab: CAVAL... 306 X