MODE (mod) FIELD CODES. mod MEMORY MODE: 8-BIT DISPLACEMENT MEMORY MODE: 16- OR 32- BIT DISPLACEMENT REGISTER MODE

Similar documents
UMBC. A register, an immediate or a memory address holding the values on. Stores a symbolic name for the memory location that it represents.

Lecture 15 Intel Manual, Vol. 1, Chapter 3. Fri, Mar 6, Hampden-Sydney College. The x86 Architecture. Robb T. Koether. Overview of the x86

Assembly Language Each statement in an assembly language program consists of four parts or fields.

Addressing Modes on the x86

The x86 Architecture

EXPERIMENT WRITE UP. LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM

ADDRESSING MODES. Operands specify the data to be used by an instruction

Assembler Programming. Lecture 2

Registers. Ray Seyfarth. September 8, Bit Intel Assembly Language c 2011 Ray Seyfarth

Credits and Disclaimers

Access. Young W. Lim Fri. Young W. Lim Access Fri 1 / 18

The Microprocessor and its Architecture

Access. Young W. Lim Sat. Young W. Lim Access Sat 1 / 19

Chapter 3: Addressing Modes

Binghamton University. CS-220 Spring x86 Assembler. Computer Systems: Sections

Hardware and Software Architecture. Chapter 2

Module 3 Instruction Set Architecture (ISA)

We can study computer architectures by starting with the basic building blocks. Adders, decoders, multiplexors, flip-flops, registers,...

Computer Processors. Part 2. Components of a Processor. Execution Unit The ALU. Execution Unit. The Brains of the Box. Processors. Execution Unit (EU)

Introduction to IA-32. Jo, Heeseung

Q1: Multiple choice / 20 Q2: Memory addressing / 40 Q3: Assembly language / 40 TOTAL SCORE / 100

INTRODUCTION TO IA-32. Jo, Heeseung

Chapter 11. Addressing Modes

mith College Computer Science CSC231 - Assembly Week #4 Dominique Thiébaut

LAB 5 Arithmetic Operations Simple Calculator

EEM336 Microprocessors I. Addressing Modes

6/20/2011. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to:

x86 Assembly Tutorial COS 318: Fall 2017

16.317: Microprocessor Systems Design I Fall 2013

UMBC. 1 (Feb. 9, 2002) seg_base + base + index. Systems Design & Programming 80x86 Assembly II CMPE 310. Base-Plus-Index addressing:

X86 Addressing Modes Chapter 3" Review: Instructions to Recognize"

Reverse Engineering II: Basics. Gergely Erdélyi Senior Antivirus Researcher

CS241 Computer Organization Spring 2015 IA

Chapter 4: Data Movement Instructions. 4 1 MOV Revisited

Reverse Engineering II: The Basics

Credits and Disclaimers

EEM336 Microprocessors I. Data Movement Instructions

CMSC Lecture 03. UMBC, CMSC313, Richard Chang

Complex Instruction Set Computer (CISC)

16.317: Microprocessor Systems Design I Spring 2014

Advanced Microprocessors

Interfacing Compiler and Hardware. Computer Systems Architecture. Processor Types And Instruction Sets. What Instructions Should A Processor Offer?

Code segment Stack segment

CS 31: Intro to Systems ISAs and Assembly. Martin Gagné Swarthmore College February 7, 2017

CSE2421 FINAL EXAM SPRING Name KEY. Instructions: Signature

Experiment 8 8 Subroutine Handling Instructions and Macros

Instruction Set Architecture (ISA) Data Types

3- ADDRESSING MODES in 8086: In this section we use the MOV instruction to describe the data-addressing modes. Figure 3-1 shows the MOV instruction.

Turning C into Object Code Code in files p1.c p2.c Compile with command: gcc -O p1.c p2.c -o p Use optimizations (-O) Put resulting binary in file p

Basic Execution Environment

Assembly I: Basic Operations. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Microprocessors ( ) Fall 2010/2011 Lecture Notes # 15. Stack Operations. 10 top

Lecture (02) The Microprocessor and Its Architecture By: Dr. Ahmed ElShafee

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 21: Generating Pentium Code 10 March 08

A4 Sample Solution Ch3

Assembly Language Lab # 9

UMBC. contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. contain displacement added to IP.

Instruction Set Architectures

Lecture 3: Instruction Set Architecture

The x86 Architecture. ICS312 - Spring 2018 Machine-Level and Systems Programming. Henri Casanova

Computer Architecture and Assembly Language. Practical Session 3

Moodle WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics

Q1: Multiple choice / 20 Q2: Memory addressing / 40 Q3: Assembly language / 40 TOTAL SCORE / 100

Lab 2: Introduction to Assembly Language Programming

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 03, SPRING 2013

CS 16: Assembly Language Programming for the IBM PC and Compatibles

The von Neumann Machine

Faculty of Engineering Computer Engineering Department Islamic University of Gaza Assembly Language Lab # 2 Assembly Language Fundamentals

6/17/2011. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to:

System calls and assembler

T Reverse Engineering Malware: Static Analysis I

IA32 Intel 32-bit Architecture

Chapter 2: The Microprocessor and its Architecture

Reverse Engineering II: The Basics

iapx Systems Electronic Computers M

CS/ECE/EEE/INSTR F241 MICROPROCESSOR PROGRAMMING & INTERFACING MODULE 4: 80X86 INSTRUCTION SET QUESTIONS ANUPAMA KR BITS, PILANI KK BIRLA GOA CAMPUS

Addressing Modes. Outline

Assembly Language Programming Introduction

MICROPROCESSOR TECHNOLOGY

HLA v2.0 Intermediate Code Design Documentation

ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-11: 80x86 Architecture

The von Neumann Machine

Marking Scheme. Examination Paper Department of CE. Module: Microprocessors (630313)

Scott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998

Machine Code and Assemblers November 6

Microprocessors & Assembly Language Lab 1 (Introduction to 8086 Programming)

Project 1: Bootloader. COS 318 Fall 2015

EECE.3170: Microprocessor Systems Design I Spring 2016

The Instruction Set. Chapter 5

Chapter Three Addressing Mode MOV AX, BX

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs

CMSC 313 Lecture 10. Project 3 Questions. The Compilation Process: from *.c to a.out. UMBC, CMSC313, Richard Chang

Program controlled semiconductor device (IC) which fetches (from memory), decodes and executes instructions.

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College February 9, 2016

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College September 25, 2018

/ 30 Q3: Arithmetic instructions / 30 Q4: Logical instructions / 20 TOTAL SCORE / 100 Q5: EXTRA CREDIT / 10

CS165 Computer Security. Understanding low-level program execution Oct 1 st, 2015

Assembly level Programming. 198:211 Computer Architecture. (recall) Von Neumann Architecture. Simplified hardware view. Lecture 10 Fall 2012

CSC 8400: Computer Systems. Machine-Level Representation of Programs

CS241 Computer Organization Spring Introduction to Assembly

Transcription:

EXERCISE 9. Determine the mod bits from Figure 7-24 and write them in Table 7-7. MODE (mod) FIELD CODES mod 00 01 10 DESCRIPTION MEMORY MODE: NO DISPLACEMENT FOLLOWS MEMORY MODE: 8-BIT DISPLACEMENT MEMORY MODE: 16- OR 32- BIT DISPLACEMENT REGISTER MODE NOTE: WHEN r/m EQUALS 110. THERE IS A 1 6-BIT DISPLACEMENT. Figure 7-24 10. Determine the reg bits from Figure 7-25 and write them in Table 7-7. REGISTERS SPECIFIED BY REG (reg) FIELD reg 000 001 0 10 01 1 100 101 11 1 16- OR 32- BIT DATA OPERATION AL CL DL AH CH BH 16- BIT DATA OPERATION w = l AX CX SP BP I 32- BIT DATA OPERATION w = l o r n o w f i e l d ECX EDX EBX ESP ESI Figure 7-25 11. You now have the binary value for the first nibble of the second byte. Write the hex value below the binary value in Table 7-7. 12. Determine the r/m bit from Figure 7-26 and write it in Table 7-7. 16-BIT ADDRESSING EFFECTIVE ADDRESSES SPECIFIED BY r/m AND mod FIELDS r/m 0 0 0 001 0 1 0 = [Bx [BX SI - 100 110 111 6 d8] Figure 7-26 [SI d 1 [Bx d 1 6 ] 13. You now have the binary value for the second nibble of the second byte. Write the hex value below the binary value in Table 7-7.

Instruction Formats - II 14. What is the hex displacement value in the instruction MOV CX,[BX SI 0060H]? 15. For the displacement 0060H, what hex code follows the first two bytes 8B 88? 16. What is the complete instruction code for the mnemonic MOV CX,[BX SI 0060H]? 17. To test the instruction code for the mnemonic MOV CX,[BX SI 0060H], do the following on the 32-BIT MICROPROCESSOR circuit board. 1. Turn the SINGLE CYCLE switch to OFF and press RESET. 2. Enter "0200" in the CS register. 3. Enter "1000" in the IP register. 4. Enter "01 00" in the DS register. 5. Enter a base value "3000" in the BX register. 6. Enter an index value "0004" in the SI register. With a base value of 3000, an index value of 0004, and a displacement of 0060, what is the EA? 18. Continue by entering the memory operand and instruction code. 1. Press <EXIT> and then press <READ>. 2. Enter the logical address "0100 3064" for the memory operand. 3. Starting at address 04064, enter "88 77" for the operand, which is 7788. 4. Press <READ> and enter the logical address "0200 1000" for the instruction code. 5. Starting at address 03000, enter the instruction code "8B88 60 00". 6. Press <STEP> to execute the instruction code.

EXERCISE 29. You now have the binary value for the second nibble of the second byte. Write the hex value below the binary value in Table 7-8. 30. Determine the mod bits from Figure 7-28 and write it in Table 7-8. MODE (mod) FIELD CODES mod 00 01 10 1 1 DESCRIPTION MEMORY MODE: NO DISPLACEMENT FOLLOWS * MEMORY MODE: 8-BIT DISPLACEMENT MEMORY MODE: 16- OR 32-BIT DISPLACEMENT REGISTER MODE * NOTE: WHEN r/m EQUALS 110. THERE IS A 16-BIT DISPLACEMENT. Figure 7-28 Determine the reg bits from Figure 7-29 and write it in Table 7-8. REGISTERS SPECIFIED BY REG (reg) FIELD 16- OR 32- BIT DATA OPERATION w = O AL CL DL BL AH CH DH BH 16-BIT DATA OPERATION w = l or no w field AX CX DX BX SP BP SI Dl 32-BIT DATA OPERATION w = l or no w field EAX ECX EDX EBX ESP EBP ESI EDI Figure 7-29 32. You now have the binary value for the first nibble of the third byte. Write the hex value below the binary value in Table 7-8. 33. Determine the r/m bits from Figure 7-30 and write it in Table 7-8. 32-BIT ADDRESSING EFFECTIVE ADDRESSES SPECIFIED BY r/m AND mod FIELDS Figure 7-30 34. You now have the binary value for the second nibble of the third byte. Write the hex value below the binary value in Table 7-8.

InstructionFormats- II 35. The scaled index (EDI*2)is given in the mnemonic. Determine the ss bits from Figure 7-31 and write them in Table 7-8. SS FIELD IN S-I-B BYTE ss 00 0 1 10 1 1 SCALE FACTOR 1 2 4 8 Figure 7-31 36. Determine the index bits from Figure 7-32 and write them in Table 7-8. INDEX (index) FIELD IN S-1-B BYTE SPECIFIED BY INDEX REGISTER index 000 001 010 01 1 100 101 110 1 1 1 *NOTE: WHEN THE INDEX FIELD IS 100. THEN THE SS FIELD MUST EQUAL 00. Figure 7-32 INDEX REGISTER EAX ECX EDX EBX NO INDEX REG* EBP ESI EDI Determine the base bits from Figure 7-33 and write them in Table 7-8. BASE (base) FIELD IN S-1-B BYTE SPECIFIED BY EFFECTIVE ADDRESS base mod = 01 mod = 10 000 001 010 01 1 100 101 110 11 1 [EDX d8] [ECX [EDX d8] [ESP d8] [EBP d8] [EAX (S*l) [ECX [EDX [EBX [ESP [EBP NOTE: S*l EQUALS THE SCALING FACTOR TIMES THE INDEX VALUE. Figure 7-33 38. You now have the binary value for the last instruction byte. Write the hex value below the binary value in Table 7-8. 39. What is the complete instruction code for the mnemonic MOV [ECX (ED l*2)], BX?

EXERCISE 7- For the instruction MOV EBX,[ECX (EDI*4) 0520F8AB], what are the r/m field bits? 32- BIT ADDRESSING EFFECTIVE ADDRESSES SPECIFIED BY r/m AND mod FIELDS r /m mod = 00 mod = 01 mod = 10 000 001 010 011 100 101 110 111 [EAX] [ E C X ] [ E D X ] [ E B X ] s- i- b present d32 [ E S I ] [ EDI] [EAX d8] [ECX d 8 ] [EDX d 8 ] [EBX d 8 ] s-i-b present [EBP db] [ESI db] [EDI d8] [EAX d32] [ECX d32] [EDX d32] [EBX d32] s- i- b present [EBP d32] [ESI d32] [EDI d32] Figure 7-36 For the instruction MOV EBX,[ECX (EDI*4) 0520F8AB], what are the index field bits? INDEX (index) FIELD IN S-1-B BYTE SPECIFIED BY INDCX REGISTER index 000 001 010 01 1 100 101 110 1 1 1 INDEX REGISTER EAX ECX EDX EBX NO INDEX REG* EBP ESI ED1 *NOTE: WHEN THE INDEX FIELD IS 100. THEN THE SS FIELD MUST EQUAL 00. Figure 7-37

Instruction Formats- II BASE (base) FIELD IN 5-1-0 BYTE SPECIFIED BY EFFECTIVE ADDRESS base m o d = 00 m o d = 01 mod = 10 000 [EAX (S*I)] [EAX (S*l) db] [EAX (S*l) d32] 001 [ECX (S*I)] [ECX (S*I) db] [ECX (S*l) d 3 2 ] 010 [EDx (S*I)] [EDX (S*I) d8] [EDX ( S * I ) d32] 011 [EBx (S*l)] [EBX (S*I) d8] [EBX (S*I) d32] 100 101 110 [ESP (S*l)] [d32 (S*I)] [ESl (S*I)] [ESP (S*I) d8] [EBP (S*I) d8] [ESI (S*I) d8] [ESP (S*I) d32] [EBP (S*I) t d32] [ESl (S*I) d32] 1 1 1 [ED1 (S*l)] [ED1 (S*I) d8] [ED1 (S*I) d32] NOTE: S'I EQUALS THE SCALING FACTOR TIMES THE INDEX VALUE. Figure 7-38 5. For the instruction MOV [ESl (EDX*8)],EAX, what are the base field bits?