General Purpose Timers. Chapter 15

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Transcription:

General Purpose Timers Chapter

Timer Free-run counter (independent of processor) Functions Input capture Output compare Pulse-width modulation (PWM) generation

Block Diagram

Timer: Clock Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer ISR Interrupt! "#_"%& =! "(_)*" +,- +

Timer: Output Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer ISR Interrupt = Timer Output (OCREF) Compare & Capture Register (CCR)

Timer: Input Capture Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer ISR Interrupt Compare & Capture Register (CCR)

Multi-Channel Outputs Each timer has four channels. Each channel has its own Compare and Capture Register. CCR, CCR, CCR, CCR. These four channels share the timer counter Compare & Capture Register (CCR) 7

GP Timer Block Diagram ARR (Autoloaded Register)

Output Compare Output Compare Mode (OCM) Timer Output (OCREF) Frozen High ifcnt==ccr Low if CNT == CCR Toggle ifcnt== CCR Forced low (alwayslow) Forced high (alwayshigh) 9

Counting up, down, center,,,,,,,..,,,,,,,.,,,,,,,,,,

PWM Mode Mode < Reference Reference PWM mode (Low True) PWM mode (High True) Active Inactive Inactive Active

Edge-aligned Mode (Up-counting) ARR =, RCR = clock counter overflow overflow overflow overflow Update event (UEV) Period = ( + ARR) * Clock Period = 7 * Clock Period RCR=Repetition

Edge-aligned Mode (down-counting) ARR =, RCR = Clock underflow underflow underflow underflow Update event (UEV) Period = ( + ARR) * Clock Period = 7 * Clock Period

Center-aligned Mode ARR =, RCR = Clock overflow underflow overflow underflow Update event (UEV) Period = * ARR * Clock Period = * Clock Period

PWM Mode (Low-True) Upcounting mode, ARR =, CCR =, RCR = Mode Timer Output = High if counter < CCR Low if counter CCR Clock CCR = OCREF Duty Cycle = CCR ARR + Period = ( + ARR) * Clock Period = 7 * Clock Period = 7

PWM Mode (High-True) Upcounting mode, ARR =, CCR =, RCR = Mode Timer Output = Low if counter < CCR High if counter CCR Clock CCR = OCREF Duty Cycle = - = 7 CCR ARR + Period = ( + ARR) * Clock Period = 7 * Clock Period

PWM Mode (High-True) Upcounting mode, ARR =, CCR =, RCR = Mode Timer Output = Low if counter < CCR High if counter CCR Clock CCR = OCREF Duty Cycle = - = 7 CCR ARR + Period = ( + ARR) * Clock Period = 7 * Clock Period 7

PWM Mode (High-True) Center-aligned mode, ARR =, CCR =, RCR = Mode Timer Output = Low if counter < CCR High if counter CCR Clock CCR = OCREF Duty Cycle = - = CCR ARR Period = * ARR * Clock Period = * Clock Period 8

PWM Mode (High-True) Center-aligned mode, ARR =, CCR =, RCR = Mode Timer Output = Low if counter < CCR High if counter CCR Clock CCR = OCREF Duty Cycle = - = CCR ARR Period = * ARR * Clock Period = * Clock Period 9

Up-Counting: Left Edge-aligned Upcounting mode, ARR =, CCR =, RCR = Clock CCR = CCR = CCR = OCREF CCR = OCREF All rising edges occur at the same time! Left-aligned PWM Period

PWM Mode : Right Edge-aligned Upcounting mode, ARR =, CCR =, RCR = Clock CCR = CCR = OCREF CCR = OCREF CCR = All falling edges occur at the same time! Right-aligned PWM Period

PWM Mode : Center Aligned Timer Output = Low if counter < CCR High if counter CCR Center-aligned mode, ARR =, CCR =, RCR = Clock CCR = CCR = OCREF CCR = OCREF CCR = PWM signals are center aligned! Center-aligned PWM Period

The devil is in the detail Timer output control Enable Timer Output MOE: Main output enable OSSI: Off-state selection for Idle mode OSSR: Off-state selection for Run mode CCxE: Enable of capture/compare output for channel x CCxNE: Enable of capture/compare complementary output for channel x

Input Capture Monitor both rising and falling edge

Input Capture Monitor only rising edges or only falling edge

Input Capture

Input Filtering 7

Input Capture Diagram 8

Ultrasonic Distance Sensor!"#$%&'( = *+,&-./"."( ((- + +,&- = 789: ;<=> ;=?@ AB CDEF GHD?/B J = *+,&-./"."( µ# 8 9

Ultrasonic Distance Sensor The echo pulse width corresponds to round-trip time.!"#$%&'( ('*) = -./#( "$h (#) 8 or!"#$%&'( ("&'h) = -./#( "$h (#) 8 If pulse width is 8ms, no obstacle is detected.

Ultrasonic Distance Sensor

Later

Repetition Register (PCR)

Repetition Register (PCR)

Repetition Register (RCR)

Repetition Register (PCR)

Repetition Register (PCR) 7