Chapter 3: Arithmetic for Computers

Chapter 3: Arithmetic for Computers

Objectives Signed and Unsigned Numbers Addition and Subtraction Multiplication and Division Floating Point Computer Architecture CS 35101-002 2

The Binary Numbering System A computer s internal storage techniques are different from the way humans represent information in daily lives Humans Decimal numbering system to rep real numbers Base-10 Each position is a power of 10 3052 = 3 x 10 3 + 0 x 10 2 + 5 x 10 1 + 2 x 10 0 Computer Architecture CS 35101-002 3

Binary Representation of Numbers Information inside a digital computer is stored as a collection of binary data Binary numbering system Base-2 Built from ones and zeros Each position is a power of 2 1101 = 1 x 2 3 + 1 x 2 2 + 0 x 2 1 + 1 x 2 0 Digits 0,1 are called bits (binary digits) Computer Architecture CS 35101-002 4

Binary Representation of Numbers 6-Digit Binary Number (111001) 111001 = 1 x 2 5 + 1 x 2 4 + 1 x 2 3 + 0 x 2 2 + 0 x 2 1 + 1 x 2 0 = 32 + 16 + 8 + 0 + 0 + 1 = 57 5-Digit Binary Number (10111) 10111 = 1 x 2 4 +0 x 2 3 + 1 x 2 2 + 1 x 2 1 + 1 x 2 0 = 16 + 0 + 4 + 2 +1 = 23 Computer Architecture CS 35101-002 5

Binary Representation of Numbers Computers use finite number of Bits for Integer Storage Size ( word ) Max Unsigned Number Allowed 16 1x2 15 + 1x2 14 + +1x2 1 +1x2 0 MIPS-32 1x2 31 +1x2 30 + +1x2 1 + 1x2 0 Otherwise Arithmetic Overflow Computer Architecture CS 35101-002 6

Number Representation MIPS word Example: 11 ten = 1 x 2 3 +0 x 2 2 + 1 x 2 1 + 1 x 2 0 = 1011 two 31 30 29 28 7654 3210 0 0 0 0 1011 Most-significant bit Least-significant bit Computer Architecture CS 35101-002 7

Signed Number Representation Sign/Magnitude Notation Signed Number Examples: -49, +3, -8 Most significant Bit Stores sign 0 +ve number 1 -ve number Remaining Bits represent Magnitude of number -49 +3 1 0 0 0 0 0 0 0 0011 0001 0011 Find the decimal value for the 32-bit sign/magnitude notation: 1 0 0 0 0 0 0 0 Computer Architecture CS 35101-002 8

Signed Number Representation Two s Complement Notation Leading 0s mean +ve Leading 1s mean -ve 1 0 0 0 0011 0001 1 x 2 31 + 0 X2 30 + 0x2 6 + 1x2 5 + 1x2 4 + 0x2 3 + 0x2 2 +0x2 1 +1x2 0 = -2,147,483,648 + 32 +16 +1 = -2,147,483,609 Compare with sign/magnitude representation for -49 Computer Architecture CS 35101-002 9

cf: Sign Magnitude/ Two s Complement Notations Up Close Sign Magnitude Two's Complement 000 = +0 000 = +0 001 = +1 001 = +1 010 = +2 010 = +2 011 = +3 011 = +3 100 = -0 100 = -4 101 = -1 101 = -3 110 = -2 110 = -2 111 = -3 111 = -1 Computer Architecture CS 35101-002 10

MIPS 32 bit signed numbers: Two s Complement Representation Value = 0 0001 = + 1 0010 = + 2... 0111 1111 1111 1111 1111 1111 1111 1110 = + 2,147,483,646 0111 1111 1111 1111 1111 1111 1111 1111 = + 2,147,483,647 1000 = 2,147,483,648 1000 0001 = 2,147,483,647 1000 0010 = 2,147,483,646... 1111 1111 1111 1111 1111 1111 1111 1101 = 3 1111 1111 1111 1111 1111 1111 1111 1110 = 2 1111 1111 1111 1111 1111 1111 1111 1111 = 1 Computer Architecture CS 35101-002 11

Two s Complement Operation To Negate a Two's complement number: First invert all bits then Add 1 to the inverted bits To Convert n bit numbers into numbers with more than n bits: MIPS 16 bit immediate gets converted to 32 bits for arithmetic copy the most significant bit (the sign bit) into the LHS half of the word 0010 -> 0010 1010 -> 1111 1010 Computer Architecture CS 35101-002 12

Addition and Subtraction Addition (carries 1s) 0011 = + 3 0010 = + 2 0101 = + 5 Subtraction: use addition of negative numbers 0011 = + 3 1111 1111 1111 1111 1111 1111 1111 1110 = - 2 0001 = + 1 Overflow (if result too large to fit in the finite computer word of the result register) e.g., adding two n-bit numbers does not yield an n-bit number 0111 0001 1000 Computer Architecture CS 35101-002 13

Overflow No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: overflow when adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive and get a negative or, subtract a positive from a negative and get a positive Computer Architecture CS 35101-002 14

Multiplication Recall: X 1000 ten 1001 ten Multiplicand Multiplier Observations 1000 1000 1001000 ten Product More storage required to store the product Place copy of multiplicand in proper location if multiplier is a 1 Place 0 in proper location if multiplier is 0 Product of n-bit Multiplicand and m-multiplier is (n + m)-bit long Number of steps (move digits to LHS) is n -1; where n rep the number of digits (1,0) Let's examine 2 versions of multiplication algorithm for binary numbers Computer Architecture CS 35101-002 15

Multiplication Version 1 Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 Multiplicand 64 bits Shift left 1a. Add multiplicand to product and place the result in Product register 64-bit ALU Multiplier Shift right 32 bits 2. Shift the Multiplicand register left 1 bit Product Write Control test 3. Shift the Multiplier register right 1 bit 64 bits Datapath Control No: < 32 repetitions 32nd repetition? Yes: 32 repetitions Done Computer Architecture CS 35101-002 16

Multiplication Refined Version Start Product0 = 1 1. Test Product0 Product0 = 0 32-bit ALU Multiplicand 32 bits Add multiplicand to bits 32 thru 63 in product register and place the result in bits 32 thru 63 of product register Product 64 bits Shift right Write Control test 3. Shift the Product register right 1 bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Computer Architecture CS 35101-002 17

Multiplication Negative Numbers Convert Multiplicand and Multiplier to Positive Numbers Run the Multiplication algorithm for 31 iterations (ignoring the sign bit) Negate product only if original signs for Multiplicand and Multiplier are different Computer Architecture CS 35101-002 18

Floating Point (Overview) Binary Representation Floats Provide representation for: Decimal numbers, e.g., 3.1416 Fractions, very small numbers, e.g.,.1 First Convert number to scientific notation: +MxB +E M ~ mantissa; B ~ base (2) of exponent E ~ exponent Computer Architecture CS 35101-002 19

Floats Binary Representation: Example 5.75 5 has binary value 101.75 = ½ + ¼ = 2-1 + 2-2 = 0.11 (binary value) 5.75 = 101.11 x 2 0 (scientific notation) Normalize number: 5.75 =.10111 x 2 3 (i.e., 1/2 + 1/8 + 1/16 + 1/32) Computer Architecture CS 35101-002 20

Floating Point MIPS Sign Magnitude Representation +5.75 = +.10111 x 2 +3 31 30 29 28 0 0 0 0.... 0001 22...22 1101 101. 1100 7654 3210 Most-significant bit Show that: General Sign Magnitude Representation (-1) s xfx2 E Least-significant bit Min value of numbers is 2x10-38 Max value of numbers is 2x10 38 How do you increase the precision? Computer Architecture CS 35101-002 21

MIPS Representation Overflow/Underflow/Double Precision Exponent is too large Overflow Exponent too small Underflow MIPS solution: Double Precision representation Combine two MIPS word +5.75 = +.10111 x 2 +3 31 30 29 28 20. 7654 3210 0 0 0 0001 1101 1100 31 30 29 28. 7654 3210 0 0 0 Computer Architecture CS 35101-002 22

Floating Point IEEE 754 Representation Observations so far: We can increase the precision by making leading 1 bit of the normalized number implicit Logically 24 bits (instead of 23) for the fractional part In our representation, the exponent of 2-1 Looks like a large binary number On the other hand the exponent 2 +1 looks like a smaller binary number Let s make the most negative exponent 000 and most positive 1111111 Hence introduce a transformation (Bias) Single Precision (7 bits) subtract 127 from exponent why 7 bits? Double Precision (10 bits) subtract 1023 from exponent why 10 bits? IEEE 754 Binary Representation: (-1) s x(1 + F)x2 (E- Bias) Computer Architecture CS 35101-002 23

Floating Point IEEE 754 Binary Representation Show the IEEE 754 Single Precision Binary Representation of -0.75-0.75 = -0.11 2 x2-1 Hence, normalized notation: -1.1 2 x2-1 ------(a) cf (a) with generalized form: (-1) s x(1 + F)x2 (E- Bias) Then (a) becomes: (-1) 1 x (1 +.1 000) x 2 (126 127) 31 30 29 28.... 22...22. 7654 3210 1 0 1 1 1111 0100 Computer Architecture CS 35101-002 24

Floating Point IEEE 754 Binary Representation Show the IEEE 754 Double Precision Binary Representation of -0.75-0.75 = -0.11 2 x2-1 Hence, normalized notation: -1.1 2 x2-1 ------(a) cf (a) with generalized form: (-1) s x(1 + F)x2 (E- Bias) Then (a) becomes: (-1) 1 x (1 +.1 000) x 2 (1022 1023) 31 30 29 28 27 26 25. 23. 21 20. 7654 3210 1 0 1 1 1 111 11 1 0 0 0 0 0 0 000 00 0 0 Computer Architecture CS 35101-002 25