CoreResetP v7.0. Handbook

CoreResetP v7.0 Handbook

CoreResetP v5.1 Handbook Table of Contents Introduction... 3 Core Overview... 3 Key Features... 4 Supported Microsemi FPGA Families... 4 Core Version... 4 Interface Description... 5 Parameters... 5 Ports... 6 Tool Flows... 9 SmartDesign... 9 Timing Diagrams... 11 List of Changes... 15 Product Support... 17 Customer Service... 17 Customer Technical Support Center... 17 Technical Support... 17 Website... 17 Contacting the Customer Technical Support Center... 17 ITAR Technical Support... 18 CoreResetP v7.0 Handbook 2

Introduction Core Overview CoreResetP handles sequencing of reset signals in a SmartFusion 2 or IGLOO 2 device. This core deals with the resets related to the peripheral blocks including the double data rate (DDR) controllers and high speed serial interface (SERDESIF) blocks. If the System Builder tool is used within the Libero System-on-Chip (SoC) software to construct a design targeted at a SmartFusion2 or IGLOO2 device, CoreResetP will automatically be instantiated and connected within the design if required. Figure 1 shows an overview of how CoreResetP is connected to other components. SYSCTRL MSS/HPMS MDDR FPGA Fabric RESET_N_F2M M3_RESET_N (SmartFusion2 only) RESET_N_M2F CoreResetP FDDR_CORE_RESET_N FPLL_LOCK SDIF0_PHY_RESET_N SDIF0_CORE_RESET_N SDIF0_SPLL_LOCK SDIF1_PHY_RESET_N SDIF1_CORE_RESET_N SDIF1_SPLL_LOCK EXT_RESET_OUT POWER_ON_RESET_N MDDR_DDR_AXI_S_CORE_RESET_N RCOSC_25_50MHZ CLK_BASE CLK_LTSSM CONFIG1_DONE CoreConfigP CONFIG2_DONE SDIF_RELEASED INIT_DONE FAB_RESET_N 25 or 50 MHz RC Osc FDDR SERDESIF_0 SERDESIF_1 Figure 1 CoreResetP Connections CoreResetP v7.0 Handbook 3

Introduction Key Features Sequences reset signals in a SmartFusion2 or IGLOO2 device Supported Microsemi FPGA Families Core Version CoreResetP supports the following families: SmartFusion2 IGLOO2 This handbook supports CoreResetP v7.0. 4 CoreResetP v7.0 Handbook

Interface Description Parameters The parameters present on CoreResetP are listed in Table 1. Parameter EXT_RESET_CFG DEVICE_VOLTAGE MDDR_IN_USE FDDR_IN_USE SDIF0_IN_USE SDIF1_IN_USE SDIF2_IN_USE SDIF3_IN_USE SDIF0_PCIE SDIF1_PCIE SDIF2_PCIE SDIF3_PCIE SDIF0_PCIE_HOTRESET SDIF1_PCIE_HOTRESET SDIF2_PCIE_HOTRESET SDIF3_PCIE_HOTRESET Table 1 CoreResetP Parameters 0 = EXT_RESET_OUT is never asserted Description 1 = EXT_RESET_OUT is asserted if power up reset (POWER_ON_RESET_N) is asserted 2 = EXT_RESET_OUT is asserted if FAB_RESET_N is asserted 3 = EXT_RESET_OUT is asserted if power up reset (POWER_ON_RESET_N) or FAB_RESET_N is asserted. 1 = 1.0 V (RC oscillator frequency = 25 MHz) 2 = 1.2 V (RC oscillator frequency = 50 MHz) 1 = MDDR block is in use. 1 = FDDR block is in use. 1 = SERDESIF_0 block is in use. 1 = SERDESIF_1 block is in use. 1 = SERDESIF_2 block is in use. 1 = SERDESIF_3 block is in use. 1 = SERDESIF_0 block is used for PCIe. 1 = SERDESIF_1 block is used for PCIe. 1 = SERDESIF_2 block is used for PCIe. 1 = SERDESIF_3 block is used for PCIe. 1 = If SERDESIF_0 block is used for PCIe, include support for Hot Reset. SDIF0_PCIE_HOTRESET should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe Hot Reset. 1 = If SERDESIF_1 block is used for PCIe, include support for Hot Reset. SDIF1_PCIE_HOTRESET should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe Hot Reset. 1 = If SERDESIF_2 block is used for PCIe, include support for Hot Reset. SDIF2_PCIE_HOTRESET should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe Hot Reset. 1 = If SERDESIF_3 block is used for PCIe, include support for Hot Reset. SDIF3_PCIE_HOTRESET should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe Hot Reset. CoreResetP v7.0 Handbook 5

Interface Description Parameter SDIF0_PCIE_L2P2 SDIF1_PCIE_L2P2 SDIF2_PCIE_L2P2 SDIF3_PCIE_L2P2 ENABLE_SOFT_RESETS DEVICE_090 Description 1 = If SERDESIF_0 block is used for PCIe, include support for L2/P2 power states. SDIF0_PCIE_L2P2 should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe L2/P2 power states. 1 = If SERDESIF_1 block is used for PCIe, include support for L2/P2 power states. SDIF0_PCIE_L2P2 should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe L2/P2 power states. 1 = If SERDESIF_2 block is used for PCIe, include support for L2/P2 power states. SDIF0_PCIE_L2P2 should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe L2/P2 power states. 1 = If SERDESIF_3 block is used for PCIe, include support for L2/P2 power states. SDIF0_PCIE_L2P2 should be set to 0 in an 090 device because the SERDESIF block present in an 090 device inherently supports PCIe L2/P2 power states. 1 = SOFT_* input signals can be used to assert corresponding reset outputs. The SOFT_* inputs are normally driven by an instance of the CoreConfigP core. 1 = The target device is a 090 sized device. Ports The ports present on CoreResetP are listed in Table 2. Table 2 CoreResetP Ports Port Name Type Description RCOSC_25_50MHZ Input 25 MHz or 50 MHz clock from RC oscillator. CLK_BASE Input Should be driven by the same clock signal that drives the CLK_BASE input of the MSS/HPMS. CLK_LTSSM Input Clock signal used to sample Link Training and Status State Machine (LTSSM) data that s present on the APB read data buses from the SERDESIF blocks during idle APB cycles. The frequency of CLK_LTSSM should be high enough to track the transitions in the LTSSM data. A frequency in the range 100 to 125 MHz is recommended. POWER_ON_RESET_N Input Active low power on reset from system controller. EXT_RESET_OUT Output Output suitable for driving an external reset pin. RESET_N_F2M Output Active low reset signal to MSS/HPMS. Resets MSS/HPMS. M3_RESET_N Output Active low reset signal to MSS. Resets Cortex-M3 processor. This signal is only relevant when CoreResetP is used in a SmartFusion2 device. RESET_N_M2F Input Active low reset from MSS/HPMS. FIC_2_APB_M_PRESET_N Input Active low reset from MSS/HPMS. MDDR_DDR_AXI_S_CORE_RESET_N Output Active low reset to MSS/HPMS. Resets MDDR AXI interface. MSS_HPMS_READY Output After power on or reset this signal will be low until the MSS/HPMS is ready for use, at which point it will go high. 6 CoreResetP v7.0 Handbook

Ports Port Name Type Description DDR_READY Output After power on or reset this signal will be low until the DDR controllers are ready for use, at which point it will go high. SDIF_READY Output After power on or reset this signal will be low until the SERDESIF blocks are ready for use, at which point it will go high. INIT_DONE Output Indicates the completion of the initialization. Asserted when peripheral configuration and reset sequencing are completed. Normally, connected to CoreConfigP. SDIF_RELEASED Output Indicates that the SERDESIF blocks have been released from reset. Normally connected to CoreConfigP. CONFIG1_DONE Input Indicates the completion of the first stage of configuration from CoreConfigP. CONFIG2_DONE Input Indicates the completion of the second stage of configuration from CoreConfigP. FAB_RESET_N Input Active low reset input from user logic in fabric. FPLL_LOCK Input Indicates phase-locked loop (PLL) lock from FDDR block. FDDR_CORE_RESET_N Output Active low reset to FDDR block. Resets FDDR AXI interface. SDIF0_SPLL_LOCK Input Indicates PLL lock from SERDESIF_0 block. SDIF0_PHY_RESET_N Output Active low PHY reset to SERDESIF_0 block SDIF0_CORE_RESET_N Output Active low core reset to SERDESIF_0 block This signal is used in devices that have a single PCIe controller within the SERDESIF_0 block. SDIF0_0_CORE_RESET_N Output Active low core reset to SERDESIF_0 block. This signal is used in devices that have two PCIe controllers within the SERDESIF_0 block. SDIF0_1_CORE_RESET_N Output Active low core reset to SERDESIF_0 block. This signal is used in devices that have two PCIe controllers within the SERDESIF_0 block. SDIF1_SPLL_LOCK Input Indicates PLL lock from SERDESIF_1 block. SDIF1_PHY_RESET_N Output Active low PHY reset to SERDESIF_1 block SDIF1_CORE_RESET_N Output Active low core reset to SERDESIF_1 block SDIF2_SPLL_LOCK Input Indicates PLL lock from SERDESIF_2 block. SDIF2_PHY_RESET_N Output Active low PHY reset to SERDESIF_2 block SDIF2_CORE_RESET_N Output Active low core reset to SERDESIF_2 block SDIF3_SPLL_LOCK Input Indicates PLL lock from SERDESIF_3 block. SDIF3_PHY_RESET_N Output Active low PHY reset to SERDESIF_3 block. SDIF3_CORE_RESET_N Output Active low core reset to SERDESIF_3 block. SDIF0_PERST_N Input SERDESIF_0 active low PCIe reset signal SDIF1_PERST_N Input SERDESIF_1 active low PCIe reset signal SDIF2_PERST_N Input SERDESIF_2 active low PCIe reset signal SDIF3_PERST_N Input SERDESIF_3 active low PCIe reset signal SDIF0_PSEL Input SERDESIF_0 APB select signal CoreResetP v7.0 Handbook 7

Interface Description Port Name Type Description SDIF0_PWRITE Input SERDESIF_0 APB write signal SDIF0_PRDATA[31:0] Input SERDESIF_0 APB write data SDIF1_PSEL Input SERDESIF_1 APB select signal SDIF1_PWRITE Input SERDESIF_1 APB write signal SDIF1_PRDATA[31:0] Input SERDESIF_1 APB write data SDIF2_PSEL Input SERDESIF_2 APB select signal SDIF2_PWRITE Input SERDESIF_2 APB write signal SDIF2_PRDATA[31:0] Input SERDESIF_2 APB write data SDIF3_PSEL Input SERDESIF_3 APB select signal SDIF3_PWRITE Input SERDESIF_3 APB write signal SDIF3_PRDATA[31:0] Input SERDESIF_3 APB write data SOFT_EXT_RESET_OUT Input When high, the EXT_RESET_OUT output is asserted (high) SOFT_RESET_F2M Input When high, the RESET_N_F2M output is asserted (low) SOFT_M3_RESET Input When high, the M3_RESET_N output is asserted (low) SOFT_MDDR_DDR_AXI_S_CORE_RESET Input When high, the MDDR_DDR_AXI_S_CORE_RESET_N output is asserted (low) SOFT_FDDR_CORE_RESET Input When high, the FDDR_CORE_RESET_N output is asserted (low) SOFT_SDIF0_PHY_RESET Input When high, the SDIF0_PHY_RESET_N output is asserted (low) SOFT_SDIF0_CORE_RESET Input When high, the SDIF0_CORE_RESET_N output is asserted (low) SOFT_SDIF1_PHY_RESET Input When high, the SDIF1_PHY_RESET_N output is asserted (low) SOFT_SDIF1_CORE_RESET Input When high, the SDIF1_CORE_RESET_N output is asserted (low) SOFT_SDIF2_PHY_RESET Input When high, the SDIF2_PHY_RESET_N output is asserted (low) SOFT_SDIF2_CORE_RESET Input When high, the SDIF2_CORE_RESET_N output is asserted (low) SOFT_SDIF3_PHY_RESET Input When high, the SDIF3_PHY_RESET_N output is asserted (low) SOFT_SDIF3_CORE_RESET Input When high, the SDIF3_CORE_RESET_N output is asserted (low) SOFT_SDIF0_0_CORE_RESET Input When high, the SDIF0_0_CORE_RESET_N output is asserted (low) SOFT_SDIF0_1_CORE_RESET Input When high the SDIF0_1_CORE_RESET_N output is asserted (low) Note: All signals in this table are active high unless otherwise stated. 8 CoreResetP v7.0 Handbook

Tool Flows SmartDesign If the System Builder tool is used within the Libero SoC software to construct a design targeted at a SmartFusion2 or IGLOO2 device, CoreResetP will automatically be instantiated and connected within the design if required. You can manually instantiate and configure CoreResetP within a SmartDesign design if required. Connecting CoreResetP in SmartDesign Peripheral blocks can be selected using check boxes available in the configuration GUI for CoreResetP. If a peripheral block is not in use, the ports related to that peripheral do not appear for connection on the CoreResetP symbol. Configuring CoreResetP in SmartDesign The CoreResetP configuration GUI is shown in Figure 2 on page 10. There are a number of aspects of interest as outlined below: The condition(s) under which the EXT_RESET_OUT signal is asserted. Note: Use of this signal to drive an external reset pin is optional. It does not have to be used. Device voltage. The device voltage determines the frequency of the RC oscillator clock which is used to clock interval timers within CoreResetP. When device voltage is 1.0 V, RC oscillator frequency will be 25 MHz. When device voltage is 1.2 V, RC oscillator frequency will be 50 MHz. DDR usage. Select MDDR and FDDR checkboxes to select MDDR and FDDR usage. You can also configure the DDR memory settling time. After the reset signals to the MDDR and FDDR blocks are released, some time must be allowed before the DDR memory can be accessed. A waiting time of between 5 to 5000 microseconds can be specified. This sets the minimum time that must have elapsed after the release of the FDDR_CORE_RESET_N and MDDR_CORE_RESET_N signals before USER_FAB_RESET_N is released, and INIT_DONE is asserted. SERDES interface usage. There is a panel for each SERDES interface block. There are options to select if a SERDES interface is in use and if it is used for PCIe. When a SERDESIF block is used for PCIe, support for PCIe Hot Reset and L2/P2 compatibility can be selected. When a 090 device is targeted, the checkboxes for PCIe Hot Reset and L2/P2 support should be left unchecked because the SERDESIF block in a 090 device inherently supports PCIe Hot Reset and L2/P2 power states. A checkbox allows support for soft reset inputs to be selected. When this checkbox is checked, the SOFT_* inputs to the core can be used to assert the various reset outputs from the core. The SOFT_* inputs are typically driven by an instance of the CoreConfigP block. CoreResetP v7.0 Handbook 9

Tool Flows Figure 2 CoreResetP Configurations Window 10 CoreResetP v7.0 Handbook

Timing Diagrams Figure 3 to Figure 6 show the timing of reset signals for reset sequences initiated by the assertion of POWER_ON_RESET_N, FIC_2_APB_M_PRESET_N, EXT_RESET_IN_N, and USER_FAB_RESET_IN_N signals. POWER_ON_RESET_N FAB_RESET_N USER_FAB_RESET_N RESET_N_F2M M3_RESET_N EXT_RESET_OUT MDDR_DDR_AXI_S_CORE_RESET_N FDDR_CORE_RESET_N CONFIG_DONE FPLL_LOCK SDIFx_SPLL_LOCK SDIFx_PHY_RESET_N SDIFx_CORE_RESET_N DDR settling time INIT_DONE 130 us Figure 3 Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N CoreResetP v7.0 Handbook 11

Timing Diagrams FIC_2_APB_M_PRESET_N FAB_RESET_N USER_FAB_RESET_N RESET_N_F2M M3_RESET_N EXT_RESET_OUT MDDR_DDR_AXI_S_CORE_RESET_N FDDR_CORE_RESET_N CONFIG_DONE FPLL_LOCK SDIFx_SPLL_LOCK SDIFx_PHY_RESET_N SDIFx_CORE_RESET_N DDR settling time INIT_DONE 130 us Figure 4 Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N EXT_RESET_IN_N FAB_RESET_N USER_FAB_RESET_N RESET_N_F2M M3_RESET_N EXT_RESET_OUT MDDR_DDR_AXI_S_CORE_RESET_N FDDR_CORE_RESET_N CONFIG_DONE FPLL_LOCK SDIFx_SPLL_LOCK SDIFx_PHY_RESET_N SDIFx_CORE_RESET_N DDR settling time INIT_DONE 130 us Figure 5 Timing for Reset Signals Initiated by the Assertion of EXT_RESET_IN_N 12 CoreResetP v7.0 Handbook

SmartDesign USER_FAB_RESET_IN_N FAB_RESET_N USER_FAB_RESET_N RESET_N_F2M M3_RESET_N EXT_RESET_OUT MDDR_DDR_AXI_S_CORE_RESET_N FDDR_CORE_RESET_N CONFIG_DONE FPLL_LOCK SDIFx_SPLL_LOCK SDIFx_PHY_RESET_N SDIFx_CORE_RESET_N DDR settling time INIT_DONE 130 us Figure 6 Timing for Reset Signals Initiated by the Assertion of USER_FAB_RESET_IN_N CoreResetP v7.0 Handbook 13

List of Changes The following table lists critical changes that were made in each revision of the document. Date Change Page June 2014 CoreResetP v7.0 release. N/A January 2014 CoreResetP v5.1 release. N/A July 2013 CoreResetP v4.0 release. N/A June 2013 CoreResetP v3.0 release. N/A CoreResetP v7.0 Handbook 15

Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 650. 318.8044 Customer Technical Support Center Technical Support Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Visit the Microsemi SoC Products Group Customer Support website for more information and support (http://www.microsemi.com/soc/support/search/default.aspx). Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on website. Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group home page, at http://www.microsemi.com/soc/. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is soc_tech@microsemi.com. My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. CoreResetP v7.0 Handbook 17

Product Support Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email (soc_tech@microsemi.com) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via soc_tech_itar@microsemi.com. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. 18 CoreResetP v7.0 Handbook

Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1(949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: sales.support@microsemi.com Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices, and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at www.microsemi.com. 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 50200461-3/06.14