Agile Hardware Design: Building Chips with Small Teams

2017 SiFive. All Rights Reserved. Agile Hardware Design: Building Chips with Small Teams Yunsup Lee ASPIRE Graduate 2016 Co-Founder and CTO

2 2017 SiFive. All Rights Reserved. World s First Single-Chip Microprocessor That Communicates Directly Using Light

Chip (Processor mode) Memory to processor link read data Chip (Memory mode) 1MB memory bank (inactive) RISC-V processor Memory controller Electrical bus Receiver Transmitter PD Laser Optical amplifier 50/50 Power Splitter Single-mode fiber Optical amplifier PD Transmitter Receiver Interface 1MB memory bank RISC-V processor (inactive) Command + address + write data Control FPGA Processor to memory link 3 2016 SiFive. All Rights Reserved.

4 2017 SiFive. All Rights Reserved. How did we build working microprocessors with such a small team?

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11 2017 SiFive. All Rights Reserved. But there were the unknown unknowns along the way

Termination Resistor Connects to Pad Wait, why are all outputs floating? Pad Output Drivers 12 2016 SiFive. All Rights Reserved.

To Pad Dude, where s my Termination Resistor?? Output drivers not connected to pad!!! Pad Output Drivers LVS check doesn t catch problems when the S is incorrect 13 2016 SiFive. All Rights Reserved.

Analog VDD Decoupling Caps VDD Decoupling Caps I/O VDD Decoupling Caps Decoupling Caps are Too Far Away! 14 2016 SiFive. All Rights Reserved.

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Agile Hardware Design Big tape-out Small tape-out Tape-in ASIC flow FPGA C++ Specification Design Implementation 16 2016 SiFive. All Rights Reserved.

! RocketChip 17 2017 SiFive. All Rights Reserved.

10+ Tapeouts at Berkeley Raven-1 Raven-2 Raven-3 Raven3.5 Raven-4 May Apr Aug Feb Jul Sep Mar Nov 2011 2012 2013 2014 2015 EOS22 Mar Apr SWERVE EOS24 EOS14 EOS16 EOS18 EOS20 18 2017 SiFive. All Rights Reserved.

Enabling Small Teams to Build Custom Silicon 2017 SiFive. All Rights Reserved.

Custom Silicon For All We contribute to the open-source Freedom SoC platform based on RISC-V and open-source infrastructure We build customized Freedom SoCs as a service, which is quick, easy, and predictable at low upfront cost System Designer Product Requirements Custom Freedom SoCs Chip Design Factory Fabs 3 rd Party IP EDA Tools Packaging/Test Logistics 20 2017 SiFive. All Rights Reserved.

2017 SiFive. All Rights Reserved. Freedom Everywhere SoCs Low power, 32-bit microcontrollers

Freedom E310 First RISC-V based SoC based on the Freedom Everywhere SoC platform Target markets: IoT, Wearables, Embedded Low-power, low-cost, high-performance Open-source software and tools support 22

JTAG Freedom E310 Chip Block Diagram First RISC-V SoC based on the Freedom Everywhere SoC platform FE310-G000 Chip TAPC dip eip lip E31 Coreplex Instruction Cache Refill M Instruction Cache (16KiB, 2-way) Branch Prediction Instruction Fetch Instruction Buffer Inst. Decompressor RV32IMAC Multiplier/Divider Load/Store Data SRAM (16KiB) Debug Module Debug RAM (28B) Platform-Level Interrupt Control Coreplex-Local Interrupt Control M M Global Interrupts Real-Time Clock Ticks C-Bus: TileLink B32 D32 M P-Bus: TileLink B32 D32 Core Reset Sync rtccmpip wdogcmpip M A-Bus: TileLink B4 D32 GPIO Complex UART0 UART1 PWM0 (16-bit) PWM1 (8-bit) QSPI1 QSPI2 QSPI0 OTP (8KiB) Mask ROM (8KiB) Clock Generation PLL HFXOSC HFROSC Always-On Domain Backup Registers PMU hfclkrst corerst Real-Time Clock Watchdog LFROSC Reset Unit 3.3V MOFF Pads 1.8V MOFF Core GPIO psd* QSPI Flash vddpll vsspll hfxoscin hfxoscout 1.8V AON Pads 1.8V AON Core vddpaden dwakeup_n psdaon* erst_n 320+ MHz SiFive E31 CPU 1.61 DMIPS/MHz 16KB L1 I$ 16KB Data Scratchpad Hardware Multiply/Divide Debug Module Multiple Power Domains Low Power Standby Wide Range of Clock Inputs TSMC180G 6mmx6mm 48-Pin QFN 23 2017 SiFive. All Rights Reserved.

Freedom E310 Chip ~6mm 2 in TSMC 180nm 24 2017 SiFive. All Rights Reserved.

HiFive1: Arduino-Compatible RISC-V Dev Kit Powered by the Freedom E310 chip $59, https://www.crowdsupply.com/sifive/hifive1 Operating Voltage: 3.3 V and 1.8 V Input Voltage: 5 V USB or 7-12 VDC Jack IO Voltages: Both 3.3 V or 5 V supported Digital I/O Pins: 19 PWM Pins: 9 SPI Controllers/HW CS Pins: 1/3 External Interrupt Pins: 19 External Wakeup Pins: 1 Flash Memory: 128 Mbit Off-Chip (ISSI SPI Flash) Host Interface (microusb): Program, Debug, and Serial Communication 25 2017 SiFive. All Rights Reserved.

2017 SiFive. All Rights Reserved. Freedom Unleashed SoCs 64-bit multi-core SoCs for embedded computing

Freedom U500 Base Platform Block Diagram TSMC 28nm Chip for Rapid Customization of the Freedom Unleashed Platform JTAG Debug Module Boot ROM E51 Core 0 L1 I$ RV64IMAC SRAM U54-MC Coreplex Platform-Level Interrupt Control U54 U54 U54 Core U54 Core Core 1-4 Core 16KiB L1 I$ 16KiB L1 L1 L1 I$ I$ I$ RV64GC RV64GC 16KiB L1 D$ 16KiB L1 L1 L1 D$ D$ D$ TileLink Switch TileLink Coherence Manager Banked L2$ DDR3/4 Controller/PHY M M TileLink Switch TileLink Switch FU500 Base Platform ChipLink GbE OTP Mask ROM SD Card Quad SPI SPI I2C UART GPIO Clock Generation Clock/Reset Control FPGA ChipLink TileLink TileLink Switch Your IP Block PCIe/USB/ MIPI U54-MC Coreplex Single- and Doubleprecision floatingpoint support Banked L2$ with directory-based cache-coherence Modern OS support ChipLink Serialized Chip-to- Chip TileLink Interconnect GbE Peripherals DDR3/4 27 2017 SiFive. All Rights Reserved.

ChipLink Freedom U500 Base Platform Chip OTP U54 U54 L2$ E51 U54 U54 GbE ~30mm 2 in TSMC 28nm DDR 250M transistors 1.5 GHz+ SiFive E51/U54 CPU 1x E51: 16KB L1I$ and 8KB DTIM 4x U54: 32KB L1I$ and 32KB L1D$ ECC support Banked 2MB L2$ ECC support TSMC 28HPC FCBGA package Development board available in Q1 2018 28 2017 SiFive. All Rights Reserved.

What s Next? Taking Agile Hardware Design to the Next Level Agile Verification: Did we build the thing right? What role does Chisel/FIRRTL play? Formal verification methodology on the horizon Agile Validation: Did we build the right thing? On-demand FPGAs (e.g., Amazon F1) will play big role High-fidelity emulation will become more important Agile Analog Design How do we write portable Analog design? Enabling agile hardware design will spur innovation! 29 2017 SiFive. All Rights Reserved.