Arithmetic Logic nit The arithmetic logic unit AL performs arithmetic, logic and shift operations. It is composed of three blocks namely the logic, arithmetic and shift blocks. Each block performs different internal functions depending on the control lines K,,. The and Y inputs are simultaneously applied to the three blocks. The required output is selected using the control lines K4, K5 as shown in the figure and table below. The top-level architecture of the AL Y...... Shift Block K K 2 K 3 Logic Block K K 2 Arithmetic Block K K 2 K 3 Z' Z Z' K 4 K 5 n s Z K5 K4 Z=Z' arithmetic Z=Z logic Z=Z' shift Not used
-The Logic Block This block performs the bitwise AN, OR, OR, NOT operations. The output is selected by the control lines K and. K Operation Instruction mnemonic Z = AN Y AN,Y Z = OR Y OR,Y Z = OR Y OR,Y Z = NOT x NOT Logic implementation of the logic block Y 3 2 3 2 K I3 I2 I I S S 4: I3 I2 I I S S 4: I3 I2 I I S S 4: I3 I2 I I S S 4: Z 3 Z 2 Z Z 2-Arithmetic Block: This block performs the basic arithmetic operations, namely addition, subtraction, increment and decrement Logic implementation of the arithmetic block The operations that the arithmetic block can perform
K Operation Instruction mnemonic Z' = + Y A,Y Z' = + Y + C AC,Y Z' = Y SB,Y Z' = Y C SBB,Y Z' = + INC Z' = EC Y3 3 Y2 2 Y Y C I I 2: S K I I 2: S K Y Co. A. Ci Y Co. A. Ci Y Co. A. Ci Y Co. A. Ci Co3 Z 3 Z 2 Notes: Other combinations of K, and that are not listed in the table above are not used. The carry flag flip flop stores Co 3 in case of addition and stores C o3 in case of subtraction. If = then we are performing an addition operation (A or AC or INC) else we are performing a subtraction operation (SB or SBB or EC). Z Z Logic implementation of the carry flag K 2 Co3 C C OT
3-Shift Block: This block has single operand. It can carry out single bit shift and rotate operations in both left and right direction. The logic implementation of the shift block is as shown C 3 C 3 I3 I2 I I S S 4: I3 I2 I I S S 4: 2 3 2 I I 2: S K I I 2: S K I I 2: S K I I 2: S K Z 3 ' Z 2 ' Z ' Z ' If K = Z' = LSsin = left shift serial input Z' = this is left shift Z2' = Zn' = 2 If K= Z '= this is right shift Z' = 2 Z2' = 3 Z3'= RSsin = right shift serial input The generation of LS and RS signals and the corresponding operations Realized unction Shift left Shift arithmetic left Rotate left Rotate left through carry LS SIN 4 To 2 3 n C OT
Operation Shift right Shift arithmetic right Rotate right Rotate right through carry RS SIN 4 To 2 3 n C OT Therefore, the shift block has the following operations: K Operation Instruction mnemonic Shift left SHL Shift right SHR Shift arithmetic left SAL Shift arithmetic right SAR Rotate left ROL Rotate right ROR Rotate through carry left RCL Rotate through carry right RCR Notes SAL and SHL are the same whereas SAR differs from SHR in that it copies the sign bit n into Z n ' and Z n- '. In all shift and rotate operations,there is a bit shifted out and a vacant location results.the vacant location is filled by LS sin or RS sin.the bit shifted out is always stored in the carry flag flip flop. The Symbol of the AL is AL Z Y Y K5 K4 K
The Complete unctions List K5 K4 K Operation Category Z = + Y Z = + Y + C Z = Y Arithmetic Z = Y C Z = + Z = Z = AN Y Z = OR Y Z = OR Y Logic Z = NOT Z = SHL () Z = SHR () Z = SAL () Z = SAR () Z = ROL () Shift Z = ROR () Z = RCL () Z = RCR () The carry flag flip flop: In case of arithmetic and shift operation, the result z has one bit more than the input operands (, Y). This extra bit is the output carry in case of addition or the output borrow in case of subtraction or the bit shifted out in case of shift operations. The logic implementation of the carry flag is as follows: Co3 4 TO 2 3 Carry lag.. 3 2 TO K5 K4 K
Note: C= for all logic operations 8/6 bit AL: This AL will be modified so that it can perform 8bit operations as well as 6 bit operations. An additional control line k6 is required to select between the two cases. Operations type 8 bits 6 bits The following changes are needed in the shift block LS SIN 4 To 2 3 C OT 7 5 RS SIN 4 To 2 3 C OT 7 5 RS sin 4 RS sin 8 6 LS sin 5 7 K 6.. K Z 5 ' Z 7 '" Z '
AL LAGS: These flags store extra bits that are needed later for further processing or store important features of the result. These flags are grouped in a 6 bit register (with independent LOA for each flip flop) The format of the flags register is as follows. x x x x O I T S Z A P C Carry lags (C): (This flags stores) Stored bit Name Instructions Type C7 Addition carry A, AC, INC 8bits addition C5 Addition carry A, AC, INC 6bits addition C 7 Subtraction borrow SB, SBB, EC 8bits subtraction C 5 Subtraction borrow SB, SBB, EC 6bits subtraction Shifted out bit SHR, SAR, ROR, RCR Right shifts 7 Shifted out bit SHL, SAL, ROL, RCL 8bits left shifts 5 Shifted out bit SHL, SAL, ROL, RCL 6bits left shifts Logic Implementation of the carry flag C7 C5 2 3 4 TO Carry lag.. 7 5 2 TO K5 K4 K
Parity lag (P): This flag stores the parity bit of the result. If the result contains an even number of ones, the parity bit is else it is zero Logic implementation of the parity flag Z Z7 Z Z5 Parity lag.. Auxiliary lag (A): This flag is needed for adjusting decimal addition or subtraction. The 888 µp decimal adjusts 8 bits addition or subtraction only; therefore one auxiliary carry is needed. C3 A.. Zero lag (Z): This flag is set if the result is zero. The zero flag is not affected by the carry bit. This flag is affected by arithmetic, logic or shift operations. Z Z7 Z Z5 Zero-lag..
Sign lag (S): The sign flag stores the most signification bit of the result. It is affected by all the instructions of the AL. Z7 Z5 S.. K 6 Over low lag (O): This flag is set in case of an over flow either in case of arithmetic or shift operations. 8 bit arithmetic: If C6= and (7 and Y7 =) then O= Or C6= and (7and Y7 =) then O= The condition 7 = Y7 = C7 = And 7 = Y7 = C7 = Therefore O= when (C6= and C7= ) or when (C6= and C7=) 6 bit arithmetic: If C4= and (5 and Y5 =) then O= Or C4= and (5 and Y5 =) then O= The condition 5 = Y5 = C5 = And 5 = Y5 = C5 = Therefore O= when (C4= and C5= ) or when (C4= and C5=) Shift overflow occurs if the sign of the result is different from the sign of the operand The full logic implementation of the overflow flag is:
C6 C7 C4 C5 Overflow.. K5 7 Z7 5 Z5 Trap lag (T): It is used to force the 888 µp into single step mod of operation. After the completion of an instruction, the µp executes the INT routine if trap flag is set.else, nothing happens. Interrupt lag (I): External interrupts on INT pin are enabled if this flag is set; else interrupts on this pin are disabled. This flag is set by the instruction STI and is cleared by the instruction CLI. irection flag (): This flag select auto increment for SI and I if flag=; else SI and I are decremented =. It is important for the string instructions.
The AL is connected to the 8/6bits bus as follows: Bus High Bus Low TH TL T2H T2L Y Z Z7 8/6 AL Z8 Z5 K- AH AL BH BL EN Exercise: ind new values of registers affected and the state of the flags. Instruction(s) Initial Values New Values SBB AL,BL AL=85,BL=95,C= AL= AS AL= A AL,87 AL=89 AL= ROR AL,CL AL=82,CL=A AL= SAL AL, AL=73 AL= RCR AL, AL=73 C= AL= CHG AL=73 BL=37 AL= AL,BL BL= A BL,5 BL= 6 BL= AA BL= TEST AL, AL= 5A AL= OR AL, AL=55 AL= SB A,B A=56BC,B=47C A= B= A =7, C=3333 =,C AN A,B C= A=5555 C=5AAA A= C= C Z O A