Partitioning for Better Synthesis Results

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3 Partitioning for Better Synthesis Results Learning Objectives After completing this lab, you should be able to: Use the group and ungroup commands to repartition a design within Design Analyzer Analyze the partitioning of a design, and if necessary, repartition the design Lab Duration: 30 minutes Partitioning Lab 3-1 Synopsys 31833-000-S38

Exercise Flow Diagram Read mapped/ my_first_design.db Analyze partitioning, Highlight critical path Remove all designs from Design Analyzer Read unmapped/ PRGRM_CNT_TOP.db Repartition using group or ungroup Apply scripts/example.scr Compile Generate a constraint report Quit Design Analyzer Lab 3-2 Partitioning

Task 1. Analyze Partitioning of PRGRM_CNT_TOP 1. If not open yet from the previous lab, start Design Analyzer and open the Command Window. 2. Choose File Read. 3. Double click on the mapped directory, then my_first_design.db. 4. Go to the Schematic View of PRGRM_CNT_TOP and highlight the critical path. Push into the subblocks to see the critical path start and end points. Notice that the path traverses a block that is completely combinational. This violates one of the partitioning rules discussed during lecture. The hierarchical boundaries limit Design Compiler s ability to optimize the combinational logic in this timing path. 5. In the space below, draw the block diagram for PRGRM_CNT_TOP, and indicate where the critical path start and end points are. Think about which partitioning guidelines the design violates. How can you improve the partitioning of this design? Original Partitioning After Re-Partitioning You will correct the partitioning problem by using the Design Compiler commands group and ungroup. 6. Remove all designs from the Designs View. Partitioning Lab 3-3

Task 2. Read Source Code and Repartition 1. Read the unmapped design unmapped/prgrm_cnt_top.db. 2. Go to the Schematic View of PRGRM_CNT_TOP. Select the designs labeled PRGRM_DECODE and PRGRM_CNT. 3. Choose Edit Group. 4. Enter the New Design Name NEW_PC. 5. Enter a cell name: I_NEW_PC. 6. Click OK. Note: A box labeled NEW_PC replaces the two selected cells. 7. Go to the Schematic View of instance I_NEW_PC (design NEW_PC). Make sure you are in the Schematic View, and that you are looking at the schematic of NEW_PC. Look at the bottom of the Design Analyzer window and verify that the Current Instance is I_NEW_PC. 8. Select both cells I_PRGRM_DECODE and I_PRGRM_CNT. 9. Choose Edit Ungroup. 10. Click OK. Lab 3-4 Partitioning

Task 3. Compile and Analyze Results 1. Go up the hierarchy to the Symbol or Schematic View of PRGRM_CNT_TOP. Look at the bottom of the Design Analyzer window to make sure the current_design is PRGRM_CNT_TOP. 2. Execute the script file scripts/example.scr. 3. Perform a Design Optimization (compile) on PRGRM_CNT_TOP. 4. Generate a constraint report with All Violations. If no timing violations are reported, the design meets its timing constraints. 5. Select File Quit. There is no need to save this design, you will not be using it again. Click OK when asked if you really want to quit Design Analyzer. Partitioning Lab 3-5

Lab Review Questions Question 1. Why is it important to partition a design correctly in the source code? Question 2. What is one reason for not ungrouping the entire hierarchy and compiling a flattened design? Question 3. How would you have performed the repartioning of PRGM_DECODE and PRGRM_CNT using the dc_shell commands group and ungroup? (Use the manual pages, if necessary) current_design... group... current_design... Question 4. ungroup... What are 3 synthesis benefits you gain from good partitioning? Question 5. How do you implement partitioning in the RTL code? Question 6. List two partitioning guidelines that will help reduce compile run times. Question 7. Name one partitioning guideline that will help simplify setting constraints on a design. Lab 3-6 Partitioning

Answers / Solutions Answer to Block Diagram Original Partitioning Input Port PRGRM_CNT Clk PRGRM_ CNT_TOP PRGRM_ DECODE Data Pin of Register After Repartitioning Input Port Clk PRGRM_ CNT_TOP NEW_PC Partitioning Lab 3-7

Question 1. Why is it important to partition a design correctly in the source code? This makes script files easier and simpler to write because the synthesis steps are straightforward (you don t have to worry about repartitioning a design using ungroup and group). The source code is also more representative of the actual design. Question 2. What is one reason for not ungrouping the entire hierarchy and compiling a flattened design? One of the partitioning guidelines was to keep block sizes reasonable. If you ungroup the entire hierarchy of a top-level design that is large (200-300k gates), the compile time may increase significantly. Question 3. How would you have performed the repartioning of PRGM_DECODE and PRGRM_CNT using the dc_shell commands group and ungroup? current_design PRGRM_CNT_TOP group -design_name NEW_PC \ {I_PRGRM_DECODE I_PRGRM_CNT} current_design NEW_PC ungroup {I_PRGRM_DECODE I_PRGRM_CNT} Question 4. What are 3 synthesis benefits you gain from good partitioning? Improved synthesis results, simplify the synthesis process, and speed up compile run times. Question 5. How do you implement partitioning in the RTL code? Implement partitioning in the source code by placing blocks in separate entities (in VHDL) or modules (in Verilog). Question 6. List two partitioning guidelines that will help reduce compile run times. Keep the block sizes reasonable. Remove glue-logic between each block; keep all the logic at the lowest level leaf cells. Question 7. Name one partitioning guideline that will help simplify setting constraints on a design. Partition so that registers drive output ports. Lab 3-8 Partitioning

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