Using Electromagnetic Simulation for Developing Automotive EMC Design Guidelines Scott Piper General Motors
Design Guidelines A List of lessons learned These guidelines should be viewed not as an all-inclusive or binding set of rules Implementation of any set of design guidelines should be verified that they do not adversely affect performance of the product There are some cases where good engineering practice can be violated in order to satisfy these design guidelines which can cause a problem later in the design cycle.
Design Guidelines Where do they come from? Opinion from industry experts Previous experience Theoretical rule of thumb Example: Dr. Smartguy at an EMC seminar stated Don t locate circuitry between connectors therefore all products must follow this rule Example: Latest product doesn t pass their emissions limit. When we added a ferrite bead on the power line the product passes, therefore all future products must have ferrite beads Example: High speed traces on all products should be kept at least 2.5cm away from I/O connectors
Industry Experts Pros More experienced than you Successful at what they do Inexpensive Cons Experts will typically try to reach a broad audience what they say may not apply to your product May provide knowledge but not understanding
Previous Experience Pros Applies specifically to your product Colleagues will be more likely to follow these guidelines Cons A guideline could be developed from a misunderstood problem This problem may be specific to only one situation Doesn t prevent problems from occurring, only reduces the likelihood of the problem reoccurring (new technology is a problem) Can become outdated but difficult to remove from lessons learned
Theoretical Rule of Thumb Pros Understanding of the principle is required Can be adaptable from one product and another Easy to follow Cons The specifics of the guideline can be arbitrary such as keep digital traces 2.5cm away from I/O connectors why 2.5cm? Difficult to get people to follow these guidelines are viewed as someone s opinion and can be debated
Developing EMC Design Guidelines using Simulation
Getting Started with EM Simulation Taking already existing design guidelines/lessons learned and providing additional information through a series of EM simulation can be an effective way to create awareness of the benefits of simulation tools This is also a good exercise to anyone new to EM simulation tools and could use some practice applying skills to solve typical problems that engineers face in the company.
Example: High Speed Traces Should Be Kept 2.5cm away from I/O Connectors This rule is to minimize electromagnetic cross-coupling from noisy traces (assuming the digital traces that cause noise do not exit the device through the same connector) I/O traces on a PCB are critical traces for EMC because they are attached to wires that can efficiently radiate EM energy similar to an antenna. It s important to consider the routing of these traces in a PCB design. Simulations will be run to show the importance of this design consideration and re-evaluate the 2.5cm keep out guideline.
10.5 cm I/O Trace PCB Setup The physical size of the PCB has been chosen somewhat arbitrarily s 50Ω Source The traces are loaded with 5pF to represent a typical CMOS circuit (this loading can vary from one device to another) The I/O trace is connected to a 1.7 meter unterminated wire (this represents a circuit isolated from chassis) 5pF Load A second wire is connected to the PCB plane and terminated through 50Ω to an infinite ground plane PCB Ground plane to trace spacing is 0.8mm (30 mils)
Field Probe Locations y x z
Initial Result (s=0.1 cm) The field appeared to be strongest 3m in the y direction
Parameter Sweep Trace Separation ( s ) will be changed to show the difference in emissions as a function of s
Results 10-1000 MHz
Electric Field at 69MHz
Electric Field at 3m (dbµv/m) Results as a function of s 140 130 120 Comparison Plot 30 MHz 300 MHz 550 MHz 767 MHz 110 100 90 80 70 60 50 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Trace Separation (cm) The data shows no significant change past 0.7cm for frequencies under 550 MHz This shows that in this case, 2 cm is more conservative than necessary unless higher frequencies are involved
Simulation Performed without I/O trace (wires still present and loaded)
Comparison Trace position on the PCB does not greatly impact emissions when the I/O trace is not present. Therefore the differences in emissions seen by adjusting the variable s are mostly related to the coupling between the traces
Smaller Spacing from Trace to Ground Plane (8 mils instead of 30 mils) Smaller plane to trace spacing causes less radiation overall and spacing matters less below 200MHz For instance, the difference between 0.19 cm and 0.27 cm separation on a 30 mil board
Electric Field at 3m (dbµv/m) Closer Plane Spacing as a function of s 140 120 Closer Trace to Plane Spacing Comparison Plot 30 MHz 300 MHz 488 MHz 786 MHz 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Trace Separation (cm)
Filter Added 0.01µF
Results with Capacitor Filter The data shows that a 0.01µF Capacitor makes spacing less critical below 200 MHz
Noise trace changed so 2.8cm runs parallel to I/O (instead of 5.5cm)
Comparison noise trace length changed
Electric Field at 3m (dbµv/m) Result and Comparison as a function of s 120 100 Comparison - Shorter Parallel Run 30 MHz 300 MHz 300 MHz - Longer Run 30 MHz - Longer run 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Trace Separation (cm) Changing the length of parallel run to the I/O trace decreased the emissions 3-5 db The effect of changing the spacing was not any more/less critical
Summary / Conclusion This data shows the following Closer HS to I/O trace spacing will cause greater amounts of product RF emissions After a certain spacing, there will be reduced benefit from further trace separation Closer reference plane to trace spacing can not only result in fewer emissions due to I/O wires, but this also makes the emissions less sensitive to the HS and I/O trace spacing I/O to HS trace spacing does not affect emissions at lower frequencies when the I/O line has a capacitor filter (in this particular case) Reducing the parallel trace length between I/O and HS traces reduces emissions, however the benefit of increasing the space between the traces remains constant HS or Digital traces or reset lines should be kept away from I/O connectors or ports guideline concept is applicable to products when evaluating a design but 2.5cm is not always the appropriate distance (in most cases, these traces could be closer together without a significant increase in radiation). While the more the better approach for trace separation may sound like a conservative approach, further separation of these traces can cost valuable PCB real-estate that could be used for other EMC benefiting features.
EM Simulation for EMC Design Guidelines Without modeling, engineers must rely on handbooks, equations, and graphs, all of which have limited applicability, as well as their own rules-of-thumb, developed through experience. These guidelines are usually based on assumptions that frequently do not exist in the problem at hand. -Dr. Bruce Archambeault EMI/EMC Computational Modeling Handbook
EM Simulation for EMC Design Guidelines Design guidelines can come from many sources What s important is that the concept behind the guideline is known so that judgements can be made on how important a guideline is to follow in particular situations EM Simulation tools can bring these guidelines to life to gain a better understanding of how a guideline applies to a particular product Some design guidelines are made conservative to cover a broad range of situations so by tailoring these guidelines to a particular situation, some accommodations can be made to reduce size, cost, or make provisions for other (more important) considerations.