K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD INTRODUCTION K0708 is a single-chip LCD driver LI for liquid crystal dot-matrix graphic display systems It incorporates 9 driver circuit for 4 commom and 8 segment and 4x8-bit bit-map RAM It is capable of interfacing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an onechip Display Data RAM And it generates internal signals for using LCD driving independent of microprocessor clock FATUR 4-Channel COMMON & 8-Channel GMNT Driver for DOT matrix LCD On-chip display data RAM : 4 X 8 = 89bits Display data is stored in display data RAM from MPU - RAM bit data : ON(), OFF(0) Internal timing generator circuit for dynamic display 8-bit parallel bi-directional data bus Applicable LCD duty : /4 Power supply voltages : Power supply voltage range : 45 ~ 55 V(VDD) LCD Driving voltage range : 80 ~ 70 V(VLCD = VDD - V) Wide operating temperature range : Ta = -30 ~ 85 High Voltage CMO process Package : available bumped chip M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD BLOCK DIAGRAM C C3 3 4 5 7 8 C33C4 VDD V V V3 V4 V V 3 CHANNL COMMON 3BIT HIFT RG 4 CHANNL GMNT DRIVR 4 CHANNL GMNT DRIVR 3 CHANNL COMMON DRIVR 3BIT HIFT RG HL PCLK F 4-BIT DATA LATCH 4-BIT DATA LATCH DIPLAY TIMING GNRATOR CIRCUIT C CR R OCILLATOR PAG & LIN Decoder DIPLAY DATA RAM 4 X 4 = 4,09 BIT DIPLAY DATA RAM 4 X 4 = 4,09 BIT PAG & LIN Decoder Column Decoder Column Decoder ADC RAM Address register RAM Address register TATU RGITR INTRUCTION DCODR INTRUCTION DCODR ITATU RGITR I/O BUFFR I/O RGITR I/O BUFFR 4 CB DB0 ~ DB7 RW R RTB CB M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD PAD CONFIGURATION 8 8 9 K0708 (TOP VIW) (0,0) Y X 85 50 54 53 ITM PAD NO X IZ Y UNIT CHIP IZ - 590 330 PAD PITCH - 90(MIN) ~ 53 5 40 BUMPD PAD IZ 54 ~ 85 40 5 8 ~ 8 5 40 9 ~ 50 40 5 m BUMPD PAD HIGHT ALL PAD 8 3 M/M-9-D00 3
PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD K0708 4 M/M-9-D00 PAD LOCATION PAD NO PAD NAM X Y PAD NO PAD NAM X Y PAD NO PAD NAM X Y PAD NO PAD NAM X Y 3 4 5 7 8 9 0 3 4 5 7 8 9 0 3 4 5 7 8 9 30 3 3 33 34 35 3 37 38 39 40 4 4 43 44 45 4 47 48 49 50 5 5 53 54 55 5 57 58 59 0 3 DUMMY DUMMY DUMMY V V V V4 V4 V4 V3 V3 V3 V V V V V V VDD VDD VDD V V V PCLK F HL ADC CB C CR R DB0 DB DB DB3 DB4 DB5 DB DB7 R RW CB RTB DUMMY DUMMY C C C3 C4 C5 C C7 C8 C9 C0-05 -5935-5477 -557-5037 -487-4597 -4377-457 -3937-377 -3497-377 -3057-837 -7-397 -77-957 -737-57 -97-077 -857-37 -47-97 3 43 43 83 903 3 343 53 783 003 75 47 759 305 3343 335 397 49 4559 4779 4999 59 5439 05-385 -95-05 -5-05 -935-845 -755-5 -575 4 5 7 8 9 70 7 7 73 74 75 7 77 78 79 80 8 8 83 84 85 8 87 88 89 90 9 9 93 94 95 9 97 98 99 00 0 0 03 04 05 0 07 08 09 0 3 4 5 7 8 9 0 3 4 5 C C C3 C4 C5 C C7 C8 C9 C0 C C C3 C4 C5 C C7 C8 C9 C30 C3 C3 DUMMY DUMMY 3 4 5 7 8 9 0 3 4 5 7 8 9 0 3 4 5 7 8 9 30 3 3 33 34 35 3 37 38 39 05 575 55 5535 5445 5355 55 575 5085 4995 4905 485 475 435 4545 4455 435 475 485 4095 4005 395 385 3735 345 3555 345 3375 385 395 305 305 95 835 745 55 55 475 385 95-485 -395-305 -5-5 -35 535 435 335 335 435 5035 5935 835 7735 835 9535 0435 335 35 335 4035 7 8 9 30 3 3 33 34 35 3 37 38 39 40 4 4 43 44 45 4 47 48 49 50 5 5 53 54 55 5 57 58 59 0 3 4 5 7 8 9 70 7 7 73 74 75 7 77 78 79 80 8 8 83 84 85 8 87 88 89 40 4 4 43 44 45 4 47 48 49 50 5 5 53 54 55 5 57 58 59 0 3 4 5 7 8 9 70 7 7 73 74 75 7 77 78 79 80 8 8 83 84 85 8 87 88 89 90 9 9 93 94 95 9 97 98 99 00 0 0 05 5 05 935 845 755 5 575 485 395 305 5 5 035 945 855 75 75 585 495 405 35 5 35 45-45 -35-5 -35-405 -495-585 -75-75 -855-945 -035-5 -5-305 -395-485 -575-5 -755-845 -935-05 -5-05 -95-385 -475-55 -55-745 -835-95 -305-305 -395-385 -3375 90 9 9 93 94 95 9 97 98 99 00 0 0 03 04 05 0 07 08 09 0 3 4 5 7 8 9 0 3 4 5 7 8 9 30 3 3 33 34 35 3 37 38 39 40 4 4 43 44 45 4 47 48 49 50 03 04 05 0 07 08 09 0 3 4 5 7 8 9 0 3 4 5 7 8 DUMMY DUMMY DUMMY C4 C3 C C C0 C59 C58 C57 C5 C55 C54 C53 C5 C5 C50 C49 C48 C47 C4 C45 C44 C43 C4 C4 C40 C39 C38 C37 C3 C35 C34 C33-345 -3555-345 -3735-385 -395-4005 -4095-485 -475-435 -445-4545 -435-475 -485-4905 -4995-5085 -575-55 -5355-5445 -5535-55 -575-5935 -05 4035 335 35 335 0435 9535 835 7735 835 5935 5035 435 335 335 435 535-35 -5-5 -305-395 -485-575 -5-755 -845-935 -05-5 -05-95 -385
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD PAD DCRIPTION Power upply Name I/O Description VDD upply Power supply V upply Ground V upply For LCD driver circuit, V V, V3 V4, upply LCD driver supply voltages The voltages must satisfy the following relationship VDD ˆ ˆ V ˆ V ˆ V3 ˆ V4 ˆ ˆ V Oscillator Name I/O Description RC Oscillator ) Internal clock C O R Rf K0708 CR Cf C Rf : 47k Cf : 0pF CR R I O ) xternal clock K0708 R CR C OPN xternal clock Open Frequency election When the frame frequency is 70Hz, the oscillation frequency should be as following table F I F - Oscillation Frequency fose = 430 khz 0 fosc = 5kHz M/M-9-D00 5
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Microprocessor Interface Name I/O Description CB I First Chip( ~ 4) elect input Data input/output is enabled via, R, RW, and DB[0:7]when CB = Low CB I econd Chip(5 ~ 8) elect input Data input/output is enabled via, R, RW, and DB[0:7] when CB = Low R I Register election - HIGH : The data in DB[7:0] is display data - LOW : The data in DB[7:0] is control data Read or Write RW Description RW I H Data appears at DB< 7:0 > when = High L Display data DB < 7:0 > can be written at falling edge of nable signal RW H Description Read data in DB< 7:0 > appears the while is high level L Display data DB < 7:0 > is latched at falling edge of DB0 ~ DB7 I/0 Data Bus [0 ~ 7] - Bi-directional data bus Reset Name I/O Description RTB I Reset input - Chip is initialized when RTB is LOW M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD LCD Driver Outputs Name I/O Description C ~ C4 O LCD driver common output ~ 8 O LCD driver segment output Phase of internal shift clock (CLK) PCLK I PCLK Phase of Internal hift Clock (CLK) 0 Data shift at the falling edge of CLK Data shift at the rising edge of CLK Address Control signal of Y address counter ADC egment output direction ADC I H 3 5 7 8 L 4 3 8 7 5 election of data shift direction HL Data shift direction HL I H C C C3 C C3 C4 L C4 C3 C C3 C C M/M-9-D00 7
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD FUNCTIONAL DCRIPTION Chip elect input The K0708 has two chip select pin, CB and CB It can interface with a mircoprocessor when these pins(cb or CB)is Low When both of these pins are set to High, DB0 to DB7 are high impedance and R, RW, and inputs are disabled CB pin controls the display status of to 4, and CB does that of 5 to 8 When CB and CB are Low at the same time, it is impossible to execute read operation Therefore one of CB or CB should be set to Low((CB = H & CB = L )or (CB = L & CB = H )) in read operation The RTB signal is entered independet of the status of Chip elect CB CB Read Operation Write Operation C C C C H H X X X X L H X X H L X X L L - - ( - : Not Recommended, : Operation, X : No Operation) Table Relationship between Chip elect pins and Read/Write Operation Microprocessor Interface K0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the K0708 through the 8-bit I/O buffer(db0 TO DB7) R, RW and identify the type of parallel data transfer to be made as shown in table R RW Description H H Display data read H L Display data write L H tatus read L L Writes to internal register (Instruction) Table Microprocessor Interface M/M-9-D00 8
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Busy flag Busy flag indicates whether K0708 is operating or not When busy flag is high, K0708 is in internal operation When low, K0708 can accept the data or instruction DB7 indicates busy flag of the K0708 BUY FLAG TBUY 4/ fosc Figure Busy timing Display Timing Generator Circuit This section explains how the timing generation circuit operates - ignal generation to display start line counter and display data latch circuit - The display clock(clk) generates a clock to the line counter The display start line address of the display RAM is synchronized with the display clock 8-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pin - LCD AC signal(m) generation M/M-9-D00 9
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Display Data RAM The Display Data RAM stores pixel data for the LCD It is a 8-column x 4-row addressable array as shown in Figure 3 The 4 rows are divided into 8 pages of 8 lines Data is read from or written to the 8 lines of each page directly through DB0 to DB7 The microprocessor reads from and writes to RAM through the I/O buffer ince the LCD controller operates independently, data can be written to RAM at the same time as data is being displayed, without causing the LCD to flick DB0 0 0 0 DB 0 0 0 DB 0 0 0 DB3 0 0 0 DB4 0 0 0 DB5 0 0 0 DB 0 0 0 DB7 0 0 0 0 0 COM COM COM3 COM4 COM5 COM COM7 COM8 ( Display Data RAM ) ( LCD Panel ) Figure RAM-to-LCD data transfer M/M-9-D00 0
PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD K0708 M/M-9-D00 Page address Line address GMNT OUTPUT(~4) DATA BU GMNT OUTPUT(5~8) Line address Page address 3 4 3 4 5 7 8 5 7 8 0000 00 0 0 03 04 05 0 07 DB0 DB DB DB3 DB4 DB5 DB DB7 00 0 0 03 04 05 0 07 000 00 08 09 0 3 4 5 DB0 DB DB DB3 DB4 DB5 DB DB7 08 09 0 3 4 5 00 00 7 8 9 0 3 DB0 DB DB DB3 DB4 DB5 DB DB7 7 8 9 0 3 00 0 4 5 7 8 9 30 3 DB0 DB DB DB3 DB4 DB5 DB DB7 4 5 7 8 9 30 3 0 00 3 33 34 35 37 38 39 DB0 DB DB DB3 DB4 DB5 DB DB7 3 33 34 35 3 37 38 39 00 0 40 4 4 43 44 45 4 47 DB0 DB DB DB3 DB4 DB5 DB DB7 40 4 4 43 44 45 4 47 0
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD GMNT OUTPUT(~4) GMNT OUTPUT(5~8) Page address Line address 3 4 3 4 DATA BU 5 7 8 5 7 8 Line address Page address 0 48 49 50 5 5 53 54 55 DB0 DB DB DB3 DB4 DB5 DB DB7 48 49 50 5 5 53 54 55 0 5 57 58 59 0 3 DB0 DB DB DB3 DB4 DB5 DB DB7 5 57 58 59 0 3 ADC 0 4 0 0 3 0 3 3 0 3 0 4 0 0 3 3 0 0 ADC Chip elect (CB) Column address Column address Chip elect (CB) Figure 3 Display Data RAM M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD MPU signal R RW DB[7:0] N D(N) D(N+) D(N+) D(N+3) D(N+4) D(N+5) Internal signal WR Input Buffer Column Address Page Address RAM N D(N) D(N+) D(N+) D(N+3) D(N+4) N N+ N+ N+3 N+4 N+5 Preset K et Page Address => K D(N) D(N+) D(N+) D(N+3) D(N+4) Figure 4 Write Timing MPU signal R RW DB[7:0] N Dummy D(N) D(N+) D(N+) D(N+3) Internal signal WR RD Output Buffer Dummy D(N) D(N+) D(N+) D(N+3) D(N+4) Column Address Page Address N N+ N+ N+3 N+4 N+5 Preset K et Page Address => K Figure 5 Read timing M/M-9-D00 3
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Data Tramsfer To match the timing of the display data RAM and registers to that of the controlling microprocessor, K0708 uses an internal data bus and bus buffer When the microprocessor reads the contents of display data RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle) On the next read cycle, the data is read from the bus buffer onto the microprocessor bus At the same time, the next block of data is transferred from RAM to the bus buffer Otherwise, when the microprocessor write data to display data RAM the data is written to RAM atfer the falling edge of Therefore, it is necessary to check Busy Flag to write or read the next data (refer to Figure4, 5) Page Address Register The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3) The microprocessor issues et Page Address instruction to change the page and to access another page Column Address Counter The column address counter is a -bit presettable counter that provides column address to display data RAM (refer to Figure 3) It is incremented by automatically after execution of each Read/Write Data instruction The column address counter loops the values 0 to 7, and it is independent of page address register The ADC pin is issued to change the relationship between RAM Column address and display segment output Display tart Line Register The display start line register stores the line address of display data RAM that corresponds to the first (normally the top) line(com) of liquid crystal display(lcd) panel ee Figure 3 When displaying contents in display data RAM on the LCD panel, -bit data(db[5:0]) of the et Display tart Line is latched in display start line register Latched data are transferred to the line address counter just before COM is active High, presetting the line address counter The line counter is then incremented on the display latch clock signal once for every display line It is used for vertical scrolling of the liquid crystal display screen M/M-9-D00 4
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD LCD Driver LCD driver circuit has 9 outputs of 8 segment outputs, 4 common outputs for LCD driving ach common output has a shift register LCD driving output voltage is determined by the combination of display data and internal AC signal Display Data Common output egment output 0 V V4 V V3 Display OFF - V or V3 Table 4 Relationship between data for each input signal and the LCD drive output Reset Circuit Reset function can initialize system by setting RTB terminal at Low level When RTB becomes low, following procedure occurs - Display start line : 0(First) - Display ON/OFF : OFF While RTB is in Low level, no instruction except tatus Read can be accepted Reset status appears at DB4 Refers to Read tatus of 'INTRUCTION DCRIPTION ' The conditions of power supply at initial power up are shown in table 3 Item ymbol Min Typ Max Unit Reset time trtb 0 - - us Rise time tr - - 00 ns Table 5 Power supply initial Conditions VDD RTB trtb tr 07VDD 03VDD Figure Reset Timing M/M-9-D00 5
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD INTRUCTION DCRIPTION Instruction Table Instruction R RW DB7 DB DB5 DB4 DB3 DB DB DB0 Function Read display data Read data Write display data 0 Write data Reads data (DB[0:7]) from display data RAM to the data bus Writes data(db[0:7]) into display data RAM After writing instruction, column address is incremented by automatically tatus Read 0 BUY 0 ON/ OFF R- T 0 0 0 0 Reads status BUY -0 : Ready - : In operation ON/OFF -0 : Display ON - : Display OFF RT -0 : Normal - : Reset et Column Address 0 0 0 Column address (0 ~ 3) et Display tart Line 0 0 Display tart Line (0 ~ 3) et Page Address 0 0 0 Page (0 ~ 7) Display ON/OFF 0 0 0 0 0/ ets the Column address at the Column address counter Indicates the display data RAM displayed at the top of the screen ets the Page address at the Page address register Controls the display on or off Internal status and display RAM data is not affected L:OFF, H:ON M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Instructions Æ Read Display Data Reads 8-bit data display data RAM area specified by column address and page address As the column address is incremented by automatically after each read operation, the microprocessor can continue to read data of multiple words R RW DB7 DB DB5 DB4 DB3 DB DB DB0 Read data Æ Write Display Data Writes 8-bit data in display data RAM As the column address is incremented by automatically after each write operation, the microprocessor can continue to write data of multiple words R RW DB7 DB DB5 DB4 DB3 DB DB DB0 0 Write data Æ Read tatus Indicates the internal status conditions of the device to the microprocessor R RW DB7 DB DB5 DB4 DB3 DB DB DB0 0 BUY 0 ON/OFF RT 0 0 0 0 Flag BUY ON/OFF RT Description The device is busy due to internal operation or reset Any instruction is rejected until BUY goes Low Indicates whether the display is on or off When goes Low, the display is on When goes High, the display is off This is the opposite of Display ON/OFF instruction Indicates the initialization is in progress by RTB signal When Low, the chip is in active When High, the chip is being reset M/M-9-D00 7
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ et Page Address ets the page address of display RAM from the microprocessor into the page address register Along with Column address register, Page address register assigns the address of the display RAM to be written to or read from display data Changing the address doesn t affect the display status R RW DB7 DB DB5 DB4 DB3 DB DB DB0 0 0 0 X X X0 X X X0 Page 0 0 0 0 0 0 : : : : 7 Æ et Column Address ets the Column address of display RAM from the microprocessor into the Column address register When the microprocessor reads or writes display data to or from display RAM, the address are automatically incremented R RW DB7 DB DB5 DB4 DB3 DB DB DB0 0 0 0 Y5 Y4 Y3 Y Y Y0 Y5 Y4 Y3 Y Y Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : : : 0 3 M/M-9-D00 8
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ et Display tart Line ets the line address of display RAM to determine the display start line The display data on the specified line of the display RAM is displayed at the top row COM of LCD panel It is followed by the higher number of lines in ascending order corresponding to the determined duty cycle When this instruction changes the display start line address, the LCD panel can be scrolled R RW DB7 DB DB5 DB4 DB3 DB DB0 DB0 0 0 Z5 Z4 Z3 Z Z Z0 Z5 Z4 Z3 Z Z Z0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : : : 0 3 Æ Display ON/OFF Turns the display ON or OFF R RW DB7 DB DB5 DB4 DB3 DB DB0 DB0 0 0 0 0 D0 D0 = : Display ON D0 = 0 : Display OFF M/M-9-D00 9
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ APPLICATION DIAGRAM (ADC = H, HL = H) COM COM3 LCD Panel (4 x 8) G G G7 G8 COM33 COM4 7 8 C3 C CB R/W R DB[0:7] RTB K0708 (Bottom View) CB VDD V V V3 V4 V C4 C33 VDD V CB R DB[0:7] RTB MPU R/W CB V V3 V4 V Figure 7 Application Diagram M/M-9-D00 0
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ APPLICATION DIAGRAM (ADC = L, HL = H) COM33 COM3 LCD Panel (4 x 8) G G G7 G8 COM COM3 8 7 C4 C33 *CB R/W R DB[0:7] RTB K0708 (Top View) *CB V V V3 V4 V C3 C VDD V CB R DB[0:7] RTB MPU R/W *CB V V3 V4 * Note When ADC = L, connects chip select pins(cb,cb) as following - Cb (mpu) -> CB (K0708) - CB (MPU) -> CB (K0708) V Figure 8 Application Diagram M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ APPLICATION DIAGRAM3 (ADC = L, HL = L) VDD *CB DB[0:7] RTB MPU R/W R *CB V V V3 V4 C33 C4 *CB RW R DB[0:7] RTB *CB K0708 (Bottom View) V V4 V3 V V 8 7 C C3 V COM COM3 G G G7 G8 LCD Panel (4 x 8) COM33 COM4 * Note When ADC = L, connects chip select pins (CB, CB) as following - CB (MPU) -> CB (K0708) - CB (MPU) -> CB (K0708) Figure 9 Application Diagram 3 M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD Æ APPLICATION DIAGRAM4 (ADC = H, HL = L) VDD *CB DB[0:7] RTB MPU R/W R *CB V V V3 V4 C C3 *CB RW R DB[0:7] RTB *CB K0708 (Top View) V V4 V3 V V 7 8 C33 C4 V COM33 G G G7 G8 LCD Panel (4 x 8) COM COM3 COM4 Figure 0 Application Diagram 4 M/M-9-D00 3
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD PCIFICATION Absolute Maximum Ratings Parameter ymbol Rating Unit Note Operating voltage VDD -03 ~ +70 * upply Voltage V VDD-90 ~ VDD+03 V *4 Driver ypply Voltage Note : VB -03 ~ VDD+03 *,3 VLCD V-03 ~ VDD+03 * * Based on Vss = 0V * VLCD = VDD - V *3 Applies to HL, F, PCLK, CR, RTB, ADC, CB, CB,, RW, R and DB0 ~ DB7 *4 Voltage level VDD ˆ ˆ V ˆ V ˆ V3 ˆ V4 ˆ ˆ V Temperature Characteristics Parameter ymbol Rating Unit Note Operating temperature Topr -30 ~ +85 torage temperature Tstg -55 ~ +5 M/M-9-D00 4
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD lectrical Characteristics DC Characteristics (VDD = 45 ~ 55V, Ta = -30 ~ +85 ) Item ymbol Condition Min Typ Max Unit Note Operating Voltage VDD - 45-55 Input High Voltage Input Low Voltage VIH - 07VDD - VDD * VIH - 0 - VDD * VIL - 0-03VDD V * VIL - 0-08 * Output High Voltage VOH IOH = -00uA 4 - - Output Low Voltage VOL IOL = ma - - 04 Input Leakage Current ILKG VIN = V ~ VDD -0 - +0 *3 *4 Tri-state Leakage Current ITL VIN = V ~ VDD -50 - +50 ua *5 Driver Input Leakage Current IDLKG VIN = V ~ VDD -0 - +0 * Operating Current On resistance IDD During Display - - 08 *7 IDD During Access - - 0 ma *8 COM RONC VDD - V = 7V - - 5 *9 G RON ILOAD = 0mA - - 75 k *0 Oscillation frequency fosc Ta=5, VDD=5V Rf = 47k % Cf = 0pF 5% 35 450 585 KHz Note : * F, CR, ADC, HL, PCLK, RTB * CB, CB,, RW, R, DB0 ~ DB7 *3 DB0 ~ DB7 *4 xcepted DB0 ~ DB7 *5 DB0 ~ DB7 at High Impedence *, V, V, V3, V4, *7 C = 0pF, R = 47 k, fose = 450 KHz, DB0 ~ DB7 = VDD, Output = No Load *8 xcepted Clock = 430KHz, RAM Access Cycle = MHz *9 = 5V, V = 3V, V = 4V, V3 = -84V, V4 = -0V, = -V, C ~ C4 *0 = 5V, V = 3V, V = 4V, V3 = -84V, V4 = -0V, = -V, ~ 8 M/M-9-D00 5
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD AC Characteristics (VDD = 45 to 55V, Ta = -30 to +85 ) Mode Item ymbol Min Typ Max Unit Cycle Time tc 000 - - Rise / Fail Time tr, tf - - 5 Write Mode (Refer to Figure 9) Read Mode (Refer to Figure 0) Pulse Width(High, Low) tw 450 - - RW and R etup Time tsu 40 - - RW and R Hold Time th 0 - - Data etup Time tsu 00 - - Data Hold Time th 0 - - Cycle Time tc 000 - - Rise / Fall Time tr,tf - - 5 Pulse Width (High, Low) tw 450 - - Rw and Rs etup Time tsu 40 - - RW and R Hold Time th 0 - - Data Output Delay Time td - - 30 Data Hold Time tdh 0 - - ns ns M/M-9-D00
K0708 PRLIMINARY PCIFICATION 4COM/8G DRIV FOR DOT MATRIX LCD R VIH VIL tu th RW VIL VIL tw th VIH VIH tf tf VIL VIL tu th VIL DB0 ~ DB7 VIH VIL Valid Data tc VIH VIL Figure 9 Write Mode Timing Diagram R VIH VIL tu th RW VIH VIH tw th tf VIH VIH tr VIL td VIL tdh VIL DB0 ~ DB7 VIH VIL Valid Data VIH VIL tc Figure 0 Read Mode Timing Diagram M/M-9-D00 7