Tp-level flder: <Cipher_Name>_<Yur_First_Name> Secnd-level flders: 1_assumptins 2_blck_diagrams 3_interface 4_ASM_charts 5_surce_cdes 6_verificatin 7_timing_analysis 8_results 9_benchmarking 10_bug_reprts [BONUS] 11_feedback [BONUS] ECE 545 Prject Deliverables The recmmended cntent f these flders is described belw: 1_assumptins A file cntaining the descriptin f all assumptins (including pssible simplificatins) that yu have made. 2_blck_diagrams A. Please name and label all data buses and cntrl signals in yur circuit (at a minimum all inputs and utputs and all cntrl and status signals that appear at the interface between the Cntrller and Datapath). In rder t supprt debugging f yur cde, I wuld als suggest naming all intermediate buses and ndes f the Datapath that appear as signals in yur VHDL cde. B. All diagrams must be submitted in PDF. Yu can draw diagrams in a graphical editr f yur chice (e.g., Dia, Xfig, MS Visi). Yu can als submit scanned versins f handwritten blck diagrams. C. In the file: hierarchy.txt, please include the list f all blck diagram files, starting frm the blck diagram f yur tp-level unit dwn t the blck diagrams f yur lwestlevel cmpnents. D. BONUS: The cmplete editable versins f blck diagrams prepared using a graphical editr will be rewarded with bnus pints. Please nte that yu wuld still need t submit PDF versins.
3_interface A_tp_level B_divisin Re: A_tp_level This is a tp-level interface f yur circuit. Draw a diagram f yur interface, and describe the meanings f all inputs and utputs. Re: B_divisin Interface with the divisin int the Datapath and Cntrller. 4_ASM_charts A. If mre than ne FSM is used, please include a blck diagram illustrating cmmunicatin amng all FSMs. B. As a minimum, please include scans f yur handwritten ASM charts and the cntrller blck diagram in the PDF frmat. C. BONUS: The cmplete editable versins f ASM charts prepared using a graphical editr will be awarded with bnus pints. Please nte that yu wuld still need t submit PDF versins. 5_surce_cdes A. Please include all synthesizable VHDL cdes f the Datapath, the Cntrller, and the Tp- Level Circuit. B. Please include als a file surce_list.txt listing all files in the rder they shuld be synthesized (bttm-up). 6_verificatin [THIS PART IS EXTREMELY IMPORTANT AND MAY DETERMINE YOUR FINAL GRADE] In this flder include: A. The mdified reference C implementatin f yur algrithm, which yu have used t generate test vectrs.
B. All test vectr files yu have used fr verificatin and debugging. C. All testbenches used t verify yur circuit peratin at varius levels f hierarchy. D. Reprt describing: Tls used fr running C implementatins and generating test vectrs Yur strategy fr verificatin: rder f tests and testbenches used, surce and frmat f test vectrs Highest level entity verified fr functinal crrectness and the results f its verificatin If the result f any verificatin was negative (i.e., yur circuit did nt perate as expected), please describe incrrect behavir and try t explain the pssible surces f errrs. Verificatin f lwer-level entities (ptinal if the tp-level unit was verified t wrk crrectly): Name f an entity Test vectrs and their surce Testbench used fr verificatin Result f verificatin, crrect r incrrect behavir Pssible surces f errrs. 7_timing_analysis A. In the file timing.pdf please prvide the exact frmulas fr a. Key Setup Time, expressed in clck cycles b. Encryptin Time as a functin f the number f message blcks, n, and the number f assciated data blcks, m, expressed in clck cycles. c. Decryptin Time as a functin f the number f ciphertext blcks, n, and the number f assciated data blcks, m, expressed in clck cycles. d. Time between tw cnsecutive input blcks (in clck cycles), during prcessing f i. assciated data blcks ii. message blcks iii. ciphertext blcks
e. Thrughput fr lng inputs as a functin f the clck perid, T (calculated as a rati f the input blck size and the time between inputting tw cnsecutive input blcks) fr prcessing f i. assciated data blcks ii. message blcks iii. ciphertext blcks B. Please d yur best t cnfirm the executin time f yur circuit thrugh simulatin. Please clearly indicate in timing.pdf, which frmulas in yur reprt have been cnfirmed thrugh functinal simulatin, and which circuit was used in these simulatins (entire cre, datapath, ther?). 8_results Please submit the dcument results.xxx cntaining the fllwing results fr all r a subset f the fllwing entities verified fr functinal crrectness: I. Datapath II. Datapath + Cntrller III. Tp Level. Use the fllwing families f FPGAs t generate yur results: a. Xilinx Virtex-6 b. Altera Stratix IV GX [BONUS] A. resurce utilizatin a. LUTs b. Slices fr Virtex-6, ALMs fr Stratix IV GX c. Flip-flps d. BRAMs fr Virtex-6, amunt f embedded memry fr Stratix IV GX e. DSP units f. I/O pins B. numerical values f the fllwing timing parameters a. Minimum Clck Perid b. Maximum Clck Frequency c. Maximum Thrughput fr prcessing f a large number f i. assciated data blcks ii. message blcks iii. ciphertext blcks based n the minimum clck perid after placing and ruting. C. analysis f the btained results; yur bservatins and cnclusins. Clearly indicate the name f the entity fr which these results were btained.
9_benchmarking Divide this flder int subdirectries crrespnding t each individual family: a. Xilinx Virtex-6 b. Altera Stratix-IV. Fr each run f ATHENa please include nly: - reprt_ptin.txt - reprt_executin_time.txt - reprt_timing.txt - reprt_resurce_utilizatin.txt - reprt_summary.txt - athena_lg.txt, and - the cnfig subflder. In the flder summary please include the reprt file benchmarking.pdf cntaining - list f ptimizatin strategies (ATHENa applicatins) used t btain best results - Excel graphs and charts summarizing all results - analysis f the btained results; yur bservatins and cnclusins. 10_bug_reprts [BONUS] In this flder, please include the fllwing subflders 1_specificatin 2_ATHENa 3_Other Each bug reprt shuld be placed in a separate subflder f these directries, and named: bug_<n>_mm_dd, where mm_dd represents the mnth and day when a given prblem was discvered, and <n> is a unique bug number. Fr each bug yu reprt, please include shrt descriptin. In 1_specificatin please describe all mistakes yu have fund in the specificatin f the algrithm assigned t yu. These mistakes can include mistakes in the pseudcde, blck diagrams, figures, tables, explanatins, etc.
In 2_ATHENa please include all infrmatin necessary t recreate the same prblem (in particular, the versin f ATHENa used, design.cnfig.txt, surce files, versins f Xilinx and Altera tls used, simulatr used, etc.). 11_feedback [BONUS] In this flder, in the file feedback.pdf, describe any ideas fr the pssible tweaks in the cipher design that culd pssibly imprve r simplify hardware implementatin, withut affecting cipher s security.