Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak

Similar documents
ELCT201: DIGITAL LOGIC DESIGN

2.1 Binary Logic and Gates

Chapter 2 Combinational Logic Circuits

Digital Fundamentals. Integrated Circuit Technologies

ELCT201: DIGITAL LOGIC DESIGN

A B AB CD Objectives:

Digital Logic Lecture 7 Gate Level Minimization

Chapter 3. Gate-Level Minimization. Outlines

Chapter 2 Combinational

Gate-Level Minimization

ECE380 Digital Logic

Gate-Level Minimization

ENGIN 112 Intro to Electrical and Computer Engineering

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

Gate Level Minimization Map Method

CMPE223/CMSE222 Digital Logic

CprE 281: Digital Logic

Specifying logic functions

Simplification of Boolean Functions

Boolean Algebra and Logic Gates

Boolean Algebra. BME208 Logic Circuits Yalçın İŞLER

Combinational Logic Circuits

Gate-Level Minimization

Experiment 3: Logic Simplification

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

University of Technology

Combinational Logic Circuits Part III -Theoretical Foundations

Simplification of Boolean Functions

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Lecture (05) Boolean Algebra and Logic Gates

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB

Combinational Logic Circuits

Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010

Chapter 2. Boolean Expressions:

DIGITAL ELECTRONICS. Vayu Education of India

Chapter 2 Combinational Logic Circuits

DKT 122/3 DIGITAL SYSTEM 1

Computer Organization

CS8803: Advanced Digital Design for Embedded Hardware

Digital Logic Design. Outline

Chapter 2. Boolean Algebra and Logic Gates

UNIT II. Circuit minimization

Copyright 2000 N. AYDIN. All rights reserved. 1

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

Chapter 3 Simplification of Boolean functions

SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

Review: Standard forms of expressions

CD4023BC Buffered Triple 3-Input NAND Gate

Switching Circuits & Logic Design

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷

3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

Combinational Circuits Digital Logic (Materials taken primarily from:

R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.

Chap-2 Boolean Algebra

Gate Level Minimization

Chapter 6. Logic Design Optimization Chapter 6


Experiment 4 Boolean Functions Implementation

ENEL 353: Digital Circuits Midterm Examination

Gate-Level Minimization

Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

Standard Forms of Expression. Minterms and Maxterms

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

Module -7. Karnaugh Maps

X Y Z F=X+Y+Z

4 KARNAUGH MAP MINIMIZATION

QUESTION BANK FOR TEST

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

IT 201 Digital System Design Module II Notes

BOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Combinational Logic & Circuits

Digital Techniques. Lecture 1. 1 st Class

Gate-Level Minimization. section instructor: Ufuk Çelikcan

74VHC132 Quad 2-Input NAND Schmitt Trigger

74VHC14 Hex Schmitt Inverter

2.6 BOOLEAN FUNCTIONS

Chapter 3. Boolean Algebra and Digital Logic

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

MUX using Tri-State Buffers. Chapter 2 - Part 2 1

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Synthesis of combinational logic

2008 The McGraw-Hill Companies, Inc. All rights reserved.

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions

Boolean Analysis of Logic Circuits

CD4010C Hex Buffers (Non-Inverting)

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION

Transcription:

Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak

Content - Introduction -2 Feature -3 Feature of BJT -4 TTL -5 MOS -6 CMOS -7 K- Map

- Introduction Logic IC ASIC: Application Specific Integrated Circuits

- Introduction IC digital logic families 炷Resistor-transistor logic炸 DTL 炷Diode-transistor logic炸 TTL 炷Transistor -transistor logic炸 ECL 炷Emitter-coupled logic炸 MOS 炷Metal-oxide semiconductor炸 CMOS 炷Complementary Metal-oxide semiconductor炸 RTL

Positve logic and Negative logic Positive logic: H is set to be binary Negative logic: L is set to be binary

-2 Feature The feature to be concerned of IC logic families: fan-out The no. of standard loads can be connected to the output of the gate without degrading its normal operation Sometimes the term loading is used Power dissipation The power needed by the gate Expressed in mw Propagation delay The average transition-delay time for the signal to propagate from input to output when the binary signal changes in value Noise margin The unwanted signals are referred to as noise Noise margin is the maximum noise added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output

Computing fan-out I OH I OL Fan out min(, ) I IH I IL

Power dissipation I CCH I CCL I CC (avg) 2 PD (avg) I CC (avg) VCC For standard TTL I CCH ma, I CCL 3mA PD (avg)? Total PD (avg) in IC 74?

Propagation delay 5% VH 5% VH 5% VH For standard TTL t PHL 7ns, t PLH ns t P (avg)? 5% VH

Noise margin

Noise margin High-state noise margin=.4 Low-state noise margin=.4

-3 Feature of BJT BJT npn or pnp Si or Ge Si is used mainly npn is most popular

Table - Typical npn Transistor Parameters Region VBE (V) VCE (V) Current Relation Cutoff <.6 Open circuit IB=IC= Active.6-.7 >.8 IC =hfeib Saturation.7-.8.2 IB IC/hFE

Diode symbol and characteristic

-5 Transistor-Transistor Logic (TTL) The original basic TTL gate was a slight improvement over the DTL gate. There are several TTL subfamilies or series of the TTL technology. Eight TTL series appear in Table -2. Has a number start with 74 and follows with a suffix that identifies the series type, e.g 744, 74S86, 74ALS6. Three different types of output configurations:. open-collector output 2. Totem-pole output 3. Three-state (or tristate) output

Open-collector TTL Gate

Wired-AND of Two Open-Collector

Open-Collector Gates Forming a Common Bus Line In this case Y=?

TTL Gate with Totem-Pole Output

Schottky TTL Gate

Three-state TTL Gate

Objectives Karnaugh Maps (K-Maps) Learn to minimize a function using K-Maps 2-Variables 3-Variables 4-Variables Don t care conditions Important Definitions 5-Variables K-Maps

Simplification using Algebra F = X YZ + X YZ + XZ = X Y(Z+Z ) + XZ (id 4) = X Y. + XZ (id 7) = X Y + XZ (id 2) Simplification may mean different things here it means less number of literals

Simplification Revisited Algebraic methods for minimization is limited: No formal steps (id first, then id 4, etc?), need experience. No guarantee that a minimum is reached Easy to make mistakes Karnaugh maps (k-maps) is an alternative convenient way for minimization: A graphical technique Introduced by Maurice Karnaugh in 953 K-maps for up to 4 variables are straightforward to build Building higher order K-maps (5 or 6 variable) are a bit more cumbersome Simplified expression produced by K-maps are in SOP or POS forms

Truth Table Adjacencies A B F A B F These minterms are adjacent in a gray code sense they differ by only one bit. We can apply XY+XY =X F = A B + A B = A (B +B) = A () = A Same idea: F = A B + AB = B Keep common literal only!

K-Map A B F A different way to draw a truth table! Take advantage of adjacency B B A F = A B + AB = B A Keep common literal only! A B A B A B AB

Minimization with K-maps Draw a K-map 2. Combine maximum number of s following rules:.. 2. 3. Only adjacent squares can be combined All s must be covered Covering rectangles must be of size,,,, Check if all covering are really needed 4. Read off the SOP expression 3. n

2-variable K-map Given a function with 2 variables: F(X,Y), the total number of minterms are equal to 4: m, m, m2, m3 The size of the k-map is always equal to the total number of minterms. Each entry of the k-map corresponds to one minterm for the function: Row represents: X Y, X Y Row represents: XY, XY XY 2 3

Example Q. Simplify the function F X,Y = m,, Sol. This function has 2 variables, and three -squares (three minterms where function is ) F = m + m2 + m3 XY Y is the common literal Note: The -squares can be combined more than once in the adjacent -squares X is the common literal Minimized expression: F = X + Y

2 variable K-Maps (Adjacency) In an n-variable k-map, each square is adjacent to exactly n other squares Q: What if you have in all squares?

3-variable K-maps For 3-variable functions, the k-maps are larger and look different. Total number of minterms that need to be accommodated in the k-map = 8 To maintain adjacency neighbors don t have more than different bit B AC m A m4 B m m3 m5 m7 C m2 m6

3-variable K-maps Note: You can only combine a power of 2 adjacent -squares. For e.g. 2, 4, 8, 6 squares. You cannot combine 3, 7 or 5 squares Minterms mo, m2, m4, m6 can be combined as m and m2 are adjacent to each other, m4 and m6 are adjacent to each other mo and m4 are also adjacent to each other, m2 and m6 are also adjacent to each other

Example Simplify F = m,,,, using K-map B BC A 3 4 A 2 5 7 6 C

Example 2 Simplify F = m,,,, using K-map B BC A F = A B + C 3 4 A 2 5 7 6 C

3 variable K-Maps (Adjacency) A 3-variable map has 2 possible groups of 2 minterms They become product terms with 2 literals

3 variable K-Maps (Adjacency) A 3-variable map has 6 possible groups of 4 minterms They become product terms with literals

4-variable K-maps A 4-variable function will consist of 6 minterms and therefore a size 6 k-map is needed Each square is adjacent to 4 other squares A square by itself will represent a minterm with 4 literals Combining 2 squares will generate a 3-literal output Combining 4 squares will generate a 2-literal output Combining 8 squares will generate a -literal output

Example F(A,B,C,D) = Sm(,,2,5,8,9,) Solution: F = B D + B C + A C D CD AB C= B= A= D=

Example (POS) F(A,B,C,D) = Sm(,,2,5,8,9,) Write F in the simplified product of sums (POS) Two methods? You already know one! CD AB C= B= A= D=

Example (POS) F(A,B,C,D) = Sm(,,2,5,8,9,) Write F in the simplified product of sums (POS) Method 2: Follow same rule as before but for the ZEROs CD AB F = AB + CD + BD Therefore, F = F = A +B C +D B +D C= B= A= D=

Don t Cares In some cases, the output of the function ( or ) is not specified for certain input combinations either because The input combination never occurs (Example BCD codes), or We don t care about the output of this particular combination Such functions are called incompletely specified functions Unspecified minterms for these functions are called don t cares While minimizing a k-map with don t care minterms, their values can be selected to be either or depending on what is needed for achieving a minimized output.

Example F = m,, + d, B BC Circle the x s that help get bigger groups of s (or s if POS). A Don t circle the x s that don t help. X 4 A 3 2 7 6 5 X C

Example F = m,, + d, B BC Circle the x s that help get bigger groups of s (or s if POS). A Don t circle the x s that don t help. X 4 A F=C 3 2 7 6 5 X C

Example 2 F A, B, C, D = m,,,, + d,, -Two possible solutions! -Both acceptable. -All s covered Src: Mano s Textbook

Definitions An implicant is a product term of a function Any group of s in a K-Map A prime implicant is a product term obtained by combining the maximum possible number of adjacent s in a k-map Biggest groups of s Not all prime implicants are needed! If a minterm is covered by exactly one prime implicant then this prime implicant is called an essential prime implicant

Finding minimum SOP Find each essential prime implicant and include it in the solution 2. If any minterms are not yet covered, find minimum number of prime implicants to cover them (minimize overlap)..

Example 2 Simplify F A, B, C, D = m,, 2, 4, 5,,,3, 5) Note: -Only A C is E.P.I -For the remaining minterms: -Choose and 2 (minimize overlap) -For m2, choose either A B D or B CD F = A C + ABD + AB C + A B D Src: Mano s Textbook

5-variable K-maps 32 minterms require 32 squares in the k-map Minterms -5 belong to the squares with variable A=, and minterms 6-32 belong to the squares with variable A= Each square in A is also adjacent to a square in A (one is above the other) Minterm 4 is adjacent to 2, and minterm 5 is to 3