SpaceWire Link Interface RTL Verification

Similar documents
The SpaceWire CODEC International SpaceWire Seminar (ISWS 2003) 4-5 November 2003, ESTEC Noordwijk, The Netherlands

Implimentation of SpaceWire Standard in SpaceWire CODEC using VHDL

SpaceWire ECSS-E50-12A International SpaceWire Seminar (ISWS 2003)

Reducing SpaceWire Time-code Jitter

SpaceWire Router Data Sheet

SpaceWire 101. Webex Seminar. February 15th, 2006

St. Petersburg State University of Aerospace Instrumentation Institute of High-Performance Computer and Network Technologies

1 CONTROL CHARACTERS AND CONTROL CODES

SpaceWire IP for Actel Radiation Tolerant FPGAs

Space engineering. SpaceWire Links, nodes, routers and networks. ECSS-E-ST-50-12C 31 July 2008

SpaceWire. Design of the SystemC model of the SpaceWire-b CODEC. Dr. Nikos Mouratidis

Page 1 SPACEWIRE SEMINAR 4/5 NOVEMBER 2003 JF COLDEFY / C HONVAULT

GAISLER. SpaceWire CODEC with RMAP GRSPW / GRSPW-FT CompanionCore Data Sheet

6 Remote memory access protocol (normative)

Research and Analysis of Flow Control Mechanism for Transport Protocols of the SpaceWire Onboard Networks

Space engineering. SpaceWire Protocols

SpaceNet - SpaceWire-T. Initial Protocol Definition

SPACEFIBRE. Session: SpaceWire Standardisation. Long Paper.

SpaceFibre Port IP Core

DRAFT Date: May ECSS-E Space Engineering. SpaceWire: SERIAL POINT-TO-POINT LINKS DRAFT

The Operation and Uses of the SpaceWire Time-Code International SpaceWire Seminar 2003

SpaceFibre Specification Draft F3

SpaceWire RMAP Protocol

SpaceWire RMAP Protocol

Dynamic Phase Alignment for Networking Applications Author: Tze Yi Yeoh

Aeroflex Colorado Springs Application Note

SoCWire: a SpaceWire inspired fault tolerant Network on Chip approach for reconfigurable System-on-Chip in Space applications

SpaceWire-RT. SpaceWire-RT Status SpaceWire-RT IP Core ASIC Feasibility SpaceWire-RT Copper Line Transceivers

Proposed Technical Solution for Half Duplex SpW

Section III. Transport and Communication

D3.2 SpaceWire-RT Updated Specification

spwr_base & spwr_chan

This amendment A1 modifies the European Telecommunication Standard ETS (1994)

Fig.12.5 Serial Data Line during Serial Communication

CCSDS Unsegmented Code Transfer Protocol (CUCTP)

SpaceWire PC Card Development. Patria New Technologies Oy ESA / ESTEC

SpaceWire Remote Memory Access Protocol

SpaceWire Router ASIC

32 Channel HDLC Core V1.2. Applications. LogiCORE Facts. Features. General Description. X.25 Frame Relay B-channel and D-channel

ADPCM-LCO Voice Compression Logic Core

Universal Asynchronous Receiver/Transmitter Core

Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting Author: Michael Francis

Single Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications

Intellectual Property Macrocell for. SpaceWire Interface. Compliant with AMBA-APB Bus

Laboratory Finite State Machines and Serial Communication

USB Compliance Checklist

ADPCM-HCO Voice Compression Logic Core

SCOC SPACEWIRE IP CORE HARDWARE USER MANUAL. Name and Function Date Signature

SpaceNet - SpaceWire-RT. Initial Protocol Definition

ECEN 468 Advanced Logic Design Department of Electrical and Computer Engineering Texas A&M University. Lab 2

UNIT - II PERIPHERAL INTERFACING WITH 8085

a16450 Features General Description Universal Asynchronous Receiver/Transmitter

Design of a High-Level Data Link Controller

STUDY, DESIGN AND SIMULATION OF FPGA BASED USB 2.0 DEVICE CONTROLLER

SPART. SPART Design. A Special Purpose Asynchronous Receiver/Transmitter. The objectives of this miniproject are to:

Serial Communication Prof. James L. Frankel Harvard University. Version of 2:30 PM 6-Oct-2015 Copyright 2015 James L. Frankel. All rights reserved.

CoE3DJ4 Digital Systems Design. Chapter 5: Serial Port Operation

Serial Communication. Simplex Half-Duplex Duplex

kcserial User Guide version 2006.FEB.20

Freescale Semiconductor, I

Upper Level Protocols (ULP) Mapping. Common Services. Signaling Protocol. Transmission Protocol (Physical Coding) Physical Interface (PI)

RESET CLK RDn WRn CS0 CS1 CS2n DIN[7:0] CTSn DSRn DCDn RXDATA Rin A[2:0] DO[7:0] TxDATA DDIS RTSn DTRn OUT1n OUT2n BAUDOUTn TXRDYn RXRDYn INTRPT

UNIVERSAL SPACEWIRE INTERFACE TO/FROM VME AND TO/FROM PCI

DYNAMIC ENGINEERING 150 DuBois St., Suite C Santa Cruz, CA (831) Fax (831) Est.

EITF35 - Introduction to the Structured VLSI Design (Fall 2016) Interfacing Keyboard with FPGA Board. (FPGA Interfacing) Teacher: Dr.

Configuration of Synchronous Protocols

CDN067 DEVICENET SPECIFICATIONS

UART Register Set. UART Master Controller. Tx FSM. Rx FSM XMIT FIFO RCVR. i_rx_clk o_intr. o_out1 o_txrdy_n. o_out2 o_rxdy_n i_cs0 i_cs1 i_ads_n

TOE10G-IP Core. Core Facts

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on PIO 8255 (Programmable Input Output Port).

PCI Express Compiler. PCI Express Compiler Version Issues

Asynchronous Transmission. Asynchronous Serial Communications & UARTS

SMCSlite and DS-Link Macrocell Development

CHAPTER 5 REGISTER DESCRIPTIONS

Time synchronization in SpaceWire networks

SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices

Computer Peripherals

CHAPTER 4 DATA COMMUNICATION MODES

FPGA for Software Engineers

UDP1G-IP Core. Core Facts

JESD204B Xilinx/IDT DAC1658D-53D interoperability Report

Hello, and welcome to this presentation of the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter Interface. It covers the main features

PICTURE Camera Interface Functional Specification

ATM-DB Firmware Specification E. Hazen Updated January 4, 2007

MCS-51 Serial Port A T 8 9 C 5 2 1

Packet Telemetry Encoder (PTME) VHDL Model

University of New Hampshire InterOperability Laboratory Ethernet in the First Mile Consortium

Using the FADC250 Module (V1C - 5/5/14)

SpaceFibre Flight Software Workshop 2015

Addressing scheme to address a specific devices on a multi device bus Enable unaddressed devices to automatically ignore all frames

Viterbi Decoder Implementation Guide. Contents. V 1.0.0, Jan. 16, Source Files Description 2

SpaceWire DC-Balanced Character Encoding for SpaceWire

A (Very Hand-Wavy) Introduction to. PCI-Express. Jonathan Heathcote

##)44 6 BIS $!4! #/-02%33)/. 02/#%$52%3 &/2 $!4! #)2#5)4 4%2-).!4).' %15)0-%.4 $#% 53).' %22/2 #/22%#4)/. 02/#%$52%3

TOE1G-IP Multisession Reference design manual Rev May-17

SpaceWire Router - Status

Universal Serial Bus Host Interface on an FPGA

Turbo Encoder Co-processor Reference Design

Quality of Service (QoS)

ECE 485/585 Microprocessor System Design

Transcription:

SpaceWire Link Interface RL Verification SpaceWire Link Interface RL Verification Ref: UoD_Link_Verif VHDL Code Issue: Document Revision: 1.0 Date: 1 Aug-2003 Document Change log Date Revision No Comments 28/11/02 draft A Initial 01/08/03 1.0 New revision number. References to other link documents updated.

SpaceWire Link Interface RL Verification I CONENS I CONENS... 2 II LIS OF FIGURES... 4 III LIS OF ABLES... 4 1. INRODUCION... 6 1.1 ERMS AND ACRONYMS... 6 1.2 DOCUMENS... 6 2. VERIFICAION SRAEGY... 8 2.1 ESBENCH ENVIRONMEN... 8 2.1.1 Command Script.... 8 2.1.2 SpaceWire Link Interface estbench... 8 2.1.3 UU... 9 2.1.4 Log File and Screen Output... 9 2.2 VERIFICAION MEHODS... 9 2.2.1 VHDL code review/analysis... 9 2.2.2 VHDL code coverage... 9 2.2.3 estbench verification... 10 2.2.4 Verification log output file... 10 2.2.5 Asynchronous Signals... 11 3. ESBENCH DIRECORY SRUCURE... 12 4. VERIFICAION MARIX... 13 4.1 ES CASES... 13 4.1.1 Configuration analysis... 13 4.1.2 Signal Level est Cases... 14 4.1.3 Character Level est Cases... 15 4.1.4 Exchange Level est Cases... 20 4.1.4.1 Flow Control est Cases... 20 4.1.4.2 Initialisation State Machine est Cases... 22 4.1.4.3 Exchange Level Error est Cases... 26 4.1.4.4 Link iming... 27 4.1.5 Network Level est Cases... 27 4.1.6 Other functions of UU-link test cases... 27 4.2 ES CASE SUMMARY... 29

SpaceWire Link Interface RL Verification 4.3 ES CASES CONFORMANCE SUMMARY... 33 4.3.1 Physical Level... 33 4.3.2 Signal Level... 33 4.3.3 Character level... 34 4.3.4 Exchange level... 35 4.3.4.1 FC usage... 35 4.3.4.2 Encoder decoder block diagram... 36 4.3.4.3 State machine... 37 4.3.4.4 Others... 39 4.3.4.5 Error Detection... 39 4.3.4.6 imecodes... 40 4.3.4.7 imings... 40 4.3.5 Packet Level... 41 4.3.6 Network Level... 41 5. VERIFICAION ESBENCH AND MODIFICAIONS... 42 5.1 ESBENCH OVERVIEW... 42 5.2 ADDIIONS AND MODIFICAIONS O HE EXISING ESBENCH... 42 5.2.1 est script hierarchy... 43 5.2.2 UoD_Ctrl... 43 5.2.3 Status Check... 44 5.2.4 Event Compare... 45 6. CODE ANALYSIS ES CASES... 46 7. NON AUO-CHECK ES CASES... 49 7.1.EXC.FC.8... 49 7.2.OFN.3... 50 8. ASYNCHRONOUS SIGNAL ANALYSIS... 52 8.1 RECEIVER... 52 8.2 RANSMIER... 52 8.3 RECEIVER CREDI... 53 9. VHDL CODE COVERAGE... 54 10. VERIFICAION PROCEDURE... 59 10.1 SIMULAOR COMMANDS... 59 10.2 COMMAND FILE... 59 10.3 CONFIGURAION IDENIY... 59 10.4 VERIFICAION OUPU... 59

SpaceWire Link Interface RL Verification 10.5 VERIFICAION COMPLEION... 60 II LIS OF FIGURES Figure 2-1 estbench Environment... 8 Figure 2-2 Verification log output file.... 11 Figure 3-1 CVS repository Directory structure... 12 Figure 7-1 Non Auto-Check test cases... 49 Figure 7-2.EXC.FC.8... 50 Figure 7-3.OFN.3 non auto-check test case... 51 III LIS OF ABLES able 1-1 Applicable Documents... 6 able 4-1 Configuration verification analysis... 14 able 4-2 Signal Level est Cases... 15 able 4-3 Character Level est Cases... 20 able 4-4 Flow Control est Cases... 22 able 4-5 State ErrorReset est Cases... 22 able 4-6 ErrorWait test cases... 23 able 4-7 State Ready test cases... 24 able 4-8 State Started test cases... 25 able 4-9 State Connecting test cases... 25 able 4-10 State Run test cases... 26 able 4-11 Exchange level error test cases... 26 able 4-12 Link timing test cases... 27 able 4-13 Network Level test cases... 27 able 4-14 Other Functions test cases... 28 able 4-15 est cases summary... 32 able 4-16 Physical level conformance... 33 able 4-17 Signal level conformance... 34

SpaceWire Link Interface RL Verification able 4-18 Character level conformance... 35 able 4-19 Exchange level conformance... 35 able 4-20 Exchange level FC conformance... 36 able 4-21 Encoder decoder block diagram conformance... 36 able 4-22 State machine conformance... 37 able 4-23 State ErrorReset conformance... 37 able 4-24 State ErrorWait conformance... 37 able 4-25 State Ready conformance... 38 able 4-26 State Started conformance... 38 able 4-27 State Connecting conformance... 39 able 4-28 State Run conformance... 39 able 4-29 Exchange level others conformance... 39 able 4-30 Exchange level error conformance... 40 able 4-31 imecodes conformance... 40 able 4-32 Link timings conformance... 41 able 4-33 Packet level conformance... 41 able 4-34 Network level conformance... 41 able 8-1 txencode synchronisation... 53 able 9-1 Coverage report file... 55

SpaceWire Link Interface RL Verification 1. INRODUCION his document presents the verification for the SpaceWire Link Interface VHDL Description as prepared by the University of Dundee. he verification includes.. Verification strategy description. A Verification matrix which cross-references the test cases to be performed with [AD1]. A description of the verification testbench and modifications. VHDL code analysis of test cases which are covered by code analysis An analysis of Asynchronous signal usage in the link interface. VHDL code coverage of all test cases performed. est case simulator run. 1.1 ERMS AND ACRONYMS UoD AAE UU-link B-link LFSR University of Dundee Austrian Aerospace Ges.m.b.H Unit Under est (University of Dundee Link Interface) estbench Link Interface Linear Feedback Shift Register 1.2 DOCUMENS In this section the documents referenced in this document are listed. ECSS-E-50-12A [AD1] European Cooperation for Space Standardization, SpaceWire Links, Nodes, Routers and Networks March 2003.. ESA VHDL Modelling Guidelines [AD2] ESA VHDL guidelines for IP and system development. SpaceWire link interface VHDL User Manual (UoD_Link_User SpaceWire link interface VHDL Functional Description (UoD_Link) [AD3] [AD4] User manual for the SpaceWire link interface under verification in this document. Functional description of the SpaceWire link interface under verification in this document able 1-1 Applicable Documents

SpaceWire Link Interface RL Verification

SpaceWire Link Interface RL Verification 2. VERIFICAION SRAEGY he verification is based on the use of a Go/No-Go VHDL testbench to exhaustively test the SpaceWire link interface. he verification environment is shown in Figure 2-1 and discussed in section 2.1. 2.1 ESBENCH ENVIRONMEN SpaceWire link Interface estbench UU Cmd Script Cmd Script Cmd Script Cmd Script Log File Screen Output Cmd Script Cmd Script Figure 2-1 estbench Environment he testbench consists of a command script file, a unit under test which is the SpaceWire link interface, a VHDL testbench, an output log file and terminal screen output. he following sections outline the function of each testbench element. 2.1.1 Command Script. he command script inputs the tests to be performed by the testbench environment in a sequential manner. It is the purpose of this document via the verification matrix to set the contents of the input command script file. Command script files can reference other command script files. his allows test runs to be repeated for different configurations. 2.1.2 SpaceWire Link Interface estbench he SpaceWire link interface testbench is based on the Austrian Aerospace SSEPPL testbench with substantial enhancements. he testbench consists of an ideal behavioural SpaceWire link interface which connects to the serial bit stream input and output from the UU. he testbench environment drives the inputs of the UU and checks the output from the UU dependant on the

SpaceWire Link Interface RL Verification commands read from the command script file. Where possible automatic checks are used to determine if the tests are successful. ests which are automatic are indicated in the verification matrix. Note: he document ASIC-N-0003-AAE describes the testbench environment in detail. 2.1.3 UU he UU is the SpaceWire link interface VHDL RL description. 2.1.4 Log File and Screen Output he log file and screen output allow the user to determine if the test run was successful. he log files are spilt into testbench working output and verification log output. he testbench working output indicates the normal running output of the testbench. his includes information about state changes or data transfers which are currently taking place. he verification log output indicates the test cases which are being run and the verification status of the current test number. he contents of this file are outlined in section 2.2.4. he screen output mirrors the contents of the verification test output. 2.2 VERIFICAION MEHODS he verification methods employed in the SpaceWire link interface verification are outlined in the following sections. 2.2.1 VHDL code review/analysis VHDL code review shall be employed in the verification of the SpaceWire link interface. Code review shall be performed internally and documented in section 6. VHDL code analysis is performed for test cases that cannot be verified by the testbench. hese test cases are marked in the verification matrix as analysis (A). 2.2.2 VHDL code coverage VHDL code coverage will be performed by the Modelsim VHDL simulator code coverage option. he code coverage output is a code coverage report which indicates the following. Percentage of VHDL code executed in VHDL architectures. Line numbers which were not covered by the test run. he expected code coverage for the verification is 100% of all VHDL statements. Exceptions include finite state machine descriptions which include the VHDL others statement.

SpaceWire Link Interface RL Verification Any VHDL statements which are not covered by the testbench are documented in section 0. 2.2.3 estbench verification Automatic testbench verification shall be employed to determine if the status of output signals matches the expected result. he status of output signals can include the status of received data and timecode transfers. Expected results are documented in the verification log output file and the verification matrix. 2.2.4 Verification log output file he verification log output file indicates the status of the verification test cases as they are run by the VHDL simulator. he log output file format is defined in Figure 2-2. Each log statement is preceded by the simulator time when the log statement is written. he verification output file name shall be defined in the VHDL configuration file associated with the testbench.

SpaceWire Link Interface RL Verification ======================================================= == IME: est Number == IME: est Description Summary == IME: Verification strategy == IME: Auto-Check [ / No] == IME: est Status [Success / Failure / NA] == IME: Further information and notes if applicable. ---------------------------------------------------- Figure 2-2 Verification log output file. Note: If the test is unsuccessful the command in the input command script file determines if the testbench is stopped. 2.2.5 Asynchronous Signals he analysis of asynchronous signals and interfaces is reported in the verification document at section 8.

SpaceWire Link Interface RL Verification 3. ESBENCH DIRECORY SRUCURE he testbench directory structure is shown in figure codec src Scripts compile msim Modelsim compilation vhdl sim Sources msim Modelsim testbench run scripts Verif tb cmdseg estbench command files cfg SpaceWire CODEC configurations Figure 3-1 CVS repository Directory structure All scripts should be run from codec/src/verify/tb o compile the VHDL files for modelsim then run the script: codec/src/scripts/compile/msim/compile_codec_allcfg.sh o run the simulation the run the do file: codec/src/scripts/sim/msim/loadsim.do

SpaceWire Link Interface RL Verification 4. VERIFICAION MARIX he verification matrix details the test cases which are performed on the SpaceWire link interface. his section includes the following: A section titled test cases which lists the test cases performed in hierachical order. his section cross references the test cases with the clause or sub-clause in the SpaceWire standard [AD1]. A verification strategy is included with each test cases and defines the verification method. A summary of the test cases to be performed. A SpaceWire link interface conformance summary table which lists all the clauses from the SpaceWire standard [AD1] which are applicable to the SpaceWire link interface (See [AD1] section 12.2.4 table 19). 4.1 ES CASES he test cases verification matrix below defines the test procedures which are performed on the UoD Link Interface. he purpose of the test cases is to verify the function of the SpaceWire link interface. he following points describe the columns in the verification matrix table: est number which is the reference used when referring to the test. Cross reference number with the SpaceWire standard [AD1]. he cross reference number indicates the section number in the SpaceWire standard [AD1] Description of the referenced clause in the SpaceWire standard [AD1]. Description of the verification method used to test the requirement. /A, est is performed by the testbench, A est is performed by analysis. Is the test performed automatically by the verification testbench. 4.1.1 Configuration analysis he UoD SpaceWire link interface can be configured to suit the users application. he configuration options and the verification method used is outlined below. he testbench has the ability to load test script files Configuration option Affects Verification CFG_PIPELINE CFG_DDROU op level global configuration op level transmit encoding method All testcases are run with CFG_PIPELINE= 0 and CFG_PIPELINE= 1 All testcases are run with CFG_DDROU= 0 and CFG_DDROU = 1.

SpaceWire Link Interface RL Verification = 1. CFG_BICLK ransmit bit clock configuration. All test cases are run for each CFG_BICLK configuration CFG_SYNCRDCLK Receive buffer clock CFG_SYNCRDCLK is used in XCLK_DEFAUL configuration CFG_DISCARD_EMPY_PK CFG_MAXCREDI CFG_RXUSELACHES Empty packet handling by receiver Maximum outstanding N-chars Receiver n-char resynchronisation storage est case.exc.err.5 covers CFG_DISCARD_EMPY_PK. Covered in test cases.exc.fc.cred.(1-4) est cases are performed for CFG_RXUSELACHES = 0 and CFG_RXUSELACHES = 1. able 4-1 Configuration verification analysis 4.1.2 Signal Level est Cases Signal level test cases correspond to section 6 of the SpaceWire standard [AD1]. est No. Reference No..SIG.1 6.3.1.a Data Strobe Encoding Interface Shall be Used Reference Description Verification Strategy /A Auto.SIG.2 6.3.1.b Data shall be logic 1 when the data bit stream is high. Data shall be logic 0 when the data bit stream is low..sig.3 6.3.1.b Strobe shall change when Data does not change.sig.4 6.3.2.a he SpaceWire receiver shall be tolerant to simultaneous transitions on Data and Strobe..SIG.5 6.3.2.b No simultaneous transitions shall occur on Data or Strobe when a reset is performed..sig.6 6.6.1 he minimum data signalling rate before receiver disconnection detection shall be 2 Mbit/s Link operation Link operation Link operation Set WireInD and WireInS to 0 when both 1 Perform a reset of the UUlink core for each DOU/SOU state, e.g. (0,0), (0,1) etc. Check for simultaneous transitions Set input bit stream data rate to 2 Mbit/s. and check no disconnect occurs

SpaceWire Link Interface RL Verification detection shall be 2 Mbit/s.SIG.7 6.6.3 he SpaceWire link shall operate at any data signalling rate from the maximum to the minimum. Vary the data signalling rate from the minimum to the maximum while data transfer is performed..sig.8 6.6.5 he SpaceWire link transmitter shall initially operate at 10Mbit/s +/- 10% after a reset is performed Start-up the UU-link after reset and check the data signalling rate..sig.9 6.6.5 he SpaceWire link transmitter shall initially operate at 10Mbit/s +/- 10% after a disconnection is performed Perform a disconnection of the UU-link and check the data signalling rate..sig.10 6.6.6 he SpaceWire link transmitter data signalling rate shall not be changed until the state machine moves to state Run Start-up the UU-link after reset and check the data signalling rate once the run state has been entered. able 4-2 Signal Level est Cases 4.1.3 Character Level est Cases Character level test cases correspond to the SpaceWire character level defined in the SpaceWire standard [AD1] section 7. est No. Reference No. Reference Description Verification Strategy /A Auto.CHA.1.a 7.2 he data character sequence shall contain a parity-bit, a data-control flag set to zero and eight bits of data. UU-link transmits a series of data characters after reset. he B-link receives data characters without parity error..cha.1.b 7.2 B-link sends a series of data characters after reset. he UUlink receives data characters without parity error

SpaceWire Link Interface RL Verification.CHA.2.a 7.2 he data character data bits shall be transmitted LSB to MSB. UU-link send data characters with the LSB set to one after reset. B-link receives data character with correct bit alignment..cha.2.b 7.2 B-link sends data characters with the LSB set to one. UUlink receives data characters with correct bit alignment..cha.3.a 7.3.a he control character sequence shall contain a parity-bit, a data-control flag set to one and a two bit control code. UU-link sends control characters on start-up and normal operation. B-link starts up and receives control characters..cha.3.b 7.3.a B-link sends control characters on start-up and normal operation. UU-link starts up and receives control characters..cha.4.a 7.3.a he flow control token two bit identifier shall be 00 UU-link transmits FC characters at start-up as part of NULL character and as flow control. B-link receives NULLs and FCs and starts up..cha.4.b 7.3.a.CHA.5.a 7.3.a he EOP control token two bit identifier shall be 01 B-link transmits FC at start-up as part of NULL character and flow control. UU-link receives FC and NULL and starts up UU-link send data characters ending with an EOP character. Blink receives data characters followed by EOP.

SpaceWire Link Interface RL Verification.CHA.5.a 7.3.a B-link send data characters ending with an EOP character. UU-link receives data characters followed by EOP..CHA.6.a 7.3.a he EEP control token two bit identifier shall be 10 UU-link send data characters ending with an EEP character. Blink receives data characters followed by EEP..CHA.6.b 7.3.a B-link send data characters ending with an EEP character. UU-link receives data characters followed by EEP.CHA.7.a 7.3.a he ESC control token two bit identifier shall be 11 UU-link transmits NULL characters at start-up which contain the ESC pattern. Blink detects NULL characters and perform link start-up..cha.7.b 7.3.a B-link transmits NULL characters at start-up. UU-link detects NULL characters and performs link start-up..cha.8.a 7.3.b he NULL character shall be formed by an ESC character followed by an FC character. he parity-bit in the middle of a NULL character shall be zero. UU-link transmits NULL characters at start-up. B-link receives NULL pattern and performs start-up without parity error..cha.8.b 7.3.b B-link transmits NULL characters at start-up. UU-link receives NULL pattern and performs start-up without parity error..cha.8.c 7.3.b B-link transmits NULL with incorrect parity bit. Parity Error is detected at UU-link

SpaceWire Link Interface RL Verification.CHA.9.a 7.3.c he timecode character shall be formed by an ESC character followed by data character. he timecode character middle parity bit UU-link transmits series of timecodes. B-link receives timecode characters without parity error..cha.9.b 7.3.c shall be one. B-link transmits series of timecodes. UU-link receives timecode characters without parity error..cha.9.c 7.3.c B-link transmits timecodes with incorrect parity bit. UU-link detects parity error..cha.10.a 7.3.f An ESC character followed by EOP, EEP or ESC shall be noted as an escape error. B-link transmits ESC followed by EOP. UU-link detects escape error and disconnects.cha.10.b 7.3.f B-link transmits ESC followed by EEP. UUlink detects escape error and disconnects.cha.10.c 7.3.f B-link transmits ESC followed by ESC. UU-link detects escape error and disconnects.cha.11.a 7.4 he parity bit shall be set to produce odd parity. UU-link transmits data and control characters. B-link does not report parity error..cha.11.b 7.4 B-link transmits data and control characters with correct parity bit. UU-link does not report parity error..cha.11.c 7.4 B-link transmits characters with incorrect parity bit set. UU-link reports parity error and disconnects.

SpaceWire Link Interface RL Verification.CHA.12.a 7.5 After reset the strobe signal shall transition before the data signal for the first NULL character. B-link starts up initially after reset with NULL pattern. UUlink detects first NULL pattern and starts up. successfully..cha.12.b 7.5 B-link starts up initially after reset with incorrect first NULL pattern. UU-link does not start-up..cha.12.c 7.5 UU-link starts up initially after reset and transmits correct NULL pattern. B-link starts up link connection.cha.13.a 7.6 he transmitter and receiver UU-link transmits data, EOP and EEP characters from host using control flag protocol. B-link receives data, EOP and EEP characters..cha.13.b 7.6 host data interfaces comprise a control flag and eight data bits. When control bit is low then the eight data bits are a data character. When control bit is high then the LSB denotes an EOP or EEP character..cha.14 7.7.a he time interface shall comprise two signals ICK_IN and ICK_OU, a six bit time output and a six bit time input, a two bit control flag input and a two bit control flag output..cha.15 7.7.b When ICK_IN is asserted in the Run state a the transmitter shall send a timecode character..cha.16.a 7.7.c. ICK_OU shall be asserted when the interface is in the Run state and a timecode is received B-link transmits data, EOP and EEP. UUlink receives data, EOP and EEP using correct protocol Code-Analysis A - UU-link transmits timecode. B-link receives timecode B-link initiates startup and transmits timecode. UU-link receives timecode in Run state

SpaceWire Link Interface RL Verification.CHA.16.b 7.7.c B-link transmits timecode before initiating start-up. UU-link ICK_OU is not asserted. able 4-3 Character Level est Cases 4.1.4 Exchange Level est Cases Exchange level test cases correspond to the SpaceWire exchange level in [AD1] section 8. est No. Reference No..EXC.1 8.2.1 N-Chars are the only characters which are passed to the packet level Reference Description Verification Strategy /A Auto.EXC.2 8.2.2.a Only N-Chars shall be passed from the host to the interface to the link for transmission..exc.3 8.2.2.b A received character shall not be acted upon until its parity bit has been checked. Code-analysis A - Code-analysis A - B-link sends data character to UU-link with incorrect parity bit. UU-link does not write character to receiver buffer. 4.1.4.1 Flow Control est Cases he flow control test cases correspond to the use of FCs to control the flow of data over the SpaceWire link. est No. Reference No. Reference Description.EXC.FC.1 8.3.c For each FC sent space shall be reserved for eight data characters in the receiver buffer..exc.fc.2 8.3.d For each FC received the transmitter shall increment the credit counter by eight. he transmitter shall not Verification Strategy /A Auto Code-Analysis, check increment. No data characters transmitted before first FC is received A -

SpaceWire Link Interface RL Verification transmit any data characters before the first FC is received..exc.fc.3 8.3.e In state ErrorReset the transmitter credit count shall be set to zero.exc.fc.4 8.3.f If a received FC causes the transmitter credit count to exceed 56 then transmitter credit error shall be reported..exc.fc.5 8.3.i Receiver Credit Counter shall keep a count of the N-Chars it expects to receive. he count shall be incremented by eight when an FC is transmitted and decremented by one when an N-Char is received..exc.fc.6 8.3.j At reset or disconnect the outstanding counter shall be set to zero..exc.fc.7 8.3.l An FC shall be transmitted when there is room in the outstanding credit count and in the buffer space count..exc.fc.8 8.3.n he order of priority for transmission shall be..exc.fc.cred.1 [AD3] section 6.10 1) imecode 2) FC 3) N-Char 4) Null CFG_MAXCREDI minimum value shall be eight outstanding N-Chars. Only one FC shall be outstanding. After B-link link disconnect check transmitter HAS_CREDI is low. B-link transmit FCs. UU-link reports credit error. Code analysis.. A - Code analysis. A - B-link receives UU-link FCs on start-up. Code check. A - Check number of FCs transmitted at start-up is one

SpaceWire Link Interface RL Verification.EXC.FC.CRED.2 [AD3] section 6.10 CFG_MAXCREDI shall be any value from.8 to 56 Set CFG_MAXCREDI value and Check number of FCs transmitted at start-up is = CFG_MAXCREDI/8.EXC.FC.CRED.3 [AD3] section 6.10 When CFG_MAXCREDI is larger than buffer size then only buffer size credit shall be requested Set CFG_MAXCREDI = 56, rxbufaddrlen = 5. Only 4 FCs transmitted by link..exc.fc.cred.4 [AD3] section 6.10 CFG_MAXCREDI is at maximum 56 Check 7 FCs transmitted at startup. Set buffer size to 1K and transmit 1K data. Check receive success able 4-4 Flow Control est Cases 4.1.4.2 Initialisation State Machine est Cases he state machine test cases correspond to the initialisation state machine in section 8 of [AD1]. 4.1.4.2.1 In state ErrorReset est No. Reference No..EXC.ERS.1 8.5.2.2.a ErrorReset shall be entered on system reset or link operation error..exc.ers.2 8.5.2.2.b In ErrorReset the transmitter and receiver shall be disabled.exc.ers.3 8.5.2.2.c After reset is de-asserted then the interface state machine shall move to state ErrorWait after 6.4 us (5.82us to 7.22us nominal) Reference Description Verification Strategy /A Auto able 4-5 State ErrorReset est Cases System reset is performed. UU-link state is ErrorReset UU-link does not detect NULLs from B-link. B-link GotNULL is not asserted After 6.4us delay from reset check UU-link state.

SpaceWire Link Interface RL Verification 4.1.4.2.2 In state ErrorWait est No. Reference No. Reference Description.EXC.ERW.1 8.5.2.3.a ErrorWait shall only be entered from state ErrorWait.EXC.ERW.2 8.5.2.3.b he receiver shall be enabled and the transmitter shall be disabled.exc.erw.3 8.5.2.3.c If a NULL is received then the GotNULL condition shall be set.exc.erw.4 8.5.2.3.d he ErrorWait state shall be left after 12.8 us to state Ready. (11.64us to 14.33us nominal) Verification Strategy /A Code analysis. A - Code analysis. A - B-link sends NULLs. GotNULL is asserted After 6.4us + 12.8us from reset check UU-link state.exc.erw.5.a 8.5.2.3.e On disconnect error, parity B-link cause error, escape error or any character other than NULL is received then move to disconnect error. Check UU-link state is ErrorReset..EXC.ERW.5.b 8.5.2.3.e state ErrorReset B-link parity error..exc.erw.5.c 8.5.2.3.e B-link escape error..exc.erw.5.d 8.5.2.3.e B-link send FC.EXC.ERW.5.e 8.5.2.3.e B-link send N- Char.EXC.ERW.5.f 8.5.2.3.e able 4-6 ErrorWait test cases B-link send imecode Auto 4.1.4.2.3 In state Ready est No. Reference No..EXC.RDY.1 8.5.2.4.a State Ready shall be entered only from state ErrorWait.EXC.RDY.2 8.5.2.4.b he receiver is enabled and the transmitter is disabled..exc.rdy.3 8.5.2.4.c If a NULL is received then the GotNULL Reference Description Verification Strategy /A Auto Code analysis. A - Code analysis. A - B-link sends NULLs. GotNULL is asserted

SpaceWire Link Interface RL Verification condition shall be set GotNULL is asserted.exc.rdy.4.a 8.5.2.4.d he state machine shall Assert UU-link move to state Started when [LinkEnabled] is LINK_SAR and check UU-link state is Started..EXC.RDY.4.b 8.5.2.4.d asserted. Assert UU-link AUOSAR and B-link send NULL. Check UUlink state is Started.EXC.RDY.4.c 8.5.2.4.d Asserted UU-link LINK_DISABLE. Check UU-link does not enter Started on LINK_SAR or autostart.exc.rdy.5.a 8.5.2.4.e On disconnect error, B-link cause disconnect parity error, escape error or any character error and check UU-link state is ErrorReset.EXC.RDY.5.b 8.5.2.4.e other than NULL is received then move to B-link parity error..exc.rdy.5.c 8.5.2.4.e state ErrorReset B-link escape error..exc.rdy.5.d 8.5.2.4.e B-link send FC.EXC.RDY.5.e 8.5.2.4.e B-link send N-Char.EXC.RDY.5.f 8.5.2.4.e able 4-7 State Ready test cases B-link send imecode 4.1.4.2.4 In state Started est No. Reference No..EXC.SA.1 8.5.2.5.c In state Started the transmitter shall send NULLs.EXC.SA.2 8.5.2.5.d If a NULL is received then GotNULL shall be asserted.exc.sa.3 8.5.2.5.e If GotNULL is asserted then the state machine shall move to state Connecting..EXC.SA.4 8.5.2.5.f At least one NULL shall be requested for transmission before moving to Connecting. Reference Description Verification Strategy /A Auto B-link receives NULLs B-link sends NULLs. GotNULL is asserted UU-link receive NULL and check UUlink state is Connecting. UU-link move from ErrorWait -> Ready -> Started. B-link detects NULL then FCs

SpaceWire Link Interface RL Verification.EXC.SA.5 8.5.2.5.g On disconnect error, parity error, escape error or any character other than NULL is received then move to state ErrorReset B-link cause disconnect error and check UU-link state is ErrorReset.EXC.SA.6 8.5.2.5.h On 12.8us timeout state machine shall move to ErrorReset B-link does not send NULLs for 12.8 us. Check UU-link state is ErrorReset able 4-8 State Started test cases Note.48. Only disconnect error can be detected in state Started. Parity error and escape error cannot be detected until the first NULL is received. On reception of the first NULL the state machine moves from state Started to Connecting. 4.1.4.2.5 In state Connecting est No. Reference No. Reference Description.EXC.CON.1 8.5.2.6.c In state Connecting the transmitter shall send NULLs and FCs.EXC.CON.2 8.5.2.6.d If an FC is received then the state machine shall move to state Run Verification Strategy B-link receives NULLs and FCs B-link sends FC. UU-link check for state Run.EXC.CON.3.a 8.5.2.6.e If disconnect, parity or B-link causes link escape error is detected or any other character other than NULL or FC is disconnect error. Check UU-link state is ErrorReset.EXC.CON.3.b 8.5.2.6.e detected then move to state ErrorReset B-link parity error.exc.con.3.c 8.5.2.6.e B-link credit error.exc.con.3.d 8.5.2.6.e B-link send incorrect character.exc.con.3.e 8.5.2.6.e.EXC.CON.4 8.5.2.6.f On 12.8us timeout state machine shall move to ErrorReset able 4-9 State Connecting test cases B-link send incorrect character B-link does not send FCs for 12.8 us. Check UU-link state is ErrorReset /A Auto

SpaceWire Link Interface RL Verification 4.1.4.2.6 In state Run est No. Reference No. Reference Description Verification Strategy /A Auto.EXC.RUN.1.a 8.5.2.7.b If the link is disabled or if B-link causes a disconnect error or parity error or escape or credit error is detected disconnect error. Check UU-link state is ErrorReset.EXC.RUN.1.b 8.5.2.7.b then move to state ErrorReset B-link parity error.exc.run.1.c 8.5.2.7.b B-link escape error.exc.run.1.d 8.5.2.7.b B-link credit error.exc.run.1.e 8.5.2.7.b able 4-10 State Run test cases UU-link LINK_DISABLE. check UU-link state is ErrorReset 4.1.4.3 Exchange Level Error est Cases est No. Reference No. Reference Description Verification Strategy /A Auto.EXC.ERR.1 8.9.2.1.f If a disconnect Error is detected in the Run state then the error shall be reported to the network level. B-link Disconnect error in run state.exc.err.2 8.9.2.2.c If a parity error is detected in the Run state then the error shall be reported to the network level. B-link Parity error in run state.exc.err.3 8.9.2.3.c If an escape error is detected in the Run state then the error shall be reported to the network level. B-link Escape error in run state.exc.err.4 8.9.2.4.c If credit error is detected in the Run state then the error shall be reported to the network level. B-link Escape credit error in run state.exc.err.5 8.9.3.2 If the next N-Char received after an EOP, EEP is an EOP, EEP then the link interface may discard the second EOP, EEP B-link sends empty packet. UU-link discards second EOP, EEP able 4-11 Exchange level error test cases

SpaceWire Link Interface RL Verification 4.1.4.4 Link iming est No. Reference No. Reference Description.EXC.IME.1 8.11.2 he disconnect timeout period of 850ns nominal shall be from 727ns to 1000ns. Verification Strategy /A Auto B-link causes disconnect error. UU-link disconnect error is not reported between 727ns and 1000ns period. able 4-12 Link timing test cases 4.1.5 Network Level est Cases est No. Reference No. Reference Description Verification Strategy /A Auto.NE.REC.1 10.6.2 On error if the last character written to the receiver buffer was not an EOP, EEP then add an EEP to the receiver buffer. B-link causes link error. UU-link last packet is terminated with EEP..NE.REC.2 10.6.2 On error delete the tail of the transmitter buffer so the next character to transmit is the head of the next packet. B-link causes link error. UU-link spills head of transmitter packet able 4-13 Network Level test cases 4.1.6 Other functions of UU-link test cases his section outlines functions which are not covered in [AD1]. est No..OFN.1.OFN.2 Description Verification Strategy /A Auto he transmitter ICK_IN signal can be asserted for more than one cycle of CLK but remains synchronous to CLK. Only one timecode shall be transmitted he input signal FLUSH_X causes the transmitter to flush packets which are present in the transmitter buffer. UU-link ICK_IN asserted for more than one clock cycle. B-Link receives one imecode. UU-link FLUSH_X is asserted. Packets are written to FIFO. B-link GotNchar is not asserted.ofn.3 Reset Function. Check outputs are as defined in [AD3] No

SpaceWire Link Interface RL Verification.OFN.4 External 10MHz clock function as defined in [AD3] section 6.11 code analysis A - able 4-14 Other Functions test cases

SpaceWire Link Interface RL Verification 4.2 ES CASE SUMMARY he test cases summary table below lists the tests cases numbers, the cross reference number with [AD1] and a brief description of the test to be performed. est No Reference No est Description.SIG.1 6.3.1.a Data-Strobe encoding.sig.2 6.3.1.b Data shall follow the bit-stream.sig.3 6.3.1.b Strobe shall change when data does not change.sig.4 6.3.2.a Receiver olerant to simultaneous transitions on DIN and SIN.SIG.5 6.3.2.b No simultaneous transitions on DOU and SOU.SIG.6 6.6.1 Minimum data signalling rate is supported.sig.7 6.6.3 Variable data signalling rate..sig.8 6.6.5 Default transmitter data signalling rate after reset..sig.9 6.6.5 Default transmitter data signalling rate after disconnection..sig.10 6.6.6 Default data signalling rate until Run state..cha.1.a 7.2 ransmit with correct data character bit sequence.cha.1.b 7.2 Receive correct data character bit sequence.cha.2.a 7.2 ransmit data LSB to MSB.CHA.2.b 7.2 Receive data LSB to MSB.CHA.3.a 7.3.a ransmit with correct control character bit sequence.cha.3.b 7.3.a Receive with correct control character bit sequence.cha.4.a 7.3.a ransmit FC character.cha.4.b 7.3.a Receive FC character.cha.5.a 7.3.a ransmit EOP character.cha.5.b 7.3.a Receive EOP character.cha.6.a 7.3.a ransmit EEP character.cha.6.b 7.3.a Receive EEP character.cha.7.a 7.3.a ransmit ESC character.cha.7.b 7.3.a Receive ESC character.cha.8.a 7.3.b ransmit NULL character with correct parity bit.cha.8.b 7.3.b Receive NULL character with correct parity bit.cha.8.c 7.3.c Receive NULL character with incorrect parity bit (cause error).cha.9.a 7.3.c ransmit imecode character with correct parity bit.cha.9.b 7.3.c Receive imecode character with correct parity bit.cha.9.c 7.3.c Receive imecode character with incorrect parity bit (cause error)

SpaceWire Link Interface RL Verification.CHA.10.a 7.3.f ESC followed by EOP character error detection..cha.10.b 7.3.f ESC followed by EEP character error detection..cha.10.b 7.3.f ESC followed by ESC character error detection..cha.11.a 7.4 UU-link transmits with correct odd parity..cha.11.b 7.4 UU-link receives characters with odd parity correctly..cha.11.c 7.4 UU-link detects parity error which receiving characters with incorrect parity..cha.12.a 7.5 UU-link detects first NULL correctly when strobe transitions before data..cha.12.b 7.5 UU-link does not detect first NULL when initial NULL pattern is incorrect..cha.12.c 7.5 UU-link starts-up after reset and transmits correct bit pattern for first NULL.CHA.13.a 7.6 UU-link transmits data, EOP and EEP characters using host data interface specification correctly..cha.13.b 7.6 UU-link receives data, EOP and EEP characters using host data interface specification correctly..cha.14 7.7.a imecode interface signals..cha.15 7.7.b ICK_IN assertion in run state shall cause a timecode to be transmitted..cha.16.a 7.7.c UU-link receives a timecode in Run state successfully..cha.16.b 7.7.c UU-link receives a timecode when not in Run state. ICK_OU is not asserted..exc.1 8.2.1 Only N-Chars to packet level.exc.2 8.2.2.a Only N-Chars accepted by transmitter.exc.3 8.2.2.b Receiver parity error character checking.exc.fc.1 8.3.c For each FC sent space shall be reserved for eight N- Chars.EXC.FC.2 8.3.d For each FC received transmitter credit counter incremented by eight..exc.fc.3 8.3.e In state ErrorReset transmitter credit count shall be zero.exc.fc.4 8.3.f ransmitter credit error.exc.fc.5 8.3.i Receiver expected N-Chars credit counter.exc.fc.6 8.3.j At reset or disconnect excepted N-Chars credit counter shall be zero.exc.fc.7 8.3.l An FC shall be transmitted when there is room in expected and buffer space receiver credit counts.exc.fc.8 8.3.n Character transmission priority.exc.fc.cred.1 [AD3] section 6.10 Maximum outstanding credit at minimum value..exc.fc.cred.2 8.3.n Maximum outstanding credit at middle value..exc.fc.cred.3 8.3.n Maximum outstanding credit larger than buffer size.

SpaceWire Link Interface RL Verification.EXC.FC.CRED.4 8.3.n Maximum outstanding credit at maximum value with large buffer size..exc.ers.1 8.5.2.2.a ErrorReset state entered after system reset.exc.ers.2 8.5.2.2.b In state ErrorReset the receiver and transmitter are disabled.exc.ers.3 8.5.2.2.c After 6.4us ErrorReset -> ErrorWait.EXC.ERW.1 8.5.2.3.a ErrorWait shall only be entered from state ErrorReset..EXC.ERW.2 8.5.2.3.b Received enabled and receive NULLs. ransmitter disabled.exc.erw.3 8.5.2.3.c In state ErrorWait if a NULL is received then GotNULL shall be set.exc.erw.4 8.5.2.3.d After 12.8us ErrorWait -> Ready.EXC.ERW.5.a 8.5.2.3.e In state ErrorWait on disconnect error move to state ErrorReset.EXC.ERW.5.b 8.5.2.3.e In state ErrorWait on escape error move to state ErrorReset.EXC.ERW.5.c 8.5.2.3.e In state ErrorWait on parity error move to state ErrorReset.EXC.ERW.5.d 8.5.2.3.e In state ErrorWait on FC received move to state ErrorReset.EXC.ERW.5.e 8.5.2.3.e In state ErrorWait on N-Char received move to state ErrorReset.EXC.ERW.5.f 8.5.2.3.e In state ErrorWait on imecode received move to state ErrorReset.EXC.RDY.1 8.5.2.4.a Ready shall only be entered from state ErrorWait..EXC.RDY.2 8.5.2.4.b In state ready receive NULLs UU-link GotNULL is asserted. ransmitter is disabled, B-link GO_NULL is not asserted..exc.rdy.3 8.5.2.4.c In state Ready if a NULL is received then GotNULL shall be set..exc.rdy.4.a 8.5.2.4.d State Ready -> Started when LINK_SAR and not LINK_DISABLED.EXC.RDY.4.b 8.5.2.4.d State Ready -> Started when GotNULL and AUO_SAR and not LINK_DISABLED.EXC.RDY.4.c 8.5.2.4.d Remain in Ready state when LINK_DISABLED..EXC.RDY.5.a 8.5.2.4.e State Ready -> ErrorReset on disconnect error.exc.rdy.5.b 8.5.2.4.e State Ready -> ErrorReset on parity error.exc.rdy.5.c 8.5.2.4.e State Ready -> ErrorReset on escape error.exc.rdy.5.d 8.5.2.4.e State Ready -> ErrorReset on FC received.exc.rdy.5.e 8.5.2.4.e State Ready -> ErrorReset on N-Char received.exc.rdy.5.f 8.5.2.4.e State Ready -> ErrorReset on imecode received.exc.sa.1 8.5.2.5.c In state Started the transmitter shall send NULLs.EXC.SA.2 8.5.2.5.d In state Started if a NULL is received then GotNULL is asserted.

SpaceWire Link Interface RL Verification.EXC.SA.3 8.5.2.5.e In state Started then the state machine shall move to state Connecting..EXC.SA.4 8.5.2.5.f At least one NULL shall be requested for transmission before moving to state connecting.exc.sa.5 8.5.2.5.g State Started -> ErrorReset on disconnect error.exc.sa.6 8.5.2.5.h State Started -> ErrorReset on 12.8us timeout.exc.con.1 8.5.2.6.c In state Connecting the transmitter shall send NULLs and FCs.EXC.CON.2 8.5.2.6.d In state Connecting if an FC is received then move to state Run.EXC.CON.3.a 8.5.2.6.e State Connecting -> ErrorReset on disconnect error.exc.con.3.b 8.5.2.6.e State Connecting -> ErrorReset on parity error.exc.con.3.c 8.5.2.6.e State Connecting -> ErrorReset on escape error.exc.con.3.d 8.5.2.6.e State Connecting -> ErrorReset on N-Char received.exc.con.3.e 8.5.2.6.e State Connecting -> ErrorReset on imecode received.exc.con.4 8.5.2.6.f State Connecting -> ErrorReset on 12.8us timeout.exc.run.1.a 8.5.2.7.b State Run -> ErrorReset on disconnect error.exc.run.1.b 8.5.2.7.b State Run -> ErrorReset on parity error.exc.run.1.c 8.5.2.7.b State Run -> ErrorReset on escape error.exc.run.1.d 8.5.2.7.b State Run -> ErrorReset on credit error.exc.run.1.e 8.5.2.7.b State Run -> ErrorReset on LINK_DISABLE..EXC.ERR.1 8.9.3.2 Empty packet error handling..ne.rec.1 10.6.2 Receiver buffer error recovery procedure.ne.rec.2 10.6.2 ransmitter buffer error recovery procedure.ofn.1 n/a ICK_IN number of cycle timings.ofn.2 n/a ransmitter buffer FLUSH_X usage.ofn.3 n/a Outputs on reset function..ofn.4 n/a External 10MHz clock enable function. able 4-15 est cases summary

SpaceWire Link Interface RL Verification 4.3 ES CASES CONFORMANCE SUMMARY Section 12.2.4 of the SpaceWire standard [AD1] lists the relevant clauses and sub-clauses which are required for the SpaceWire link interface. he following table defines each relevant clause and sub clause. ests cases which are associated with the clause are defined in the table. Note: Clauses and subclasses which are not relevant or are covered in other test cases are printed in italics. Note: est Numbers which have prefixes a,b,c etc. are shortened for clarity 4.3.1 Physical Level Ref No est No Reference Summary Notes 5.3 - SpaceWire Connectors n/a 5.5 - PCB racks usage n/a able 4-16 Physical level conformance 4.3.2 Signal Level Ref No est No Reference Summary Notes 6.1 - Low Voltage Differential signalling shall be used n/a 6.2 - Failsafe operation of LVDS n/a 6.3.1.a.SIG.1 Data Strobe Encoding shall be used. 6.3.1.b.SIG.2,.SIG.3 Data value shall follow bit stream value. Strobe shall change when Data Changes 6.3.2.a.SIG.4 Receiver shall be tolerant to simultaneous transitions on DIN and SIN 6.3.2.b.SIG.5 No simultaneous transitions shall occur on DOU and SOU. 6.4 - LVDS shall be used for data and strobe signals n/a 6.5 - A SpaceWire link shall comprise of two pairs of differential signals in both directions 6.6.1.SIG.6 Minimum data signalling rate. 6.6.2 - Maximum data signalling rate is dependant on signal skew and jitter 6.6.3.SIG.7 SpaceWire link shall operate at any data signalling rate from the maximum to the minimum. he link in one direction can operate at a different data signalling rate than the link in the other direction 6.6.4 - Effects of skew and jitter n/a n/a n/a

SpaceWire Link Interface RL Verification 6.6.5.SIG.8 Initial data signalling rate after reset 6.6.5.SIG.9 Initial data signalling rate after link disconnection 6.6.6.SIG.10 he transmitter data signalling rate shall not be changed until the state machine moves to the Run state able 4-17 Signal level conformance 4.3.3 Character level Ref No est No Reference Summary Notes 7.1 - General Description of character level n/a 7.2.CHA.1,.CHA.2 7.3.a.CHA.3,.CHA.4,.CHA.5,.CHA.6,.CHA.7 Data character bit definition. Data bits shall be transmitted LSB to MSB Control character bit sequence definition. Control character code fields :- FC -> 00 EOP -> 01 EEP -> 10 ESC -> 11 7.3.b.CHA.8 NULL character bit sequence definition. NULL character middle parity bit usage 7.3.c.CHA.9 imecode character bit sequence definition, imecode character middle parity bit usage. 7.3.d - imecode character shall be least significant six bytes of a timecode character transmitted. he two most significant bits shall be the timecode control-flag 7.3.e.CHA.10 An Escape character followed by escape, EOP or EEP shall be noted as an escape error 7.4.CHA.11 he parity bit shall be set to produce odd parity 7.5.CHA.12 Data-Strobe shall be set to zero after reset. Data-Strobe bit pattern after transmitter enabled. 7.6.CHA.13 N-char host interface control bit usage. 7.7.a.CHA.14 he timecode interface shall comprise two signals ICK_IN and ICK_OU, six bit timecode input and output signals and two bit timecode control-flag input and output. est cases cover all control character transmission and reception UU-link accepts timecodes as eight bit characters on the input signal IME_IN. External host controls timecode control bit fields. imecode transmission is covered in.cha.9 imecodes are accepted as an eight bit character. Bits 5-0 are timecode and bits

SpaceWire Link Interface RL Verification bit timecode control-flag input and output. 7.7.b.CHA.15 ICK_IN asserted shall cause a timecode to be transmitted in the Run state. 7.7.c.CHA.16 ICK_OU shall be asserted when a timecode is received and the transmitter is in the Run state. 7.7.d - Only one node in a system shall have an active ICK_IN signal. 7.7.e - All other nodes shall keep ICK_IN deasserted. 7.7.f - A six bit time counter shall be provided from the link receiver to the local time counter. 7.7.g - A six bit time input shall be provided to the transmitted from the local time counter 7-6 are the controlflag he time master ICK_IN controller is a system level issue As above. Covered in.cha.14 Covered in.cha.14 able 4-18 Character level conformance 4.3.4 Exchange level Ref No est No Reference Summary Notes 8.1 - General Description of exchange level n/a 8.2.1.EXC.1 N-Chars are the only characters which are passed to the packet level 8.2.2.a.EXC.2 Only N-Chars shall be passed from the host interface to the link. 8.2.2.b.EXC.3 Received characters shall not be acted upon until the parity bit is checked. able 4-19 Exchange level conformance 4.3.4.1 FC usage Ref No est No Reference Summary Notes 8.3.a - Flow control tokens shall be transferred over the link to control data transfers. 8.3.b - FC sent to indicate there is room for eight more data N-Chars 8.3.c.EXC.FC.1 For each FC sent space shall be reserved for eight more N-Chars 8.3.d.EXC.FC.2 ransmitter credit counter increment by eight for each FC received Overview of FC usage Covered in 8.3.c

SpaceWire Link Interface RL Verification 8.3.e.EXC.FC.3 In state ErrorReset the transmitter credit count shall be set to zero. 8.3.f.EXC.FC.4 ransmitter credit error when credit counter is greater than 56 8.3.g - Maximum amount of credit is 56 Covered in 8.3.f 8.3.h - On reset the number of FCs to send shall be set to the size of the receiver credit counter 8.3.i.EXC.FC.5 Receiver expected characters credit counter shall be incremented by eight when a FC is transmitted and decremented by one when an N- Char is written to the buffer 8.3.j.EXC.FC.6 At reset the expected characters count shall be set to zero. 8.3.k - Expected characters credit counter shall hold a maximum of 56 characters. 8.3.l.EXC.FC.7 An FC shall be transmitted when there is room in the outstanding credit counter and in the buffer space count. 8.3.m.EXC.FC.8 FCs transmitted when no imecodes. N-Chars transmitted when no FCs or imecodes. NULLs transmitted when no FCs, imecodes or N- Chars. 8.3.n.EXC.FC.8 ransmission priority able 4-20 Exchange level FC conformance Covered in.exc.fc.2 Covered in.exc.fc.4 4.3.4.2 Encoder decoder block diagram Ref No est No Reference Summary Notes 8.4.1 - Encoder decoder block diagram general informative 8.4.2 - ransmitter functions and host interface Informative 8.4.3 - ransmitter clock description Covered in 6.6 8.4.4 - Receiver functions and states. Informative 8.4.5 - Receiver clock recovery functions Informative 8.4.6 - State Machine functions Informative 8.4.7 - imer functions Informative 8.4.8 - Receiver buffer management Informative 8.4.9 - Receiver FIFO buffering Informative able 4-21 Encoder decoder block diagram conformance n/a

SpaceWire Link Interface RL Verification 4.3.4.3 State machine Ref No est No Reference Summary Notes 8.5.1 - State machine general description n/a 8.5.2.1 - General description of state machine states n/a able 4-22 State machine conformance 4.3.4.3.1 In State ErrorReset Ref No est No Reference Summary Notes 8.5.2.2.a.EXC.ERS.1 ErrorReset shall be entered on system reset or link operation error 8.5.2.2.b.EXC.ERS.2 ransmitter and receiver are disabled in state ErrorReset 8.5.2.2.c.EXC.ERS.3 After 6.4us ErrorReset -> ErrorWait 8.5.2.2.d - State machine shall remain in ErrorReset when reset is asserted Covered in 8.5.2.2.a able 4-23 State ErrorReset conformance 4.3.4.3.2 In State ErrorWait Ref No est No Reference Summary Notes 8.5.2.3.a.EXC.ERW.1 ErrorWait shall only be entered from ErrorReset 8.5.2.3.b.EXC.ERW.2 he transmitter shall be disabled and the Receiver shall be enabled 8.5.2.3.c.EXC.ERW.3 If a NULL is received then GotNULL shall be asserted 8.5.2.3.d.EXC.ERW.4 he ErrorWait state shall be left unconditionally after the 12.8us timeout. 8.5.2.3.e.EXC.ERW.5 On receiver error or incorrect character received then move to state ErrorReset able 4-24 State ErrorWait conformance 4.3.4.3.3 In State Ready Ref No est No Reference Summary Notes 8.5.2.4.a.EXC.RDY.1 State Ready shall be entered only from the ErrorWait state. 8.5.2.4.b.EXC.RDY.2 he transmitter shall be disabled and the Receiver shall be enabled 8.5.2.4.c.EXC.RDY.3 If a NULL is received then GO_NULL shall be

SpaceWire Link Interface RL Verification asserted 8.5.2.4.d.EXC.RDY.4 Remain in state Ready until LinkEnabled is asserted then move to state Started 8.5.2.4.e.EXC.RDY.5 On receiver error or incorrect character received then move to state ErrorReset. able 4-25 State Ready conformance 4.3.4.3.4 In State Started Ref No est No Reference Summary Notes 8.5.2.5.a - State Started shall be entered from state Ready when LinkEnabled is asserted. 8.5.2.5.b - When started is entered the 12.8us timer shall be started. 8.5.2.5.c.EXC.SA.1 In the started state the transmitter shall send NULLs. he receiver shall be enabled 8.5.2.5.d.EXC.SA.2 If a NULL is received then GO_NULL shall be asserted. 8.5.2.5.e.EXC.SA.3 If GO_NULL is asserted then the state machine shall move to state Connecting. 8.5.2.5.f.EXC.SA.4 At least one NULL shall be requested for transmission before moving to state connecting. 8.5.2.5.g.EXC.SA.5 On receiver error the state machine shall move to state ErrorReset 8.5.2.5.h.EXC.SA.6 On 12.8us timeout the state machine shall move to state ErrorReset. Covered in.exc.rdy.2 Covered in.exc.sa.6 able 4-26 State Started conformance 4.3.4.3.5 In State Connecting Ref No est No Reference Summary Notes 8.5.2.6.a - he connecting state shall be entered from the started state when GO_NULL is asserted. 8.5.2.6.b - he 12.8us timer shall be started when entering Connecting. 8.5.2.6.c.EXC.CON.1 he transmitter shall be enabled to send NULLs and FCs. 8.5.2.6.d.EXC.CON.2 If an FC is received then state machine shall move to state Run. 8.5.2.6.e.EXC.CON.3 On receiver error or incorrect character error the state machine shall move from state Connecting to state Run. Covered in.exc.sa.3 Covered in.exc.con.4

SpaceWire Link Interface RL Verification 8.5.2.6.f.EXC.CON.4 On 12.8us timeout the state machine shall move to state ErrorReset. able 4-27 State Connecting conformance 4.3.4.3.6 In State Run Ref No est No Reference Summary Notes 8.5.2.7.a - Run state shall be entered from connecting when GotFC is asserted. 8.5.2.7.b.EXC.RUN.1 On LinkDisable or receiver error or credit error the state machine shall move to state ErrorReset Covered in.exc.con.2 able 4-28 State Run conformance 4.3.4.4 Others Ref No est No Reference Summary Notes 8.5.3.3 - State machine transitions. Covered in.exc.* state test cases. 8.6 - AutoStart definition Covered in.exc.rdy.4 8.7 - Link Initialisation Informative 8.8 - Normal Operation Informative 8.10 - Exception conditions Informative able 4-29 Exchange level others conformance 4.3.4.5 Error Detection Ref No est No Reference Summary Notes 8.9.1 - General information n/a 8.9.2.1 - Disconnect Error Covered in.exc. states. 8.9.2.1.f.EXC.ERR.1 If disconnect error is detected in the Run state then the error shall be reported to the Network level 8.9.2.2 - Parity Error Covered in.cha.11 8.9.2.2.c.EXC.ERR.2 If parity error is detected in the Run state then the error shall be reported to the Network level 8.9.2.3. - Escape Error Covered in.cha.10

SpaceWire Link Interface RL Verification 8.9.2.3.c.EXC.ERR.3 If escape error is detected in the Run state then the error shall be reported to the Network level states. 8.9.2.4 - Credit Error Covered in.exc.run.1 8.9.2.4.c.EXC.ERR.4 If credit errr is detected in the Run state then the error shall be reported to the Network level 8.9.2.5 - Character sequence error. Character sequence error shall not be reported to the network level. 8.9.3..EXC.ERR.5 Empty packets may be discarded by the receiver. Covered in.exc. states. 8.9.4 - Exchange of silence procedure. Covered in.exc. states. 8.9.5 - Reporting errors to network levels Covered above. able 4-30 Exchange level error conformance 4.3.4.6 imecodes Ref No est No Reference Summary Notes 8.12 - imecode counter shall be implemented in SpaceWire node or router he purpose of the SpaceWire link interface is to accept timecodes for transmission using ICK_IN and IME_IN and to output timecodes received using ICK_OU and IME_OU. External logic shall be used to implement the imecode counter. ICK_IN and ICK_OU usage is covered in.cha.14, 15, 16. able 4-31 imecodes conformance 4.3.4.7 imings Ref No est No Reference Summary Notes 8.11.1 - D and S reset timing Covered in.sig.5 8.11.2.EXC.IM.1 he disconnect timeout period of 850ns nominal shall be from 727ns to 1000ns. 8.11.3.a - he 6.4us nominal timeout period shall be from 5.82us to 7.22us. 8.11.3.b - he 12.8us nominal timeout period shall be from 11.64us to 14.33us. - Covered in.exc.ers.3 Covered in.exc.erw.4

SpaceWire Link Interface RL Verification able 4-32 Link timings conformance 4.3.5 Packet Level Ref No est No Reference Summary Notes 9. - Packet format description n/a able 4-33 Packet level conformance 4.3.6 Network Level Ref No est No Reference Summary Notes 10.4 - Spacewire node shall comprise one or more SpaceWire link interfaces. SpaceWire nodes shall accept a stream of packets. 10.6.1 - ypes of packet level errors which occur. n/a 10.6.2.NE.REC.1,.NE.REC.2 On Link error the tail of the transmitter packet shall be discarded and an EEP shall be added to the tail of the currently received packet. 10.6.3 - Reception of packet with EEP. EEP is received as N- Char and passed on to packet level by receiver. 10.6.4 - Invalid destination address n/a 10.6.4.4 - An EOP,EEP received immediately after an EOP, EEP represents an empty packet. he second EOP, EEP shall be discarded able 4-34 Network level conformance n/a Covered in.exc.err.5

SpaceWire Link Interface RL Verification 5. VERIFICAION ESBENCH AND MODIFICAIONS As outlined in section 2.1.2 the verification testbench environment is based on the AAE SpaceWire link interface testbench modified by UoD. his section gives a brief overview of the testbench environment and indicates any modifications and additions which have been made to perform the verification. 5.1 ESBENCH OVERVIEW he testbench consists of a command parser which reads commands to be performed from an input command file. Each command in the file has an unique identifier which corresponds to a VHDL entity in the testbench. Each VHDL entity is responsible for the following Determining when a command is targeting the entity. Parsing the command string and performing the command, (e.g. a wait statement which causes the testbench to wait). Assuming control of the testbench until the command is completed, (i.e. no other commands are performed until the current command has completed). Acknowledging completion and status of the command to the command parser. Existing VHDL entity in the testbench include a common control unit, a SpaceWire link control unit and a SpaceWire link check unit. he common control unit provides testbench control functions wait, echo and system clock control. he SpaceWire link control unit controls the inputs of the SpaceWire link interface signals. LinkReset, LinkStart, AutoStart and LinkDisabled are controlled by this unit. he SpaceWire link control unit allows the testbench user to transmit N-Chars or timecodes to the link interface. N-Chars can be transmitted from a file, using a random number (LFSR) generator or a series of bytes read from the input command file. he SpaceWire link check unit checks the outputs of the SpaceWire link interface. he check unit is responsible for receiving N-Chars read from the link interface. N-Chars are checked against the expected character and an error is generated if the received data does not match the expected data. he link check unit can also check timecodes which are received by the link interface. 5.2 ADDIIONS AND MODIFICAIONS O HE EXISING ESBENCH he section outlines the changes which were made to the AAE testbench to perform the UoD SpaceWire link interface verification.

SpaceWire Link Interface RL Verification 5.2.1 est script hierarchy he ability to reference one script file from another has been added to the AAE testbench. his can be performed by placing the command SOURCE cmdfile in a command script. 5.2.2 UoD_Ctrl he VHDL entity UoD_Ctrl was added to the testbench and given the identifier UoDCRL_ID in the file parser.pkg. he entity UoD_Ctrl is responsible for the following. Reporting test number and test description to the verification log output file. Controlling the UoD SpaceWire link interface configuration options such as the 10MHz clock enable rate and the transmitter data rate inputs. Performing status checks on status signals which are inputs to the entity and acting accordingly. Commands which can be performed by the UoD_Ctrl entity are listed in table Command ECHO string HAL ESNUMBER val ESGROUP val CONINUE_AFER_ERROR booleanval SYSCLK_DELAY val RDCLK_DELAY val XCLK_DELAY val SLOWCLK_DELAY val RDCLK booleanval XCLK booleanval SLOWCLK booleanval DDROU val PIPELINE val RXUSELACHES val SYNCRDCLK val Description Echo a string from the command file to the verification log output file. Cause the testbench to stop running for debugging purposes Set a UoD_Ctrl output signal which indicates the test case number which is currently being performed. Set a UoD_Ctrl output signal which indicates the test group which is currently being performed. Set a control flag which determines if the testbench continues after an error has occurred. In a go/no-go testbench this value should be set to FALSE. Initial value is FALSE. Set the UU-link system clock period. Initial value is 100 ns Set the UU-link receive buffer clock period. Initial value is 100 ns Set the UU-link receive transmit clock period. Initial value is 100 ns Set the UU-link receive 10/5MHz reference clock period. Initial value is 100 ns Enable the receiver buffer clock Enable the transmitter clock Enable the 10/5MHz reference clock Set the configuration signal CFG_DDROU Set the configuration signal CFG_PIPELINE Set the configuration signal CFG_RXUSELACHES Set the configuration signal CFG_SYNCRDCLK

SpaceWire Link Interface RL Verification CFGBICLK val DISCARD_EMPY_PK val MAXCREDI val RXBUFPROGVAL val SLOWRAE_SYSCLK val SLOWRAE_XCLK val Set the configuration signal CFG_BICLK Set the configuration signal CFG_DISCARD_EMPY_PK Set the configuration signal CFG_MAXCREDI Set the configuration signal RXBUF_PROGVAL Set the configuration signal CFG_SLOWRAE_SYSCLK Set the configuration signal CFG_SLOWRAE_XCLK X_RAE val Set data transmission rate of the transmitter. Initial value is 0 (see [AD3] section 5.2.1) FLUSH_X val SA_CHECK EVEN_COMPARE SYNCHRON Set the value of the UU-link input signal FLUSH_X. FLUSH_X function is defined in [AD3] section 5.3.5.2 Perform a status check on a testbench signal. See section 5.2.3 Perform an event comparison on two testbench signals. his command is added to test the event times on DOU and SOU at reset. See section 5.2.4 Synchronises all entitys to the same testbench time. 5.2.3 Status Check he command SA_CHECK performs a status check on testbench signals. SA_CHECK can check the the following testbench signals. B-link status (State, GotNULL, etc.) UU-link status(state, GotNULL, etc.) B-link data receive, timecode receive status. UU-link data receive, timecode receive status. he command syntax is shown below. UoDCRL SA_CHECK <REPOR/NOREPOR> <signal name> <when> <EQUALS/NOEQUALS> <expected value> <timeout> <timestep>. Status check has a number of options which determine <when> the status value is checked. he options are listed below. Command NOW PREV_VALUE NEX_VALUE Description he value of <signal name> is checked against <expected value> when the command is run and the result is returned immediately. he status check can either be equals or not equals <expected value>. he previous value of <signal name> is checked against <expected result> and the result is returned immediately. he status check can either be equals or not equals <expected value>. he command NEX_VALUE checks if the <signal name> value equals <expected value> before <timeout> or if

SpaceWire Link Interface RL Verification <signal name> value does not equal <expected value> for the duration of <timeout> SA_CHECK is used extensively thoughout the verification command file as the main method of verification. 5.2.4 Event Compare he command EVEN_COMPARE is used to check the event times of reset on DOU and SOU.

SpaceWire Link Interface RL Verification 6. CODE ANALYSIS ES CASES Code analysis was performed for the test cases marked A in the verification matrix. est Case Description Code analysis.sig.4.cha.14.exc.1.exc.2.exc.fc.1.exc.fc.2.exc.fc.5 Receiver shall be tolerant off simultaneous transitions on DIN and SIN. ime interface shall comprise ICK_IN, ICK_OU, IME_IN and IME_OU. N-Chars are the only characters which are passed to the packet level. Only N-Chars shall be passed from host to the link interface for transmission. For each FC sent space shall be reserved for eight data characters. For each FC received the transmitter credit counter is incremented by eight. Receiver credit counter shall keep a credit count of the N-Chars it expects to receive. Simultaneous or near simultaneous transition on DIN and SIN causes a short pulse on RX_CLK or a missed clock pulse. his will simply cause a parity error as the bit-stream will be disrupted. Excerpt from top/spwrlink.vhd line 147-150 IME_IN : in SD_LOGIC_VECOR(7 downto 0); ICK_IN : in SD_LOGIC; IME_OU : out SD_LOGIC_VECOR(7 downto 0); ICK_OU : out SD_LOGIC; Interface to packet level is through receiver FIFO. Receiver FIFO only accepts N-Chars. Interface to transmitter is through transmitter FIFO inputs which only accept N-Chars. he following excerpt from receive/rxcredit.vhd line 562-567shows the FCPR count is updated by eight when an FC is loaded into the transmitter shift registers. -- if moving to this state then increment fct pointer by eight if (SENDFC_SAE = wait8more) then FCPR <= FCPR+8; else FCPR <= FCPR; end if; he following excerpt from txencode.vhd lines 92-94 shows the credit counter is incremented by eight when an FC is received. when "10" => -- got fct increment by eight CREDI_COUN <= CREDI_COUN+8; See file rxcredit_outstding_count.vhd.

SpaceWire Link Interface RL Verification.EXC.FC.6.EXC.ERW.1 At reset or disconnect the outstanding credit counter shall be zero. ErrorWait shall only be entered from state ErrorReset. See file rxcredit_outsding_count.vhd he command grep C 7 e NEX_INFCE_SAE <= ErrorWait initfsm/init_fsm.vhd was performed to determine when the next state is set to ErrorWait. he output is printed below. begin -- dependant on current state case INFCE_SAE is when ErrorReset => -- state transition to state ErrorWait after 6.4 us if (IMER_EVEN_EN = '1') then NEX_INFCE_SAE <= ErrorWait; else NEX_INFCE_SAE <= ErrorReset; end if; when ErrorWait => -- state transition dependant on errors and 12.8us timeout -- if error then move to state ErrorReset, error is RX_ERR or -- GO_FC or CHAR_SEQ_ERROR if (RX_ERR = '1' or GO_FC = '1' or CHAR_SEQ_ERROR = '1') then NEX_INFCE_SAE <= ErrorReset; elsif (IMER_EVEN_EN = '1') then NEX_INFCE_SAE <= Ready; else NEX_INFCE_SAE <= ErrorWait; end if; when Ready => -- state transition dependant on errors and LINK_ENABLED -- if error then move to state ErrorReset, error is RX_ERR or -- GO_FC or CHAR_SEQ_ERROR if (RX_ERR = '1' or GO_FC = '1' or CHAR_SEQ_ERROR = '1') then.exc.erw.2 he transmitter shall be disabled and the receiver enabled in state ErrorWait. the following excerpt from initfsm/init_fsm.vhd lines 460-463 shows the output statements for the state ErrorWait. Only the receiver is enabled. when ErrorWait => RX_RS <= '0'; -- enable rx.exc.rdy.1 State ready shall only be entered from ErrorWait. he command grep C 10 e NEX_INFCE_SAE <= Ready init_fsm.vhd was performed to determine when the next state is set to Ready. he output is printed below.

SpaceWire Link Interface RL Verification when ErrorWait => -- state transition dependant on errors and 12.8us timeout -- if error then move to state ErrorReset, error is RX_ERR or -- GO_FC or CHAR_SEQ_ERROR if (RX_ERR = '1' or GO_FC = '1' or CHAR_SEQ_ERROR = '1') then NEX_INFCE_SAE <= ErrorReset; elsif (IMER_EVEN_EN = '1') then NEX_INFCE_SAE <= Ready; else NEX_INFCE_SAE <= ErrorWait; end if; when Ready => -- state transition dependant on errors and LINK_ENABLED -- if error then move to state ErrorReset, error is RX_ERR or -- GO_FC or CHAR_SEQ_ERROR if (RX_ERR = '1' or GO_FC = '1' or CHAR_SEQ_ERROR = '1') then NEX_INFCE_SAE <= ErrorReset; elsif (LINK_ENABLED = '1') then NEX_INFCE_SAE <= Started; else NEX_INFCE_SAE <= Ready; end if; when Started => -- state transition dependant on errors and FIRS_NULL -- if error then move to state ErrorReset, error is RX_ERR or -- GO_FC or CHAR_SEQ_ERROR if (RX_ERR = '1' or GO_FC = '1' or CHAR_SEQ_ERROR = '1' or IMER_EVEN_EN = '1') then.exc.rdy.2.ofn.4 he transmitter shall be disabled and the receiver enabled in state Ready. External 10MHz function. he following excerpt from initfsm/init_fsm.vhd lines 340-342 shows the output statements for the state ErrorWait. Only the receiver is enabled. when Ready => RX_RS <= '0'; -- enable rx he input signals SLOW_CE_SEL and SLOW_CE determine if the external 10MHz function is used. he signal SLOW_CE_SEL acts as a multiplexer as shown in the code excerpt from top/spwrlink.vhd lines 560-561 -- assign SLOW_EN which can be generated internally or externally -- receiver disconnection detection and state machine timeout SLOW_EN <= CFG_SLOW_CE when (CFG_SLOW_CE_SEL = '1') else SLOW_EN_INERNAL;

SpaceWire Link Interface RL Verification 7. NON AUO-CHECK ES CASES his section documents the test cases which are performed by the VHDL testbench but cannot be verified automatically. he following command was run on the testbench script file to determine the non auto-check tests grep e ES NUMBER e AUO-CHECK = ** NO ** < uodrun.cmd he command output is shown below with non auto-check tests shown in bold type. Other test cases were removed for clarity.. UODCRL ECHO == ES NUMBER =.EXC.FC.7 UODCRL ECHO == ES NUMBER =.EXC.FC.8 UODCRL ECHO == AUO-CHECK = ** NO ** UODCRL ECHO == ES NUMBER =.EXC.ERS.1.. UODCRL ECHO == ES NUMBER =.OFN.2 UODCRL ECHO == ES NUMBER =.OFN.3 UODCRL ECHO == AUO-CHECK = ** NO ** Figure 7-1 Non Auto-Check test cases 7.1.EXC.FC.8 est case.exc.fc.8 states the priority for characters to be transmitted over the link. For this verification the contents of the report file are used to verify the requirement. he report file is shown below. he requirement was verified as stated in the ES RESULS = section. # 1200331 ns: ========== ======== ========== ======== ========== ======== # 1200331 ns: ========== ======== ========== ======== ========== ======== # 1200331 ns: == ES NUMBER =.EXC.FC.8 # 1200331 ns: ========== ======== ========== ======== ========== ======== # 1200331 ns: == ES DESCRIPION = RANSMIER CHARACER PRIORIY # 1200331 ns: == he order of priority for transmission shall be # 1200331 ns: == 1) imecode # 1200331 ns: == 2) FC # 1200331 ns: == 3) N-Char # 1200331 ns: == 4) NULL # 1200331 ns: == # 1200331 ns: == ES SRAEGY = # 1200331 ns: == Data ransfer is performed. with intermittent timecodes # 1200331 ns: == and FCs transmitted as space is available. NULLS transmitted # 1200331 ns: == when no data, FC or timecode. # 1200331 ns: == # 1200331 ns: == AUO-CHECK = ** NO ** # 1200331 ns: == # 1200331 ns: == ES RESULS = # 1200331 ns: ========== ======== ========== ======== ========== ======== # 1200331 ns: == # 1200331 ns: == B-link RESE, UU-link RESE # 1200531 ns: == Wait for both ends to start-up # 1222281 ns: == UU-link state = Run, B-link state = Run # 1222281 ns: == # 1222281 ns: == UU-link transmits 16 data characters # 1222281 ns: == CHECK FCs are transmitted in data bit stream

SpaceWire Link Interface RL Verification # 1222730 ns: == CHECK UU-link transmits timecode in data bit stream # 1222897 ns: == B-link receives 4 data characters # 1222957 ns: == CHECK NULLS transmitted when no data # 1242957 ns: == B-link receives remaining 12 data characters # 1243127 ns: == # 1243127 ns: ========== ======== ========== ======== ========== ======== # 1243127 ns: ========== ======== ========== ======== ========== ======== Figure 7-2.EXC.FC.8 7.2.OFN.3 est case.ofn.3 tests the reset requirement for the output signals as specified in [AD3]. he following waveform shows the reset applied to the SpaceWire link interface core.

SpaceWire Link Interface RL Verification Figure 7-3.OFN.3 non auto-check test case