Summer 2003 Lecture 21 07/15/03 Simple I/O Devices Simple i/o hardware generally refers to simple input or output ports. These devices generally accept external logic signals as input and allow the CPU to read the value, or accept values from the CPU and hold them as output logic levels. A simple output port can be implemented using a latch circuit or a flip-flop circuit. Latches and flip-flops have data inputs, data outputs, and gate or clock inputs. They sample their inputs when the gate or clock signal is true, and hold that value until the next time the gate or clock is asserted. Different devices can trigger at different times. Examples of different triggering is the NMI which is edge-sensitive, and the INT which is levelsensitive. Generally, the latches have a level sensitive gate input and flip-flops have an edge sensitive clock input. A latch with a level sensitive gate input will continually sample its inputs and pass them through to the output as long as the gate input is asserted. When the gate input is de-asserted, the last input will be held on the outputs until then next time that the gate is asserted. A flip-flop with an edge sensitive clock will sample the inputs and hold them on its outputs whenever the active edge (either rising or falling edge) occurs. The 74LS373 and 74LS374 are two chips commonly used to implement simple output ports. The 74LS373 is an 8 bit wide latch with an active high, level sensitive gate input. The 74LS374 is an 8 bit wide D flip-flop with a rising edge sensitive clock input. Each of these devices has tri-state outputs and so each also has an active low output enable to enable the tri-state output drivers. The following symbols can be used to represent these devices. The and pins represent an 8 bit wide data bus in and out of the devices. The G input of the 74LS373 is the active high gate input. The input signal with the caret
G OE OE 74LS373 74LS374 A simple input port can be implemented using nothing more than a tri-state buffer chip. It is necessary to use a tri-state buffer, as the outputs of the buffer need to be connected to the data bus. It is essential that the buffer output only appear on the data bus when a read is being performed at the port address for the buffer. Otherwise, bus contention would occur between the buffer chip and any other device attempting to place data on the bus. A common tri-state buffer is the 74LS244. This is chip contains two sets of four tri-state buffers with a common output enable. If the two output enables are tied together, it can be used as an 8 bit wide buffer with active low enable.
The following symbol can be used for the 74LS244. The and pins represent an 8 bit wide data bus in and out of the chip. The two enables, OE1 and OE2 are active low enables. OE1 enables output bits 0-3 and OE2 enables output bits 4-7. OE1 OE2 74LS244 Complex I/O Devices There are many peripheral chips available that implement more complex i/o functions. For example, the 16550 UART used in most IBM PC type computers performs: parallel to serial data conversion, serial to parallel data conversion, FIFO buffering of received data, and baud rate (data clock rate) generation in a single chip. As another example, the 8254 provides three 16 bit programmable timers that can be independently configured to work in any one of five different timing modes. Although the internal operation of these devices can be quite complex, they are generally relative simple to interface to a computer system bus.
These devices generally have several internal registers, and so will have some number of address inputs used to select the specific register being read from or written to. There will be a chip select signal of some sort that is used to enable the device to respond to its bus interface inputs. There will usually be read and write strobe inputs that are used to read from or write to the device. Most manufacturers that produce microprocessor chips will also have a line of peripheral chips that are designed to work with that manufacturers microprocessors. These chips will have inputs that are compatible with the bus timing generated by the microprocessor. It is generally very simple to hook up peripherals within a product family line, as they are designed to work together. It is sometimes more difficult when trying to use a peripheral chip from one vendor with a microprocessor from a different manufacturer as the bus timings may be different and incompatible. One example of a peripheral chip within the Intel 8088 family product line is the 8255 Programmable Peripheral Interface. This device has three 8 bit parallel input/output ports that can be configured to work in one of several modes, a control port that is used to configure the operating modes of the three data ports, four internal registers, it requires two address lines to select one of the ports, an active low chip select line, an active low RD (read) and WR (write) inputs, HTTP://drew.hickmans.net/8255a.pdf
The following symbol can be used to represent the 8255: A1 A0 RD WR CS Port A Port B Port C 8255 A1 A0 RD WR CS READ Op. 0 0 0 1 0 Port A -> Data Bus 0 1 0 1 0 Port B -> Data Bus 1 0 0 1 0 Port C -> Data Bus 1 1 0 1 0 Ctrl Word -> Data Bus WRITE Op. 0 0 1 0 0 Data Bus -> Port A 0 1 1 0 0 Data Bus -> Port B 1 0 1 0 0 Data Bus -> Port C 1 1 1 0 0 Data Bus -> Ctrl Word DISABLE FUNC. X X X X 1 Data Bus -> Three State X X 1 1 0 Data Bus -> Three State