ES611 FPGA Based System Design Behavioral Model
Structural procedures Two statements Initial always initial they execute only once always they execute for ever (until simulation finishes)
initial block Start execution at sim time zero and finish when their last statement executes module example; initial $display( VLSI ); initial begin #50; $display( VerilogHDL ); end endmodule
always block Start execution at sim time zero and continue until sim finishes
Procedural assignments Update values of reg, integer, real or time variables Value remains same until it is updated with different value Two types Blocking assignments Non-blocking assignments
Blocking assignments Block assignments = executed in the order they appear executed one after another. first statement blocks the second until it is done Example: a = b; b = a; Both a & b = b
Non-blocking assignments Non-blocking assignments <= executed in parallel. an earlier statement does not block the later statement. Example: a <= b; b <= a; swap a & b
Events @ always @(signal1 or signal2 or..) begin.. end always @(posedge clk) begin.. end always @(negedge clk) begin.. end
Events (contd) half adder implementation module half_adder(s,c,a,b); output S, C; input A, B; reg S,C; wire A, B; always @(A or B) begin S = A ^ B; C = A && B; end endmodule Behavioral edge-triggered DFF implementation module dff(q,d,clk); output Q; input D, Clk; reg Q; wire D, Clk; always @(posedge Clk) Q = D; endmodule
Events (contd) wait (expr) always begin wait (ctrl) #10 count = count + 1; #10 count2 = count2 + 2; end
Conditional Statements data flow Syntax: conditional_expression? expression_if_true : expression_if_false 2-to-1 multiplexer: assign output = s? input1 : input0; 4-to-1 multiplexer: assign output = s[1]? (s[0]? in3 : in2) : (s[0]? in1 : in0)
Conditional Statements - Behavioral if else Type 1 if (enable) out = in; Type 2 if (num_queued < Max_Q) begin data_queue = data; number_queued = number_queued + 1; else $display( Queue full )
Conditional Statements Type 3 if (alu_control == 0) y = x + z; else if (alu_control == 1) y = x - z; else if (alu_control == 2) y = x * z; else $display( Invalid ALU control signal );
Conditional Statements - Examples module mux4to1 (w0, w1, w2, w3, S, f); input w0, w1, w2, w3; input [1:0] S; output f; reg f; always @(w0 or w1 or w2 or w3 or S) if (S == 2'b00) f = w0; else if (S == 2'b01) f = w1; else if (S == 2'b10) f = w2; else if (S == 2'b11) f = w3; endmodule
module mux4to1 (W, S, f); input [0:3] W; input [1:0] S; output f; reg f; always @(W or S) if (S == 0) f = W[0]; else if (S == 1) f = W[1]; else if (S == 2) f = W[2]; else if (S == 3) f = W[3]; endmodule
Building a 16-to-1 multiplexer combining 4-to-1 multiplexers: module mux16to1 (W, S16, f); input [0:15] W; input [3:0] S16; output f; wire [0:3] M; mux4to1 Mux1 (W[0:3], S16[1:0], M[0]); mux4to1 Mux2 (W[4:7], S16[1:0], M[1]); mux4to1 Mux3 (W[8:11], S16[1:0], M[2]); mux4to1 Mux4 (W[12:15], S16[1:0], M[3]); mux4to1 Mux5 (M[0:3], S16[1:0], f); endmodule
Multiway Branching Nested if-else-if becomes unwieldy if too many alternatives Solution is case statement
Case statement - examples module dec2to4 (W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(W or En) case ({En, W}) 3'b100: Y = 4'b1000; 3'b101: Y = 4'b0100; 3'b110: Y = 4'b0010; 3'b111: Y = 4'b0001; default: Y = 4'b0000; endcase endmodule
Case statement - examples module dec2to4 (W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(W or En) begin if (En == 0) Y = 4'b0000; else case (W) 0: Y = 4'b1000; 1: Y = 4'b0100; 2: Y = 4'b0010; 3: Y = 4'b0001; endcase end endmodule
casez, casex In case statement it is possible to use the logic values 0, 1, x, and z in the case alternatives. Verilog provides two variants of the case statement: The casez statement treats all z values in the case alternatives as don t-cares. The casex statement treats all z and x values as don tcares.
Casex - examples module priority_encoder (W, Y, z); input [3:0] W; output [1:0] Y; output z; reg [1:0] Y; reg z; always @(W) begin z = 1; casex (W) 4'b1xxx: Y = 3; 4'b01xx: Y = 2; 4'b001x: Y = 1; 4'b0001: Y = 0; default: begin z = 0; Y = 2'bx; end endcase end endmodule
Loops Four types of looping statements While For Repeat Forever
While loop Loop executes until while expression becomes false
For loops Syntax: for (initial_index; terminal_index; increment) statements; Example: module dec2to4 (W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; integer k; always @(W or En) for (k = 0; k <= 3; k = k+1) if ((W == k) && (En == 1)) Y[k] = 1; else Y[k] = 0; endmodule
Repeat loops Executes the loop a fixed number of times Cannot be used to loop on a logical expression Number, constant, variable must be used
Forever loops Loop does not contain any expression and executes forever until $finish task is encountered Exited by the use of disable statement
Tasks and Functions
Tasks Declared with keywords task and endtask Must be used if one of the following conditions is true There are delay, timing, or event control constructs (#, @, wait) Procedure has zero or more than one output arguments Procedure has no input arguments
Task - examples module mult (clk, a, b, out, en_mult); input clk, en_mult; input [3:0] a, b; output [7:0] out; reg [7:0] out; always @ (posedge clk) multme (a, b, out); // task invocations task multme; // task definition input [3:0] xme, tome; output [3:0] result; wait (en_mult) result = xme * tome; endtask endmodule
Functions Declared with keywords function and endfunction typically used to perform a computation, or to represent combinational logic Cannot contain any delays; functional happen in zero simulation time Has only input arguments and returns a single value through the function name Can enable other functions, but not tasks
Functions - examples
Tutorial A position encoder uses the gray code (two successive values differ in only one bit) for angle measurement. Design a suitable digital converter circuit which converts Binary coded decimal to Gray Code. Consider the circuit to have don t care terms for BCD values of 10 and above. Develop a Verilog model for the circuit. Develop a Verilog model for a combinational circuit that implements the following three Boolean equations, representing part of the control logic for an air conditioner: heater_on = temp_low.auto_temp + manual_heat cooler_on = temp_high. auto_temp + manual_cool fan_on = heater_on + cooler_on + manual_fan Also implement the digital circuit for this model.
Tutorial A priority encoder has 2 N inputs. It produces an N-bit binary output, indicating the most significant bit of the input that is TRUE. Design a priority encoder with a 8-bit input using Verilog HDL. To avoid generating latches, assume that the priority encoder generate output of all zeros by default.
Reference Samir Palnitkar, "Verilog HDL: a guide to digital design and synthesis", Prentice Hall, Second Edition, 2003