Floating Point User Guide 3/2014 Capital Microelectronics, Inc. China
Contents Contents... 2 1 Introduction... 3 2 Floating_Point Overview... 4 2.1 Pin Description... 4 2.2 Parameter Description... 5 2.3 Block Diagram... 6 3 Floationg_Point IP Usage... 7 3.1 Floating_Point operation timing diagram... 7 3.2 Floating_Point functional description... 8 4 Resource usage and performance analysis... 10 5 Generate File Directory Structure... 11 Revision History... 14 http://www.capital-micro.com 2
1 Introduction This document mainly describes the usage of the Floating_Point IP. It is of 6 kinds of functions and they can be customized. The Floating_Point IP supports the following features: Compliance with IEEE-754 standard Support single precision Supported operators: addition/subtraction multiply divide comparison conversion from floating-point to fixed-point conversion from fixed-point to floating-point Fully synchronous design with a single clock Pure combinational logic or fixed output latency can be customized Device family support: CME-M7,CME-M5 http://www.capital-micro.com 3
2 Floating_Point Overview 2.1 Pin Description Table 2-1 Floating_Point interface Interface Name Direction Width Description System clk Input 1 Clock rst_n Input 1 Reset, low active din_a Input 32 or Input data a WIDTH_INT_INPUT din_b Input 32 or Input data b WIDTH_DATA_INPUT (float_to_fixed conversion minus no this port ) WIDTH_INT_INPUT add_sub Input 1 Specifies the operation is add or subtract, only present when add /sub operation is programmable mode 0:add 1:subtract User interface din_en Input 1 Data input enable dout Output 32 or WIDTH_DATA _OUTPUT Output data, no this port in compare operation and the value is 32 except float_to_fixed conversion overflow Output 1 Set high when the output is too large to represent underflow Output 1 Set high when the output is too small to represent division_by _zero operation_ invalid Output 1 Set high to indicate divide-byzero during divide operation and only present on divide operation Output 1 Set high when the inputs cause an invalid operation http://www.capital-micro.com 4
dout_rdy Output 1 Set high when to indicate the result is valid dout_ compare Output 4 Data output of compare, only present on compare operation 0001 --- din_a == din_b 0010 --- din_a < din_b 0011 --- din_a <= din_b 0100 --- din_a > din_b 0101 --- din_a >= din_b 1xxx --- nan 2.2 Parameter Description Table 2-2 Floating_Point parameter description Name Type Value Description OP_TYPE Integer 001~110 Specifies the kinds of operation 001 --- Add/Sub operation 010 --- Multiply 011 --- Division 100 --- Compare 101 --- Fixed_to_float conversion 110 --- Float_to_fixed conversion ADD_SUB_TYPE Integer 00/01/10 Specifies add or subtract or both 00 --- Add/Sub operation controlled by add_sub port 01 --- Add 10 --- Sub COMPARE_OP_TYPE Integer 001~111 Specifies the compare operation type 001 --- equal 010 --- less 011 --- less equal 100 --- lager 101 --- lager equal 110 --- not equal 111 --- dynamically controlled by operand a and b WIDTH_INT_INPUT Integer 1~32 Specifies the integer width of input http://www.capital-micro.com 5
data in fixed_to_float conversion WIDTH_DATA_INPUT Integer 2~64 Specifies the total width of input data in fixed_to_float conversion WIDTH_INT_OUTPUT Integer 1~32 Specifies the integer width of output data in float_to_fixed conversion WIDTH_DATA_OUTPUT Integer 1~64 Specifies the total width of output data in float_to_fixed conversion Add/sub:0~10 Multiply:0~6 LATENCY Integer Divide:0,1,2,6,14,31 Compare:0~3 Specifies the output data latency Float_to_fixed:0~6 Fixed_to_float:0~6 2.3 Block Diagram Floating_Point Special value logic Operand A Dout Operand B Sign logic Exponent logic Pipeline logic ALU (Add/Sub Multiply Divide Compare Fixed_to_float Float_to_fixed) Dout_compare Mantissa logic Figure 2-1 Floating Point IP block diagram Operand A and B are the input data of the floating point IP. The special value logic is used to handle the special values(as Table3-1). The input data will be separated into three parts: sign, exponent and mantissa and every part has related logic. The pipeline logic will generate the pipeline stage according to the parameter LATENCY. Then the data input ALU part and finish the operation according the parameter OP_TYPE. There are 6 kinds of operation: add/sub, multiply, divide, compare, float_to_fixed conversion and fixed_to_float conversion. Dout_compare is the compare operation result and dout is the result of the other 5 kinds of operation. http://www.capital-micro.com 6
3 Floationg_Point IP Usage 3.1 Floating_Point operation timing diagram clock 1 2 3 4 5 6 7 8 9 10 din_a data_a1 data_a2 din_b data_b1 data_b2 add_sub din_en dout_rdy dout dout_1 dout_2 overflow underflow Figure 3-1 add_sub operation(latency = 2) TimeGen clock 1 2 3 4 5 6 7 8 9 10 din_a data_a1 data_a2 data_a3 din_b data_b1 data_b2 data_b3 din_en dout_rdy dout dout_1 dout_2 dout_3 operation_invalid division_by_zero Figure 3-2 divide operation(latency = 0) TimeGen http://www.capital-micro.com 7
clock 1 2 3 4 5 6 7 8 9 10 din_a data_a1 data_a2 data_a3 din_b data_b1 data_b2 data_b3 din_en dout_rdy dout_compare dout_1 dout_2 dout_3 Figure 3-3 compare operation(latency = 0) TimeGen clock 1 2 3 4 5 6 7 8 9 10 din_a data_a1 data_a2 din_b data_b1 data_b2 din_en dout_rdy dout dout_1 dout_2 TimeGen Figure 3-4 fixed_to_float operation(latency = 1) 3.2 Floating_Point functional description The IEEE-754 supports four special inputs. They are summarized in Table 3-1. Table 3-1 Floating_Point special values Meaning Sign Field Exponent Field Mantissa Field +0 or -0 Sign of 0 All 0's All 0's +infinity or - infinity Sign of infinity All 1's All 0's NaN(Not-a-Number) Don't care All 1's Non-zero + Denormalized Sign of the denormalized or -Denormalized number All 0's Non-zero Operation_invalid pin indicates that the operation performed is invalid, All the invalid cases as Table 3-2. http://www.capital-micro.com 8
Table 3-2 Floating_Point invalid cases Operation Invalid cases dout Add/Sub Any of the inputs is NaN 32'h80000000 +infinity +(-infinity) -infinity +(+infinity) +infinity -(+infinity) -infinity -(-infinity) Multiply Any of the inputs is NaN 0 infinity 32'h80000000 Any of the inputs is NaN Divide 0 / 0 infinity / infinity 32'h80000000 http://www.capital-micro.com 9
4 Resource usage and performance analysis Resource usage and performance of the Floating_Point IP on Primace Table 4-1 Floating_Point IP resource usage and performance Resource LUT4 Regs MAC Performance Add(latency = 0) 841 0 0 Sub(latency = 0) 852 0 0 Add/Sub(latency = 10) 795 553 0 100 MHz Multiply(latency = 0) 340 0 4 Multiply(latency = 6) 358 321 4 100 MHz Divide(latency = 0) 776 553 0 Divide (latency = 31) 1550 2277 0 130 MHz Compare (==, latency = 0) 94 0 0 Compare (==, latency = 3) 98 77 0 200 MHz Float_to_fixed (WIDTH_DATA_OUTPUT = 64, WIDTH_INT_OUTPUT= 32, 592 0 0 latency = 0) Float_to_fixed (WIDTH_DATA_OUTPUT = 64, WIDTH_INT_OUTPUT= 32, 776 406 0 120 MHz latency = 6) Fixed_to_float (WIDTH_DATA_INPUT = 64, WIDTH_INT_INPUT= 32, 564 0 0 latency = 0) Fixed_to_float (WIDTH_DATA_INPUT = 64, WIDTH_INT_INPUT= 32, latency = 6) 559 372 0 120 MHz http://www.capital-micro.com 10
5 Generate File Directory Structure The Floating Point IP Wizard generated file includes: source files (src), simulation files(sim) and example design files and related document. The detailed design directory structure is as below. Project src outputs ip_core ip_top.v (define by user) floating_point_v1 sim src doc example alligner.v FPU.v mult_m5.v matlab src_vp *.vp (Protected RTL) tb_m5 CME_floating_poi nt_user_guide_en 01.pdf FPU_demo_m5 FPU_demo_m7 CME_floating_point_ example_user_guide_ EN01.pdf mult_m7.v CONFIG floating_point_tb.do floating_point_tb.v floating_point_tb_ modelsim.f js_sim.v = directory = source RTL code = simulation related files = documentation pipeline.v tb_m7 CONFIG floating_point_tb.do floating_point_tb.v floating_point_tb_ modelsim.f m7s_sim pipeline.v Figure 5-1 IP wizard generated file directory structure http://www.capital-micro.com 11
Table 5-1 Generated File Directory structure Directory Description src\ Directory for project source code, including IP wizard generate code. ip_core\ The directory specially for all IPs \floating_point_v1 Directory for floating_point IP \doc\cme_floating_point_user_guide_en01.doc User guide for floating_point IP \src \src\fpu.v \src\alligner.v \src\mult_m5.v \src\mult_m7.v IP Design RTL The src of floating_point IP (Encrypted) The control module of floating_point IP (Encrypted) The mult module for m5 of floating_point IP (Encrypted) The mult module for m7 of floating_point IP (Encrypted)) \sim tb_m5 \floating_point_tb.v tb_m5 \floating_point_tb_modelsim.f tb_m5 \floating_point_tb.do tb_m5 \js_sim.v tb_m5 \ pipeline.v tb_m5 \CONFIG Testbench of floating_point IP for m5 Modelsim simulation related files Do script for Modelsim simulation Other RTL design files and configuration files for simulation on M5 tb_m7 \floating_point_tb.v Testbench of floating_point IP for m7 tb_m7 \floating_point_tb_modelsim.f Modelsim simulation related files tb_m7 \floating_point_tb.do Do script for Modelsim simulation tb_m7 \m7s_sim.v Other RTL design files and configuration tb_m7 \ pipeline.v files for simulation on M7 tb_m7 \CONFIG \src_vp Protected design RTL for Modelsim simulation \*.vp Encrypted floating_point IP related design RTL \matlab \*.txt Files stores the input data and expected results \example FPU_demo_m5.zip FPU_demo_m7.zip Floating_point IP example on M5 device Floating_point IP example on M7 device http://www.capital-micro.com 12
CME_floating_point_example_user_guide _EN01.pdf The guide of floating_point IP example on M5 and M7 device http://www.capital-micro.com 13
Revision History Revision Date Comments 1.0 2013-03-14 Initial release http://www.capital-micro.com 14