Model Paper 1 Seventh Semester B.E. Degree Examination Time: 3 hrs. Max. Marks: 100 Note: 1. Answer any FIVE full questions, selecting at least two questions from each part. PART - A 1. a. What is an embedded system? What is the deference between VLSI and embedded system? (04 Marks) Ans: Embedded system : an a combination of hardware and software parts as well as other components that we bring together into product such as a cell phone, a music player, a network renter or an aircraft guidance systems. They are the system with in another system. Difference between VLSI and embedded system: Embedded systems techniques allows us to make products that are smaller, faster and non reliable and cheaper. They allow us to bring feature and capabilities to every day things that could only be dreamed about just a few years ago. VLSI: Very large scale integrated circuit are the key components in enabling all of this to happen. VLSI is in terms of million of transistors collected onto a single integrated circuit. Without VLSI embedded by systems would not be feasible and without embedded system, VLSI would serve little purpose. 1. b. What does the term real time means. (06 Marks) Ans: The system is real time demands that the system must respond to designated external and internal events with in a specified time interval. The expected response is typically the execution of the task associated with triggering event. These are three kinds of real time systems hand on the urgency of meeting the required time constraint. a) Soft Real time systems: A system is considered to be a soft real time if failure to meet the time constraint results only in degraded performance. b) Hard Real time system: If a time constraint is not met in a hard real time system the system is said to have failed. Such a failure may be seen as catastrophic if it can result in considerable link to people to the environment or to a system being monitorial or controlled. c) A firm real time system: This system falls in between with a main of the two kind of tasks. 1. c. Briefly describe the major elements of the embedded system development life cycle. (10 Marks) Ans: The major elements of the development life cycle are : Requirement Analysis, specification, system architecture, hard ware and software design, system integration, system validation and finally operation and maintenance. The hardware portion of the life cycle involves the design development and test of the physical system architecture, packaging, printed circuit boards and ultimately the individual components. The software portion involves the task or algorithms portion of the application. Such software may be 4-Model Question paper I.indd 93 8/30/2013 10:08:57 AM
June 13 - M.P. 1 written in a high level language assembler or a mixture of the two work in assembly requires detailed knowledge of the microprocessor architecture and its register structures. User Inputs Requirements Analysis Requirements Definition Hardware Architecture Block Diagram Schematic and logic diagrams prototype Verified Hardware Hardware Design Hardware Implementation Hardware Testing System Architecture Functional Software Design Software Implementation Software Testing Software Architecture Module Module Object Code Verified Software System integration System Validation Operation and Maintenance Verified System Verified System Fig. Embedded system life cycle The traditional design approach has been to traverse the two sides of the accompanying diagram separately. That is Design the software components Bring the two together Spend time testing and debugging the system Contemporary methodologies follow the combined and simultaneous design of both the hardware and the software 4-Model Question paper I.indd 94
M.P. 1 June 13 - components, with the objective of meeting system level requirements, through trade off between these two. The key points in such an approach as to specify and design and develop both aspects of the system concurrently with the goal of increased productivity, reduced design cycle time and improved product quality. 2. a. Identify and briefly describe the major functional blocks that comprise the computing CPU. (07 Marks) Ans: Major functional blocks that comprise the computing are an follows. i) Input ii) Output iii) Memory iv) Data Path and Control Memory: The memory block serves to hold collection of program instructions that we call software and firm ware as well as to provide short term storage for input data output data and intermediate results of computations. Input : Data as well as other kinds of signals comes into the system from the external world through input block. Once inside of the system, they may be divided into any number of destinations. Output: The output block provides the means to send data or other signals back to the outside world. Data Path and Control Block: This co-ordinates the activities of the system as well as performs. Computations and data manipulation operations necessary to execute the application. In performing its responsibilities the CPU fetches instructions from memory interprets them, and then perform the task indicated by the instruction. In doing so it may retrive additional data from memory or from the input block. Input Data Path and Control Memory output 2. b. What is meant by the term bus width? (05 Marks) Ans: The width of a bus, that is the number of figures or bits that is can carry simultaneously, provides on indirect measure of how quickly information can be moved. Transferring 64 bits of data on a bus that is 32 bit wide requires two transfers to move the data. Source 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Destination time 4-Model Question paper I.indd 95
June 13 - M.P. 1 2. c. Briefly explain the block diagram of microprocessor based system. (08 Marks) Ans: Microprocessor: A microprocessor is an integrated implementation of the central processing unit portion of the machine it is often simply referred to as a cpu or data path. Block diagram for a micro processor based system is as shown below. Firmware Memory Data Memory Microprocessor Input/ output device Outside world signals Real time clock Input /output device Hosting application Input /output device Registers as small amounts of high speed memory that are used to temporarily store frequently used values such as a loop index or the index into a buffer. Input output subsystems the external memory system, clock or timing reference are the basis for timing, scheduling or measuring clasped time are included in computer system. All such components are connected via a system bus or buses. External to the microprocessor to different memory block are present. a) The firmware or program store contains the application code, and b) Data store: Contains data that is being manipulated, sent to or brought in from the external world. 3. a. What is state diagram? What is the purpose of a state diagram and what information can we derive from it? (12 Marks) Ans: State diagram or graph is one means send to capture, describe and specify the behavior of a system. In a state diagram each state is represented by a circle node or vertex. For example: A memory device has two states: its output is a logical 1 or a logical 0. Thus to express its behaviors, two node are required as shown in fig. below. 0 1 States of a Digital Memory Device Transition between two states is shown using a labeled directed line or arrow called an arc as shown in fig below. Since the times has a direction, the state diagram is refused to as a directed graph. The head or point of the arrow identifies the final state and the tail or back of arrow identifies the initial state. 4-Model Question paper I.indd 96
M.P. 1 June 13 - [Inputs]/ [Outputs] state b state a [Inputs]/ [Outputs] Transitions Between sates in a Digital Memory Device The state diagram is very powerful tool for specifying and modelling the behavior of many different kinds of hardware and software systems from a high level, abstract point view and as the design progresses from a detailed point follow. For example: We can use state diagram shown in fig. (a) below to describe an evenings entertainment. The diagram graphically impresses the same behavior that is described textually in fig. (b). enter room awake boring event asleep fall off chair Fig. a) An example State Diagram enter room if in state awake input boring event. Change to state asleep also if state asleep input fall off chair Change to state awake Fig. b) Textual Description of the Behavior Expressed in the State Diagram In the embedded world, the state diagram is a very powerful tool for specifying and modeling the behaviour of many different kinds of hardware and software systems from a high level, abstract point of view and as the design progress, from a detached point of view. 3. b. What are the major differences between the following types of read only memory ROM, PROM, EPROM, EEPROM and flash. (08 Marks) Ans: ROM : (Read Only Memory) During normal operation, ROM, can only be read. Like RAM, any location in memory is visible for immediate accuse rather than having to sequence through predecessor locations. The read operation is orders of magnitude faster than a write operation. The data is typically referred to a programming the ROM. ROM may be organised as bits, bytes or words. PROM: (Programmable ROM): is typically programmed using a programing device of one form or another. The device can only be programmed one time. EPROM: (Erasable PROM): Like the PROM, an EPROM is typically programmed using a programmable device. Erasure, so that is it can be reprogrammed, is done by placing the device under ultra violet light for a specified time intervals. EEPROM: (Electrically Erasable PROM): EEPROM is similar to EPROM, in that it can be reprogrammed rather than requiring a UV light for erasure, the operation is done electrically via a programming device. Flash: A kind of EEPROM. Its advantage is that it can be reprogrammed in situ. The device does not have to be removed from the circuit for reprogramming although it can be. 4. a. Explain in brief the four different life cycle models. (16 Marks) Ans: Common life cycle models are: a) Water fall b) V Cycle c) Spiral d) Rapid prototype 4-Model Question paper I.indd 97
June 13 - M.P. 1 Water fall model : The water fall modal represents a cycle specifically a series of steps appearing much like a water fall sequentially one below the next as shown in fig. below. Review and Revise Primary Design Review and Revise Detailed Design Review and Revise Implementation Review and Revise Successive steps are linked in a chain manner and each step is connected to the previous phase. Reverse connection provides an essential clarification backwards to ensure that the solution agree with and follows from the specification. With the water fall model, the recognition of problems can be delayed until late states of development when the cost of repair in higher. b) The V cycle model: specification Requirement Design development Verification and Validation Test and evaluation Implementation and maintains System Test Decompression Verification System integration System Verification Performance test Design Primary Design Verification Integration test Implementation Verification Detailed Design Until test Code 4-Model Question paper I.indd 98
M.P. 1 June 13 - The V cycle is similar to the waterfall model except that it places greater emphasise on the importance of addressing testing activities up front instead of later in the life cycle. Each stage associates the development activity for that phase with a test or validation at the same level. Here if one fellows the sequence down the left hand side of the drawing, one can see that the specification and design procedure utilizes a top down model, when as implementation and test proceed from a bottom up as is reflected on the right hand side of the drawing shown below. The development concluder the design and design related test portion of the development cycle of the system with both a verification and a validation test against the original specification. c) The spiral model: The spiral model brings with good specification of the requirements. It then initiatively completes a little of each phase. Its philosophy is to start small enplou the risks develop a plan to deal with the risks and commit to an approach for the next iteration. The cycle continues until the product is complete. A simplified version of a spiral by cycle is as shown below. Determine objectives cost Identify and Resolve risks start Evaluate alternatives Plan Next Iteration Release Develop Deliverable The spiral model is an improvement on the waterfall and V models because it provides for multiple builds as well as several opportunities for risk assessment and customer involvement. On the negative side it is elaborate, difficult to manage and does not keep all developers occupied during all of the phases. d) Rapid prototyping: The Rapid prototyping model is intended to provide rapid implementation of high level portion of both the software and hardware and the hardware only in the project. The approach allows developers to construct working portion of the hardware and software in incremental stages. Each stage consists of design code and unit test, integration test and delivery. The proto type is useful for both the designer and the customer. For the designer, it enables the early development of major prices of the intended functionality of system. The prototype can be either evolutionary or throw anyway. It has the advantages of having a working system early in the development process. To the effective however the rapid protyping approach requires careful planning at both the project management and designer levels. 4. b. What are the five steps for a successful design. (04 Marks) Ans: The five steps for a successful design is are follows. a) Requirement definition b) System specification c) Functional design d) Architectural design e) Prototyping 4-Model Question paper I.indd 99
June 13 - M.P. 1 The formality of each step depends on the complexity of the end product. If you are working alone or with several other in your own company on a smaller project, a white board in the center of the gauags can often suffice. If you are orchestrating a project that includes developer, manufacturers and regulations in several countries around the world, the need for formality increases. When working with each of these phases of a product life cycle, we must remember that they are guide lines- collective host practices. They are not a checklist to a successful project and they are not exhaustive. PART - B 5. a. What is scheduling strategy? Explain in brief its categories. (04 Marks) Ans: Scheduling strategy: The criteria for deciding which task is to run next are collectively called a scheduling strategy. Scheduling strategy generally fall into three categories. a) Multiprogramming: In which the running task continues until it performs an operation that requires waiting for an internal event. b) Real time: In which task with specified temporal deadlines are guaranteed to complete before the deadlines expire. System using such a scheme requires a response to certain events with in a well defined and constrained time. c) Time sharing: in which the running task is required to give up the cpu so that another task may get a turn under a time scheduled strategy, a hardware timer is used to preempt the currently executing task and return control to the operating system. Such a scheme permits one to reliably ensure that each process is given a slice of time to use the operating system. 5. b: What is task control Block (TCB). Briefly explain with it's block diagram. (08 Marks) Ans: Each process is represented in the operating system by a data structure called a task control block (TCB) also known as a process control block. The TCB contains all the important information about the task. A typical TCB, contain following information. Pointer (for linking the TCB to various queues) Process 1D and state Program counter Cpu register Scheduling information (priorities and pointers to scheduling queues). Memory management information (tag labels and cache information) I/O status information (resources allocated or open files) Pointer State Process ID Program Counter Register Contents Memory limits Open files etc TCB allocation may be states or dynamic. State allocation is typically used in embedded systems with no memory management. Then an a fixed number of task control blocks, the memory is allocated at system generation time and pleased in a dormant or unused state. When task is initiated, a TCB is created and the appropriate information is entered. The TCB is then placed into the ready state by the schedule. From the ready state, it will the be moved to the excute state by dispatches. When a task terminates, the associated TCB is returned to the dormant state. 4-Model Question paper I.indd 100
M.P. 1 June 13 - With dynamic allocation, a variable number of task control blocks can be allocated from the heap at run time. When a task is created the TCB is created, initialized and placed into the ready state and scheduled by the scheduler. From the ready state, it will be moved to the execute state and given the cpu by dispatcher. When a task is terminated the TCB memory is returned to heap storage. 5. c. Write a brief note on stack. (08 Marks) Ans: The state in a rather simple data structure and for strong information associated with a task or thread. It is an area set aside in memory as part of system allocation. The information is hold in stack frame or activation record. Typical information that must be stored is illustrated in fig below. start of current stack frame Lower stack storage saved registers including Pc + 1, the return address Low address top of stack Local variables Fig. (a) High address When a state is used, procedures must be written to manage the process of saving accusing, and removing information to or from the stack. Such procedures are initially invoked as part of a function call or by the interrupt handler prior to a context switch. In the case of an interrupt, function interrupts are temporarily blocked to allow the mechanics of the switch to occurs. The stack management procedures also invoked when returning to the calling content to restore the original state. The current top of the state is identified by a variable called the stack pointer. When an activation record is added to the stack, the stack pointer is advanced. Fig. (a) shows the stack growing from low to high memory. Then is an alternate implementation i.e from high to low memory. Thus it is important to always read the documentation for the particular implementation being used. The stack data type generally supports the following operation. Push: Add to the top of the stack Pop: Remove from the top of the stack peek: Look at the top of the stack. 6. a. What is duplicate hardware content? Explain it in brief. (10 Marks) Ans: Duplicate hardware content: Some microprocessor architecture significantly reduces the amount of information that must be saved and restored by simply switching to a duplicate or alternate content rather than developing time to save the old; load a new one and then restore the original on return. The typical microprocessor has a limited number of general purpose register, when a context switch is necessary, the value contained therein must be saved prior to the switch and then restored an return. At the software level, several different contents can be defined and a sub set of the register allocated to each. For example with 64 general purpose register, 4 different contents each with 16 general purpose registers can be defined. Then each content can be have a set of register called R0 R15 as shown in Fig. (1) below. 4-Model Question paper I.indd 101
June 13 - M.P. 1 Reg 0 Register 0 Reg 0 Register 0 Register 1 Content 0 Register 1 Content 0 Register F Register E,0 Register 0 Content 9 Register F, 1 Register 1 Register 2 Content1 Register 3 Register F Register 0 Content 12 Register I Register 1 Register 0 Register 1 Content 2 Register F Register 0 Register F Register 1 Content 3 Reg 2F Reg 3F Register F Fig. (1) Fig. (2) When the switch is to occur, rather than saving the contents of the current set of registers, the system simply switches to a new hardware content. Because the different contents are a logical interpretation of the register set at the software level there is nothing including over lapping contents. That is a subset of registers can be included in two adjacent contents as show in fig 2. In this illustration, the fourteen and fifteenth register appear as register E and F in content 0 and as register 0 and 1 in content 1. Using such a scheme, variables can easily be passed between contents with no over load. 6. b. Implement task control block (TCB) is C. (08 Marks) Ans: In C, the TCB is implemented as a struct containing pointers to all relevant information as shown below. // the task control block struct TCB // the task valid a task (void * task data ptr) { { void (*task ptr) (void * task data ptr); function body ; void * task data ptr; } void * stack ptr; // the data passed into the task unsigned shot priority struct TCB* next ptr; Struct TCB * prev ptr; struct task data { int task data 0; int task data1; char task data2; Because the data member of a struct must all be of the same types, the pointers are all void * pointers. 6. c. Define Big 0 notion. (02 Marks) Ans: Function f (N) is 0 (g (N)) if there is a content C and a value No such that f(n) is C* g(n) for N 4-Model Question paper I.indd 102
M.P. 1 June 13-7. a. Write a brief note on interrupt call. (06 Marks) Ans: An interrupt is another special kind of procedure call. In this case, the initiator is some asynchronous internal or external event as shown in fig. below. Interrupt handler Foreground task ISR Normal execution proceeds in the foreground task. When the interrupt occurs, control is first transferred to the interrupt handler and then the appropriate ISR. The analysis of an interrupt follows that for the function call. Most processors compute the current instruction before initiating the content switch. Thus, since it is not generally known which instruction is being executed when the interrupt occurs, the longest is selected. Such a choice gives a upper bound. To this number, one must add the time for the content switch exactly as was done for the function call except that no variables are pushed onto the stack. Values cannot be passed into an ISR. The return from the ISR is the same as the function call except that once again, then are no variables to return. 7. b. What are the rules Big 0 Arithmetic based on. (08 Marks) Ans: Big 0 arithmetic is based on following rules. Order common function from smallest to longest 1, log (N), N, N log (N), N 2, N 3, -----2 N, 3 N ------ Ignore constant multipliers 300 N + SN 4 + 6.2 N = 0 (N + N 4 + 2 N ) Ignore every thing except the higher order term. N + N 4 + 2 N = 0 (2 N ) For example: 37N 5 + 7N 2 2N + 1 starting with the smallest term, as N increases the 1 become insignificant, the same holds first for the N and then for the N 2. The 37N 5 remains The multiplicative constant is neglected. The expression is 0(N 5 ) 7. c. In an embedded application what is meant by the term response time? Through put? memory loading? time loading. (06 Marks) Ans: Response Time: Response time is the interval between an event and the completion of the associated action. For example, one might issue a command to an A/D to make reading and receive an event from the A/D signifying completion of the task. More accurately, however, response time is driven by the types of system involved. For example, the time between issuing a command to an A/D to make a reading and receiving the event from the A/D signifying a completion of the task. Time Loading: Time loading is the percentage of time that the cpu is doing useful work. Useful work means execution of those task for which the embedded program has been designed. 4-Model Question paper I.indd 103
June 13 - M.P. 1 Memory loading: Memory loading is defined as the percentage of usable memory being devoted to that application. 8. a. List and explain most commonly used models in tools like VHDL. (12 Marks) Ans: The most commonly used models are as follows. System Level Model: The system level model is described by a hierachical and structural model and sented by a set of communicating functions or processes. Typically the functions specified using a behavioral model. Functional Model: A functional model expresses the system as a collection of functions. Its structure archival and graphical, and it describes a system by a set of interacting functional elements. The behaviour of each elements is independent of any future hardware or implementations. Physical model: The physical model describes the architectural structure of the system based on responents and their interactions. Structural Model: A structural model specifies the organization of the system based on the components system and the interconnections among them. It includes both functional and physical elements and the mapping between them. The model binds the functional to the and can be used at any level of abstraction. Behavioral model: There are a wide variety of models in this category. As noted earlier such a model is based on symbol to represent qualitative aspects, and behavior is frequency express a function of time. DATA Model: A data model or entity relation model represents the world in terms of entities and attributes and the relations between / among them. 8. b. Give the brief note on Co routine. (08 Marks) Ans: Control Procedure Procedure 0 Procedure 1 The Co routine Co routine is a special kind of procedure all in which there is a mutual call exchange between cooperating procedures that is two procedures sharing time. The mechanics are the same as the simple procedure call and so is the time budget. The major difference is that a conventional procedure executes until the end unless it leaves under extraordinary circumstances. Co routines exit and return throughout the body of the procedure. Usually, this is executed under the direction of a third process or procedure. Graphically the process appears as shown n figure. The control procedure starts the process. Each context switch is determined by an of the following. Control procedure External even a timing signal Internal even a data value The process continues until both procedures are completed. With each switch the appropriate information from the current context must be saved. Such activities incur a significant time burden. If such a construct is used in a time constrained context, then one must permit preemption as appropriate. The co routine sequence is analyzed exactly as was done with the procedure call. 4-Model Question paper I.indd 104