Enhanced Serial Peripheral Interface (espi) ECN

Similar documents
Enhanced Serial Peripheral Interface (espi)

Intel Desktop Board DZ68DB

SDLC INTELLECTUAL PROPERTY POLICY

Intel Cache Acceleration Software for Windows* Workstation

NOOTRY TERMS OF SERVICE

Intel 848P Chipset. Specification Update. Intel 82848P Memory Controller Hub (MCH) August 2003

HYCU SCOM Management Pack for F5 BIG-IP

Terms of Use. Changes. General Use.

LED Manager for Intel NUC

Intel RealSense Depth Module D400 Series Software Calibration Tool

1. License Grant; Related Provisions.

EMPLOYER CONTRIBUTION AGREEMENT

Revised 10/15/2014 WEBSITE TERMS OF USE

Intel G31/P31 Express Chipset

Terms Of Use AGREEMENT BETWEEN USER AND DRAKE MODIFICATION OF THESE TERMS OF USE LINKS TO THIRD PARTY WEB SITES USE OF COOKIES

Intel Desktop Board DP67DE

LOGO LICENSE AGREEMENT(S) CERTIPORT AND IC³

End User License Agreement

TERMS OF SERVICE. Maui Lash Extensions All Rights Reserved.

Intel Desktop Board DH61SA

SUPPORT MATRIX. HYCU OMi Management Pack for Citrix

Network-MIDI Driver Installation Guide

Intel Desktop Board DH55TC

Intel Desktop Board DG41CN

Intel Desktop Board D945GCLF2

How to Create a.cibd File from Mentor Xpedition for HLDRC

DEMO MANUAL DC2645A LTC MHz to 9GHz High Linearity I/Q Demodulator with Wideband IF Amplifier DESCRIPTION BOARD PHOTO

How to Create a.cibd/.cce File from Mentor Xpedition for HLDRC

Oracle Technology Network Developer License Terms for Java Card Classic Edition and Java Card Connected Edition Specifications

Intel 852GME/852PM Chipset Graphics and Memory Controller Hub (GMCH)

Ecma International Policy on Submission, Inclusion and Licensing of Software

Intel 945(GM/GME)/915(GM/GME)/ 855(GM/GME)/852(GM/GME) Chipsets VGA Port Always Enabled Hardware Workaround

CA File Master Plus. Release Notes. Version

Intel Desktop Board D945GCCR

Oracle Binary Code License Agreement for Java Secure Sockets Extension for Connected Device Configuration 1.0.2

FLUENDO GENERIC EULA

FOR TCG ACPI Specification

fontseek.info outofthedark.xyz

Intel Desktop Board DP55SB

Evolving Small Cells. Udayan Mukherjee Senior Principal Engineer and Director (Wireless Infrastructure)

DME-N Network Driver Installation Guide for M7CL

HUAWEI H30-U10. Quick Start Guide

Intel Desktop Board D946GZAB

INTEL PERCEPTUAL COMPUTING SDK. How To Use the Privacy Notification Tool

The Travel Tree Terms and Conditions

Intel Desktop Board DH61CR

TERMS OF USE Effective Date: January 1, 2015 To review material modifications and their effective dates scroll to the bottom of the page. 1.Parties.

Apple Inc. itunes 10 and QuickTime 7 Bundling Agreement (University CD Distribution) Licensee (Institution Name): Individual to Contact:

Native route discovery algorithm

End User License Agreement

CALSTRS ONLINE AGREEMENT TERMS AND CONDITIONS

Mobile Banking and Mobile Deposit Terms & Conditions

Intel 82580EB/82580DB GbE Controller Feature Software Support. LAN Access Division (LAD)

Oracle Technology Network Developer License Terms for Java Card Classic Edition and Java Card Connected Edition Software Development Kits

Intel Desktop Board DG31PR

Funding University Inc. Terms of Service

Intel Desktop Board D945GCLF

Intel Desktop Board D102GGC2 Specification Update

Bar Code Discovery. Administrator's Guide

Intel Desktop Board DG41RQ

Intel Server Board S2600CW2S

Oracle Binary Code License Agreement for the Java SE Platform Products and JavaFX

SUPPORT MATRIX. Comtrade OMi Management Pack for Citrix

Intel RealSense D400 Series Calibration Tools and API Release Notes

BCDC 2E, 2012 (On-line Bidding Document for Stipulated Price Bidding)

DCMI Data Center Manageability Interface Specification v1.0, Revision 1.0. Addenda, Errata, and Clarifications

VSC-PCTS2003 TEST SUITE TIME-LIMITED LICENSE AGREEMENT

Intel & Lustre: LUG Micah Bhakti

Intel Desktop Board D845PT Specification Update

Intel Cluster Ready Allowed Hardware Variances

Intel Server Board S2600STB

FONT SOFTWARE END USER LICENSE AGREEMENT. We recommend that you print this Font Software End User License Agreement for further reference.

Intel Desktop Board D975XBX2

MOTIF-RACK XS Editor VST Installation Guide

Daniel MeterLink Software v1.40

Upgrading MYOB BankLink Notes (desktop)

Migration Guide: Numonyx StrataFlash Embedded Memory (P30) to Numonyx StrataFlash Embedded Memory (P33)

Device Firmware Update (DFU) for Windows

MERIDIANSOUNDINGBOARD.COM TERMS AND CONDITIONS

IETF TRUST. Legal Provisions Relating to IETF Documents. Approved November 6, Effective Date: November 10, 2008

QUARTZ LEGAL TERMS AND CONDITIONS

Sample for OpenCL* and DirectX* Video Acceleration Surface Sharing

INCLUDING MEDICAL ADVICE DISCLAIMER

Innovating and Integrating for Communications and Storage

SafeNet Authentication Client

SafeNet Authentication Client

Mile Terms of Use. Effective Date: February, Version 1.1 Feb 2018 [ Mile ] Mileico.com

TERMS OF USE. 1.3 This Site is intended for personal use only. Any commercial use without the prior written consent of Eretz Hemdah is prohibited.

SIMS TERMS AND CONDITIONS OF USE AGREEMENT

Embedded and Communications Group January 2010

Intel Atom Processor E3800 Product Family Development Kit Based on Intel Intelligent System Extended (ISX) Form Factor Reference Design

Intel Desktop Board DQ57TM

Intel Core TM i7-4702ec Processor for Communications Infrastructure

OpenCL* and Microsoft DirectX* Video Acceleration Surface Sharing

Ecma International Policy on Submission, Inclusion and Licensing of Software

TERMS & CONDITIONS. Complied with GDPR rules and regulation CONDITIONS OF USE PROPRIETARY RIGHTS AND ACCEPTABLE USE OF CONTENT

Evaluation Board User Guide UG-163

Software Evaluation Guide for ImTOO* YouTube* to ipod* Converter Downloading YouTube videos to your ipod

Webfont License End User License Agreement (EULA)

Theory and Practice of the Low-Power SATA Spec DevSleep

Transcription:

Enhanced Serial Peripheral Interface (espi) ECN Engineering Change Notice TITLE Clarify OOB packet payload DATE 10 January 2014 AFFECTED DOCUMENT espi Base Specification Rev 0.75 DISCLOSURE RESTRICTIONS CNDA or espi Click to Accept License Agreement espi Engineering Change Notice

Intel hereby grants you a fully-paid, non-exclusive, non-transferable, worldwide, limited license (without the right to sublicense), under its copyrights to view, download, and reproduce the Enhanced Serial Peripheral Interface (espi) Specification ("Specification"). You are not granted any other rights or licenses, by implication, estoppel, or otherwise, and you may not create any derivative works of the Specification. The Specification is provided "as is," and Intel makes no representations or warranties, express or implied, including warranties of merchantability, fitness for a particular purpose, non-infringement, or title. Intel is not liable for any direct, indirect, special, incidental, or consequential damages arising out of any use of the Specification, or its performance or implementation. Intel retains ownership of all of its intellectual property rights in the Specification and retains the right to make changes to the Specification at any time. No license is granted to use Intel s name, trademarks, or patents. If you provide feedback or suggestions on the Specification, you grant Intel a perpetual, non-terminable, fully-paid, nonexclusive, worldwide license, with the right to sublicense, under all applicable intellectual property rights to use the feedback and suggestions, without any notice, consent, or accounting. You represent and warrant that you own, or have sufficient rights from the owner of, the feedback and suggestions, and the intellectual property rights in them, to grant the above license. This agreement is governed by Delaware law, without reference to choice of law principles. Any disputes relating to this agreement must be resolved in the federal or state courts in Delaware and you consent, and will not object, to the exclusive personal jurisdiction of the courts in Delaware. This agreement is the entire agreement of the parties regarding the Specification and supersedes all prior agreements or representations. This agreement is hosted at the following location http//downloadcenter.intel.com/detail_desc.aspx?agr=y&dwnldid=21353 THIS SIFICATION IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SIFICATION, OR SAMPLE. Except for a limited copyright license to copy this specification for internal use only, no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel Corporation and the authors of this specification disclaim all liability, including liability for infringements of proprietary rights, relating to implementation of information in this document and the specification. Intel Corporation and the authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights. Implementations developed using the information provided in this specification may infringe the patent rights of various parties including the parties involved in the development of this specification. Except as expressly granted hereunder, no license, express or implied, by estoppel or otherwise, to any intellectual property rights (including without limitation rights under any party s patents) is granted. All suggestions or feedback related to this specification become the property of Intel Corporation upon submission. Intel may make changes to the specifications, product descriptions, and plans at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document is an intermediate draft for comment only and is subject to change without notice. Do not finalize a design based on this document. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others. Copyright 2013, Intel Corporation. All rights reserved. 2 espi Engineering Change Notice

ECN Motivation espi Base Specification 0.75 defines the transaction packet format for the Out-of- Band (OOB) Message channel. Feedback has been received on the spec clarification related to payload definition for the Out-of-Band (OOB) Message transactions. This ECN is to clarify the packet length field, the Byte Count field and the effect of the Maximum Payload Size (MPS) for the OOB transaction packets. The ECN provides clarity for the and the generic block write packets on the espi OOB Message channel. espi Engineering Change Notice 3

ECN Description espi Base Specification 0.75 is clarified with the following 5.1.3 Length For Flash Write and OOB message with data, data payload size must not exceed the Maximum Payload Size of the respective channel with no alignment requirement. The data payload of the OOB message affected by the Maximum Payload Size is the actual payload of the protocol embedded in the message itself. Refer to Section 5.2.3 for the OOB message payload. 5.2.3 OOB (Tunneled ) Message Channel The packets can be tunneled through espi as Out-Of-Band (OOB) messages. The whole packet is embedded inside the espi OOB message as data. Only block writes are tunneled through the espi OOB message. These include the Management Component Transport Protocol () packets which are based on the block write protocol. The Slave Address, Command Opcode, Byte Count, and fields and the optional byte are sent as data within the espi OOB message packet. The Byte Count field does not include the byte. It comprehends the actual payload of the block write packet message itself (up to the Maximum Payload Size), excluding the 3 header bytes of the Command Opcode. The Length field of the OOB message comprehends the count by the Byte Count field, in addition to the 3 header bytes (i.e. Slave Address, Command Opcode and Byte Count) and an optional byte. The presence of is determined through a simple arithmetic operation between the espi OOB header length field and the Byte Count. The Maximum Payload Size (MPS) for OOB Message channel applies to the actual payload of the protocol embedded in the packet that tunneled through the channel, such as but not limited to the and the generic block writes. 4 espi Engineering Change Notice

Figure 45(a) OOB (Tunneled ) Message Packet Format 7 6 5 4 3 2 1 0 Cycle Type 7 6 5 4 3 2 1 0 Cycle Type Byte 1 Length[118] Byte 1 Length[118] Byte 2 Length[70] Byte 2 Length[70] Byte 3 Byte 3 Slave Address 0 Byte 4 Byte N Packet Format Byte 4 Byte 5 Byte n+6 Command Opcode Byte Count Byte n Byte n+7 over is a specific form of the block write packet with the Command Opcode of 0Fh (i.e. ). The header and payload are embedded as the block write data bytes. For espi OOB packet, the Maximum Payload Size (MPS) applies to the payload itself excluding the header and the optional byte. For example, MPS of 64 bytes allows the transfer of a packet with up to 64 bytes payload over the OOB Message channel. In the case of 64 bytes payload with the optional byte, the byte count field and the OOB header length field are 69 bytes and 73 bytes respectively. espi Engineering Change Notice 5

Figure 45(b) OOB Packet 7 6 5 4 3 2 1 0 OOB with Max Payload Size (MPS) = 64 bytes for a 64 bytes packet (with byte) Cycle Type Byte 1 Byte 2 Length[70] Length[118] OOB Length = (3+5+64+1) = 73 bytes Byte 3 Byte 4 Byte 5 Destination Slave Address Command Code = = 0Fh Byte Count 0 Byte Count = (5+64) = 69 bytes (3 bytes) Byte 6 Source Slave Address 1 Note byte is excluded Byte 7 Byte 8 Byte 9 Byte 10 Byte 11 Byte n+11 Byte n+12 S O M Reserved Version Destination Endpoint ID E O M Source Endpoint ID Packet Seq # T O Message Payload Byte n Message OOB Block Write Bytes (5 bytes) Payload (64 bytes) (5 bytes) Payload (64 bytes) (1 byte) For espi OOB generic block write packet, the Maximum Payload Size (MPS) applies to the number of block write data bytes allowed in a packet excluding the optional byte. For example, MPS of 64 bytes allows the transfer of a generic block write packet with up to 64 bytes data payload over the OOB Message channel. In the case of 64 bytes data payload with the optional byte, the byte count field and the OOB header length field are 64 bytes and 68 bytes respectively. 6 espi Engineering Change Notice

Figure 45(c) OOB Generic Block Write Packet 7 6 5 4 3 2 1 0 Cycle Type OOB with Max Payload Size (MPS) = 64 bytes for a 64 bytes generic Block Write packet (with byte) Byte 1 Length[118] OOB Byte 2 Length[70] Length = (3+64+1) = 68 bytes Byte 3 Byte 4 Byte 5 Slave Address Command Opcode Byte Count 0 Byte Count = 64 bytes (3 bytes) Byte 6 Byte n+6 Byte n+7 Payload Byte n OOB Block Write Bytes Note byte is excluded Payload (64 bytes) Payload (64 bytes) (1 byte) 7.2.1.6 Offset 30h Channel 2 Capabilities and Configurations Bit Type Default Description OOB Message Channel Maximum Payload Size Selected espi master sets the Maximum Payload Size (MPS) for the OOB Message channel. The value set by the espi master must never be more than the value advertised in the Max Payload Size Supported field. 108 RW 001b The MPS applies to the actual payload of the protocol embedded in the OOB packet. Refer to Section 5.2.3 for the detail of the OOB message payload. 000b Reserved. 001b 64 bytes max payload size. 010b 128 bytes max payload size. 011b 256 bytes max payload size. 100b 111b Reserved. espi Engineering Change Notice 7

OOB Message Channel Maximum Payload Size Supported This field advertises the Maximum Payload Size (MPS) supported by the slave. 64 RO HwInit The MPS applies to the actual payload of the protocol embedded in the OOB packet. Refer to Section 5.2.3 for the detail of the OOB message payload. 000b Reserved. 001b 64 bytes max payload size. 010b 128 bytes max payload size. 011b 256 bytes max payload size. 100b 111b Reserved. 8 espi Engineering Change Notice