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INFORMATICA INDUSTRIALE Lezione 2 Prof. Christian Forlani forlani@disco.unimib.it Tutor: Stefano Brusamolino brusamolino@ira.disco.unimib.it

Device Structure: Core» Oscillator» Reset» Architecture» CPU (Central Processing Unit) and System Bus» ALU (Arithmetic Logical Unit)» Hardware 8x8 Multiplier» Memory Map» Table Read / Table Write» System Bus» Interrupts» Instruction Set Lezione 2 2

Architecture PIC Lezione 2 3

Instruction/Data size Data Size (8 bit) Data Memory (8bit) Instruction Size (Word, Double Word:16,32 bit) Program Memory (8bit) Lezione 2 4

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General Instruction Format Lezione 2 8

General Instruction Format Lezione 2 9

Device Structure: Core» Oscillator» Reset» Architecture» CPU (Central Processing Unit) & System Bus» ALU (Arithmetic Logical Unit)» Hardware 8x8 Multiplier» Memory Map» Table Read / Table Write» System Bus» Interrupts» Instruction Set Lezione 2 10

ALU (Arithmetic Logical Unit) Lezione 2 11

Status Register N =Negative bit OV=Overflow bit Z =Zero bit DC=Digit Carry (Half Carry) C =Carry Lezione 2 12

8X8 HW multiplier included in the ALU Lezione 2 14

Program & Data Memory Lezione 2 16

Program Memory Map Lezione 2 17

Program Counter (PC) Lezione 2 18

Data Memory Map Lezione 2 19

Access Bank Si accede quando a=0 E una zona di memoria ad accesso veloce formata dai primi 128byte del Bank0 (GPR) e gli ultimi 128 del Bank15 (SFRs) ed è utilizzata per: Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) Lezione 2 20

Table Write E una tabella che permette il trasferimento di dati dalla Data Memory alla Program Memory. NB: Per i dispositivi con memoria EPROM, i bit della Program Memory possono essere portati da 1 a 0 ma non viceversa!! Lezione 2 22

Table Read E una tabella che permette il trasferimento di dati dalla Program Memory alla Data Memory. Lezione 2 23

Reset Control (RCON) register LWRT: Long Write Enable bit 1 = Enable Table Writes to internal program memory Once this bit is set, it can only be cleared by a POR or MCLR reset. 0 = Disable Table Writes to internal program memory; Table Writes only to external program memory. Lezione 2 24

Interrupts Interrupts can come from many sources. These sources currently include: External interrupt from the INT, INT1, and INT2 pins Change on RB7:RB4 pins TMR0,1,2,3Overflow USART Interrupts Receive buffer full Transmit buffer empty SSPInterrupt SSP I 2 C bus collision interrupt A/D conversion complete CCP interrupt LVD Interrupt Parallel Slave Port CAN interrupts Receive 1,2 buffer Receive invalid Transmit 1,2,3 buffer Bus wakeup Bus invalid error Lezione 2 26

Interrupts As other peripheral modules are developed, they will have interrupt sources. These sources will map into the 10 registers used in the control and status of interrupts. These registers are: INTCON INTCON1 INTCON2 INTCON3 PIR1 PIR2 PIE1 PIE2 IPR1 IPR2 The INTCON register contains the GIE/GIEH bit. This is the Global Interrupt Enable bit. When this bit is set, all interrupts are enabled. If needed for any single device, additional INTCON, PIR,PIE, and IPR registers will be defined. Lezione 2 27

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High Priority Interrupt Logic Block Lezione 2 29

Low Priority Interrupt Logic Block Lezione 2 30

Interrupt Registers:INTCON Lezione 2 31

Interrupt Registers:INTCON2 Lezione 2 32

Interrupt Registers:INTCON3 Lezione 2 33

Peripheral Interrupt Enable: PIE Lezione 2 34

Peripheral Interrupt Registers: PIR Lezione 2 35

Interrupt Priority Registers: IPR Lezione 2 36

Peripheral Interrupt Registers: PIR Lezione 2 37

Reset Control (RCON) register IPEN: Interrupt Priority Enable bit 1 = Enable priority levels (high and low) on interrupts 0 = Disable priority levels (all peripherals are high) on interrupts (This causes the Interrupt Priority (IP) bits to be ignored) Lezione 2 38

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