Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

Similar documents
Specifying logic functions

Simplification of two-level combinational logic

Chapter 2. Boolean Expressions:

DKT 122/3 DIGITAL SYSTEM 1

Gate Level Minimization Map Method

Simplification of Boolean Functions

University of Technology

Gate Level Minimization

Chapter 3. Gate-Level Minimization. Outlines

CprE 281: Digital Logic

ELCT201: DIGITAL LOGIC DESIGN

CS8803: Advanced Digital Design for Embedded Hardware

ELCT201: DIGITAL LOGIC DESIGN

Chapter 6. Logic Design Optimization Chapter 6

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Simplification of Boolean Functions

Experiment 4 Boolean Functions Implementation

Digital logic fundamentals. Question Bank. Unit I

Combinational Logic Circuits Part III -Theoretical Foundations

IT 201 Digital System Design Module II Notes

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Combinational Logic & Circuits

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.

Experiment 3: Logic Simplification

Combinational Circuits Digital Logic (Materials taken primarily from:

1. Mark the correct statement(s)

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil


Module -7. Karnaugh Maps

Chapter 2: Combinational Systems

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

2.6 BOOLEAN FUNCTIONS

SWITCHING THEORY AND LOGIC CIRCUITS

Combinational Logic Circuits

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Combinational Logic Circuits

R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

Code No: 07A3EC03 Set No. 1

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions

Chapter 3 working with combinational logic

Unit-IV Boolean Algebra

Gate-Level Minimization

ECE380 Digital Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

EECS Components and Design Techniques for Digital Systems. Lec 07 PLAs and FSMs 9/ Big Idea: boolean functions <> gates.

QUESTION BANK FOR TEST

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

TWO-LEVEL COMBINATIONAL LOGIC

CMPE223/CMSE222 Digital Logic

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

A B AB CD Objectives:

2008 The McGraw-Hill Companies, Inc. All rights reserved.

Chapter 2 Combinational Logic Circuits

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Gate-Level Minimization

4 KARNAUGH MAP MINIMIZATION

BOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.

Gate-Level Minimization

X Y Z F=X+Y+Z

(Refer Slide Time 6:48)

Digital Logic Design (CEN-120) (3+1)

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

Standard Forms of Expression. Minterms and Maxterms

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)

Summary. Boolean Addition

ece5745-pla-notes.txt

DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

Lecture 22: Implementing Combinational Logic

UNIT II. Circuit minimization

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION

Digital Logic Lecture 7 Gate Level Minimization

Chapter 2 Combinational

DIGITAL ELECTRONICS. P41l 3 HOURS

Ch. 5 : Boolean Algebra &

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure

Computer Science. Unit-4: Introduction to Boolean Algebra

Chapter 3 Simplification of Boolean functions

Question Total Possible Test Score Total 100

2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

Gate-Level Minimization

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

10EC33: DIGITAL ELECTRONICS QUESTION BANK

Propositional Calculus. Math Foundations of Computer Science


VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007

Code No: R Set No. 1

Homework. Update on website issue Reading: Chapter 7 Homework: All exercises at end of Chapter 7 Due 9/26

MODULE 5 - COMBINATIONAL LOGIC

Transcription:

Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

Incompletely specified functions Example: Fruit Detector at Fruit Factory To distinguish Round Fruits (X = 1) from Odd Shaped Fruits (X = 0) Three input signals! Intuition tells us that X = C!! Check this out algebraically

Review of DeMorgan s Laws DeMorgan s Law: (a + b) = a b (a b) = a + b a + b = (a b ) (a b) = (a + b ) = = = = push bubbles or introduce in pairs or remove pairs

Transformation to Simple Gates Sum of Products Involution: x = (x ) = De Morgans

Implementations of Two-level Logic Sum-of-products AND gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product

Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate

Two-level Logic using NAND Gates (cont d) OR gate with inverted inputs is a NAND gate de Morgan's: A'+ B'= (A B)' Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

Two-level Logic using NOR Gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate

Two-level Logic using NOR Gates (cont d) AND gate with inverted inputs is a NOR gate de Morgan's: A' B'= (A + B)' Two-level NOR-NOR network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

Another look at simplification Key tool to simplification: A (B'+ B) = A Essence of simplification of two-level logic Find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements ())*)(+)*,)() "#$% & ''"% % &

Boolean cubes Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube Neighbors address differs by one bit flip

Hamming Distance Number of Bit Differences Note Hamming distance between the numbers in the figures

Mapping truth tables onto Boolean cubes Uniting theorem combines two "faces" of a cube into a larger "face" Example: % ''/+, #''/ +, "% '0 ') $( $( - $( )

Three variable example Binary full-adder carry-out logic +)*, +)*, +*), $ -"#- #+ 1,'## '% -$ 2 3 " (**

Higher dimensional cubes Sub-cubes of higher dimension than 2 +00,(Σ +4050607, % 8 9 $' : 0#' ; <"# 0= & ; +, "- > ## 9+00,= Σm(Decimal list of min terms) = Π M(Decimal list of MAX terms)

m-dimensional cubes in a n- dimensional Boolean space In a 3-cube (three variables): 0-cube, ie, a single node, yields a term in 3 literals 1-cube, ie, a line of two nodes, yields a term in 2 literals 2-cube, ie, a plane of four nodes, yields a term in 1 literal 3-cube, ie, a cube of eight nodes, yields a constant term "1" In general, m-subcube within an n-cube (m < n) yields a term with n m literals

Karnaugh maps Flat map of Boolean cube Wrap around at edges Hard to draw and visualize for more than 4 dimensions Virtually impossible for more than 6 dimensions Alternative to truth-tables to help visualize adjacencies Guide to applying the uniting theorem On-set elements with only one variable changing value are adjacent unlike the situation in a linear truth-table ; =

Karnaugh maps (cont d) Numbering scheme based on Gray code eg, 00, 01, 11, 10 2 n values of n bits where each differs from next by one bit flip» Hamiltonian circuit through n-cube Only a single bit changes in code for adjacent map cells ; = ; = 6 4 7 5 6 4 7 5 4 5 = 7 ; 6 ;? = @ 5 4 =( (A

Adjacencies in Karnaugh maps Wrap from first to last column Wrap top row to bottom row

Karnaugh map examples F = Cout = f(a,b,c) = Σm(0,4,6,7) A ** *AA *A # '' #-" % # #

More Karnaugh map examples +00,( +00,(Σ +040507, (*AA ) - )% )"" )+00,(Σ + 0;0=06, (A*A

K-map: 4-variable interactive quiz F(A,B,C,D) = Σm(0,2,3,5,6,7,8,10,11,14,15) F = ' #'# ## " $ +'% % '%,

Karnaugh map: 4-variable example F(A,B,C,D) = Σm(0,2,3,5,6,7,8,10,11,14,15) F = *A *AA ' #'# ## " $ +'% % '%,

Karnaugh maps: don t cares f(a,b,c,d) = Σ m(1,3,5,7,9) + d(6,12,13) without don't cares» f = A *AA

Karnaugh maps: don t cares (cont d) f(a,b,c,d) = Σ m(1,3,5,7,9) + d(6,12,13) f = A'D + B'C'D without don't cares f = with don't cares #-)B B ;$##' $#" ) # % "

Design example: two-bit comparator ; E> F > #D # G ( H E> F > % )4$"#C ''='

Design example: two-bit comparator (cont d) C$ 'E> C$ ' F C$ ' > E> ( F ( > ( ))*)*) ))))*))**)A ))*)*) (+<,I+<, Canonical PofS vs minimal? E> > +'JJ,

Design example: two-bit comparator (cont d) % " ' F % % 1 1 % =

Design example: 2x2-bit multiplier ; ; #D # ; 4? ; ;? 4 ; 4$"#C$ ''4 '

Design example: 2x2-bit multiplier (cont d) ; C$ '? C$ '4 4(;; ) *; ); ; ;?(; ; ; ; C$ '; C$ ' ( ; ; ; (;) ; * ; ) *;;) *; ) ;

Design example: BCD increment by 1 K K; K4 K? #D # ; 4? K? K4 K; K? 4 ; 4$"#C$ '' 4'

Design example: BCD increment by 1 (cont d) K?? 4 K? K; K4 K? K ;?(K4K;K *K?K ) 4(K4K;)*K4K )*K4AK;K ;(K?AK;AK *K;K ) (K ) K; K4 K? K K K K; K; K4 K4

Definition of terms for two-level simplification Implicant Single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube Prime implicant Implicant that can't be combined with another to form a larger subcube Essential prime implicant Prime implicant is essential if it alone covers an element of ON-set Will participate in ALL possible covers of the ON-set DC-set used to form prime implicants but not to make implicant essential Objective: Grow implicant into prime implicants (minimize literals per term) Cover the ON-set with as few prime implicants as possible (minimize number of product terms)

Examples to illustrate terms 6 L 00000 "L* * 5 L 0000 "L4

Algorithm for two-level simplification Algorithm: minimum sum-of-products expression from a Karnaugh map Step 1: choose an element of the ON-set Step 2: find "maximal" groupings of 1s and Xs adjacent to that element» consider top/bottom row, left/right column, and corner adjacencies» this forms prime implicants (number of elements always a power of 2) Repeat Steps 1 and 2 to find all prime implicants Step 3: revisit the 1s in the K-map» if covered by single prime implicant, it is essential, and participates in final cover» 1s covered by essential prime implicant do not need to be revisited Step 4: if there remain 1s not covered by essential prime implicants» select the smallest number of prime implicants that cover the remaining 1s

Algorithm for two-level simplification (example)

Summary Boolean Algebra provides framework for logic simplification Binary Cubes and Karnaugh maps provide visual notion of simplifications Algorithm for producing reduced form