Review: minimum sum-of-products expression from a Karnaugh map EECS 5 - Components and Design Techniques for Digital Systems Lec 7 PLAs and FSMs 9/2- David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs5 Step : choose an element of the ON-set Step 2: find "maximal" groupings of s and Xs adjacent to that element consider top/bottom row, left/right column, and corner adjacencies this forms prime implicants (number of elements always a power of 2) Repeat Steps and 2 to find all prime implicants Step 3: revisit the s in the K-map if covered by single prime implicant, it is essential, and participates in final cover s covered by essential prime implicant do not need to be revisited Step : if there remain s not covered by essential prime implicants select the smallest number of prime implicants that cover the remaining s 9/2/ EECS5 F Culler 9/2/ EECS5 F Culler 2 Big Idea: boolean functions <> gates 2 2^n boolean functions of n inputs Each represented uniquely by a Truth Table Describes the mapping of inputs to outputs Each boolean function represented by many boolean expressions Axioms establish equivalence Transform expressions to optimize Each boolean expression has many implementations in logic gates Canonical: Sum of Products, Product of Sums Minimal K-maps as a systematic means of reducing Sum of Products Any acyclic network of gates implements a boolean function Outline Programmable to Implement Sum of Products Designing with PLAs Announcements FSM Concept Example: history sensitive computation Example: Combo lock Encodings and implementations 9/2/ EECS5 F Culler 3 9/2/ EECS5 F Culler One Answer: Xilinx CLB How to quickly implement SofPs? 9/2/ EECS5 F Culler 5 9/2/ EECS5 F Culler 6
Two -input functions, registered output 5-input function, combinational output 9/2/ EECS5 F Culler 7 9/2/ EECS5 F Culler 8 Programmable Regular logic Programmable Arrays Multiplexers/Decoders ROMs Field Programmable Gate Arrays (FPGAs) Xilinx Programmable Arrays (PLAs) Pre-fabricated building block of many AND/OR gates Actually NOR or NAND Personalized" by making or breaking connections among gates Programmable array block diagram for sum of products form 9/2/ EECS5 F Culler 9 9/2/ EECS5 F Culler Shared Product Terms Before Programming! " All possible connections available before "programming" In reality, all AND and OR gates are NANDs! " $ 9/2/ EECS5 F Culler 9/2/ EECS5 F Culler 2
After Programming Unwanted connections are "blown" Fuse (normally connected, break unwanted ones) Anti-fuse (normally disconnected, make wanted connections) Alternate Representation for High Fan-in Structures Short-hand notation--don't have to draw all the wires Signifies a connection is present and perpendicular signal is an input to gate $% 9/2/ EECS5 F Culler! " 3 9/2/ EECS5 F Culler Programmable Array Example Multiple functions of A, B, C F = A B C F2 = A + B + C F3 = A' B' C' F = A' + B' + C' F5 = A xor B xor C F6 = A xnor B xnor C $$ )!"&'(! "&' ( 9/2/ EECS5 F Culler 5 PLAs Design Example BCD to Gray code converter, -. /$, /$ PLAs Design Example (cont d) Code converter: programmed PLA +$, -. % $2 3% 3563 % 33 % 9/2/, - EECS5. F Culler 7 PLAs Design Example (revisited) BCD to Gray code converter, -. +$, -. /$- /$. 9/2/ EECS5 F Culler 6 +$, -. /$- /$. 9/2/ EECS5 F Culler 8 /$, /$
PLAs Design Example PLA Second Design Example BCD to Gray code converter Magnitude comparator, -. +$, -. /$- /$. 9/2/ EECS5 F Culler 9 /$, /$ /$78 /$7 /$29 /$:9 9/2/ EECS5 F Culler 78 7 29 :9 2 Other Options Muxes DeMuxes ROMs LUTs Announcements Reading: Katz..2 (again), 7.-3, pp 7-86 Mid term th /7 We will return to these later 9/2/ EECS5 F Culler 2 9/2/ EECS5 F Culler 22 Recall: What makes Digital Systems tick? Recall 6C: Single-Cycle MIPS PC + instruction memory x 3 imm registers 7 reg[] ALU reg[]+7 Data memory MEM[r+7] clk time. Instruction Fetch LW r3, 7(r) 2. Register Read 3. Execute. Memory 5. Reg. Write 9/2/ EECS5 F Culler 23 9/2/ EECS5 F Culler 2
Recall 6C: 5-cycle Datapath - pipeline PC + instruction memory x 3 IR imm registers 7 reg[] ALU reg[]+7 Data memory MEM[r+7] Typical Controller: Next i2 i i o2 o o. Instruction Fetch LW r3, 7(r) 2. Register Read 3. Execute 5. Reg.. Memory Write Example: Gray Code (t+) = F ( (t) ) Sequence 9/2/ EECS5 F Culler 25 9/2/ EECS5 F Culler 26 Typical Controller: + output Typical Controller: + output + input Output (t) = G( (t) ) Next Output (t) = G( (t) ) Next i2 i i o2 o o odd Input clr i2 i i o2 o o odd (t+) = F ( (t) ) (t+) = F ( (t), input (t) ) clr= x x x / / / / / / / / 9/2/ EECS5 F Culler 27 / / / / / / / / clr= clr=? 9/2/ EECS5 F Culler 28 Two Kinds of FSMs Moore Machine vs Mealy Machine Output (t) = G( (t)) Input Input Output (t) = G( (t), Input ) Parity Checker Example A string of bits has even parity if the number of s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a if the parity thus far is even and outputs a if odd: bit stream IN CLK Parity Checker OUT if even parity if odd parity example: even even odd even odd odd even CLK time (t+) = F ( (t), input(t)) (t+) = F ( (t), input) Input / Out Input State State / out 9/2/ EECS5 F Culler 29 IN OUT Can you guess a circuit that performs this function? 9/2/ EECS5 F Culler 3
Formal Design Process bit stream IN CLK Parity Checker OUT State Transition Diagram circuit is in one of two s. transition on each cycle with each new input, over exactly one arc (edge). Output depends on which the circuit is in. if even parity if odd parity example: even even odd even odd odd even time 9/2/ EECS5 F Culler 3 Formal Design Process State Transition Table: present next OUT IN EVEN EVEN EVEN ODD ODD ODD ODD EVEN Invent a code to represent s: Let = EVEN, = ODD present (ps) OUT IN next (ns) Derive logic equations from table (how?): OUT = PS NS = PS xor IN 9/2/ EECS5 F Culler 32 Formal Design Process equations from table: OUT = PS NS = PS xor IN Circuit Diagram: ps ns Review of Design Steps:. Circuit functional specification 2. State Transition Diagram 3. Symbolic State Transition Table. Encoded State Transition Table 5. Derive Equations 6. Circuit Diagram FFs for XOR gate for ns calculation CL for NS and OUT DFF to hold present no logic needed for output 9/2/ EECS5 F Culler 33 Finite State Machines (FSMs) FSM circuits are a type of sequential circuit: output depends on present and past inputs» effect of past inputs is represented by the current Behavior is represented by State Transition Diagram: traverse one edge per clock cycle. 9/2/ EECS5 F Culler 3 FSM Implementation Another example Door combination lock: punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset inputs: sequence of input values, reset outputs: door open/close memory: must remember combination or always have it available as an input FFs form register number of s 2number of flip-flops CL (combinational logic) calculates next and output Remember: The FSM follows exactly one edge per cycle. 9/2/ EECS5 F Culler 35 9/2/ EECS5 F Culler 36
Implementation in software integer combination_lock ( ) { integer v, v2, v3; integer error = ; static integer c[3] = 3,, 2; while (!new_value( )); v = read_value( ); if (v!= c[]) then error = ; while (!new_value( )); v2 = read_value( ); if (v2!= c[2]) then error = ; while (!new_value( )); v3 = read_value( ); if (v2!= c[3]) then error = ; Implementation as a sequential digital system Encoding: how many bits per input value? how many values in sequence? how do we know a new input value is entered? how do we represent the s of the system? Behavior: clock wire tells us when it s ok to look at inputs (i.e., they have settled after change) sequential: sequence of values must be entered sequential: remember if an error occurred finite- specification < 5 } if (error == ) then return(); else return (); 9/2/ EECS5 F Culler 37 ; 9/2/ EECS5 F Culler 38 Sequential example: abstract control data-path vs. control Finite- diagram States: 5 s» represent point in execution of machine» each has outputs Transitions: 6 from to, 5 self transitions, global» changes of occur when clock says it s ok» based on value of inputs Inputs: reset, new, results of comparisons Output: open/closed >5!>5 ">5 5!5 "5 Internal structure data-path» storage for combination» comparators control» finite- machine controller» control for data-path» changes controlled by clock value comparator C C2 C3 multiplexer mux control new equal controller reset clock 9/2/ EECS5 F Culler 39 equal datapath open/closed 9/2/ EECS5 F Culler Sequential example (cont d): finite- machine Finite- machine refine diagram to include internal structure Sequential example (cont d): finite- machine Finite- machine generate table (much like a truth-table)????!? "? 9/2/ EECS5 F Culler Symbolic s????!? "? Encoding? 9/2/ EECS5 F Culler 2
Sequential example: encoding Encode table can be: S, S2, S3, OPEN, or ERR» needs at least 3 bits to encode:,,,,» and as many as 5:,,,,» choose bits:,,,, Encode outputs output mux can be: C, C2, or C3» needs 2 to 3 bits to encode» choose 3 bits:,, output open/closed can be: open or closed» needs or 2 bits to encode» choose bits:, binary hybrid One-hot 9/2/ EECS5 F Culler 3 Sequential example (cont d): encoding Encode table can be: S, S2, S3, OPEN, or ERR» choose bits:,,,, output mux can be: C, C2, or C3» choose 3 bits:,, output open/closed can be: open or closed» choose bits:,! " $!% & $ $ & $ 9/2/ EECS5 F Culler Sequential example (cont d): controller implementation Implementation of the controller One-hot encoded FSM Even Parity Checker Circuit: ' )!) $ &! " & ' &(! ' In General: FFs must be initialized for correct operation (only one ) 9/2/ EECS5 F Culler 5 9/2/ EECS5 F Culler 6 FSM Implementation Notes General FSM form: Often PLAs Design hierarchy +" All examples so far generate output based only on the present :!! &! Commonly called Moore Machine (If output functions include both present and input then called a Mealy Machine) 9/2/ EECS5 F Culler 7! "! '! 9/2/ EECS5 F Culler 8